1 /* arch/arm/plat-samsung/include/plat/uncompress.h
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C - uncompress code
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #ifndef __ASM_PLAT_UNCOMPRESS_H
15 #define __ASM_PLAT_UNCOMPRESS_H
17 typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
21 unsigned int fifo_mask;
22 unsigned int fifo_max;
24 /* forward declerations */
26 static void arch_detect_cpu(void);
28 /* defines for UART registers */
30 #include <plat/regs-serial.h>
31 #include <plat/regs-watchdog.h>
33 /* working in physical space... */
34 #undef S3C2410_WDOGREG
35 #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
37 /* how many bytes we allow into the FIFO at a time in FIFO mode */
41 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
44 static __inline__ void
45 uart_wr(unsigned int reg, unsigned int val)
47 volatile unsigned int *ptr;
49 ptr = (volatile unsigned int *)(reg + uart_base);
53 static __inline__ unsigned int
54 uart_rd(unsigned int reg)
56 volatile unsigned int *ptr;
58 ptr = (volatile unsigned int *)(reg + uart_base);
62 /* we can deal with the case the UARTs are being run
63 * in FIFO mode, so that we don't hold up our execution
64 * waiting for tx to happen...
67 static void putc(int ch)
69 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
73 level = uart_rd(S3C2410_UFSTAT);
83 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
87 /* write byte to transmission register */
88 uart_wr(S3C2410_UTXH, ch);
91 static inline void flush(void)
95 #define __raw_writel(d, ad) \
97 *((volatile unsigned int __force *)(ad)) = (d); \
100 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
102 static void arch_decomp_error(const char *x)
106 putstr("\n\n -- System resetting\n");
108 __raw_writel(0x4000, S3C2410_WTDAT);
109 __raw_writel(0x4000, S3C2410_WTCNT);
110 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
115 #define arch_error arch_decomp_error
118 #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
119 static inline void arch_enable_uart_fifo(void)
121 u32 fifocon = uart_rd(S3C2410_UFCON);
123 if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
124 fifocon |= S3C2410_UFCON_RESETBOTH;
125 uart_wr(S3C2410_UFCON, fifocon);
127 /* wait for fifo reset to complete */
129 fifocon = uart_rd(S3C2410_UFCON);
130 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
136 #define arch_enable_uart_fifo() do { } while(0)
141 arch_decomp_setup(void)
143 /* we may need to setup the uart(s) here if we are not running
144 * on an BAST... the BAST will have left the uarts configured
145 * after calling linux.
150 /* Enable the UART FIFOs if they where not enabled and our
151 * configuration says we should turn them on.
154 arch_enable_uart_fifo();
158 #endif /* __ASM_PLAT_UNCOMPRESS_H */