2 * We need constants.h for:
7 #include <asm/asm-offsets.h>
8 #include <asm/thread_info.h>
11 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
13 .macro vma_vm_mm, rd, rn
14 ldr \rd, [\rn, #VMA_VM_MM]
18 * vma_vm_flags - get vma->vm_flags
20 .macro vma_vm_flags, rd, rn
21 ldr \rd, [\rn, #VMA_VM_FLAGS]
25 ldr \rd, [\rn, #TI_TASK]
26 ldr \rd, [\rd, #TSK_ACTIVE_MM]
30 * act_mm - get current->active_mm
35 ldr \rd, [\rd, #TI_TASK]
36 ldr \rd, [\rd, #TSK_ACTIVE_MM]
40 * mmid - get context id from mm pointer (mm->context.id)
43 ldr \rd, [\rn, #MM_CONTEXT_ID]
47 * mask_asid - mask the ASID from the context ID
53 .macro crval, clear, mmuset, ucset
64 * cache_line_size - get the cache line size from the CSIDR register
65 * (available on ARMv7+). It assumes that the CSSR register was configured
66 * to access the L1 data cache CSIDR.
68 .macro dcache_line_size, reg, tmp
69 mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR
70 and \tmp, \tmp, #7 @ cache line size encoding
71 mov \reg, #16 @ size offset
72 mov \reg, \reg, lsl \tmp @ actual cache line size
77 * Sanity check the PTE configuration for the code below - which makes
78 * certain assumptions about how these bits are layed out.
80 #if L_PTE_SHARED != PTE_EXT_SHARED
81 #error PTE shared bit mismatch
83 #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
84 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
85 #error Invalid Linux PTE bit settings
89 * The ARMv6 and ARMv7 set_pte_ext translation function.
91 * Permission translation:
92 * YUWD APX AP1 AP0 SVC User
93 * 0xxx 0 0 0 no acc no acc
94 * 100x 1 0 1 r/o no acc
95 * 10x0 1 0 1 r/o no acc
96 * 1011 0 0 1 r/w no acc
101 .macro armv6_mt_table pfx
103 .long 0x00 @ L_PTE_MT_UNCACHED
104 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
105 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
106 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
107 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
109 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
110 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
112 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
114 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
115 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
121 .macro armv6_set_pte_ext pfx
122 str r1, [r0], #-2048 @ linux version
124 bic r3, r1, #0x000003fc
125 bic r3, r3, #PTE_TYPE_MASK
127 orr r3, r3, #PTE_EXT_AP0 | 2
129 adr ip, \pfx\()_mt_table
130 and r2, r1, #L_PTE_MT_MASK
134 tstne r1, #L_PTE_DIRTY
135 orreq r3, r3, #PTE_EXT_APX
138 orrne r3, r3, #PTE_EXT_AP1
139 tstne r3, #PTE_EXT_APX
140 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
143 orreq r3, r3, #PTE_EXT_XN
148 tstne r1, #L_PTE_PRESENT
152 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
157 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
158 * covering most CPUs except Xscale and Xscale 3.
160 * Permission translation:
162 * 0xxx 0x00 no acc no acc
163 * 100x 0x00 r/o no acc
164 * 10x0 0x00 r/o no acc
165 * 1011 0x55 r/w no acc
170 .macro armv3_set_pte_ext wc_disable=1
171 str r1, [r0], #-2048 @ linux version
173 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
175 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
176 bic r2, r2, #PTE_TYPE_MASK
177 orr r2, r2, #PTE_TYPE_SMALL
179 tst r3, #L_PTE_USER @ user?
180 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
182 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
183 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
185 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
189 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
190 tst r2, #PTE_CACHEABLE
191 bicne r2, r2, #PTE_BUFFERABLE
194 str r2, [r0] @ hardware version
199 * Xscale set_pte_ext translation, split into two halves to cope
200 * with work-arounds. r3 must be preserved by code between these
203 * Permission translation:
205 * 0xxx 00 no acc no acc
213 .macro xscale_set_pte_ext_prologue
214 str r1, [r0], #-2048 @ linux version
216 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
218 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
219 orr r2, r2, #PTE_TYPE_EXT @ extended page
221 tst r3, #L_PTE_USER @ user?
222 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
224 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
225 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
226 @ combined with user -> user r/w
229 .macro xscale_set_pte_ext_epilogue
230 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
231 movne r2, #0 @ no -> fault
233 str r2, [r0] @ hardware version
235 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
236 mcr p15, 0, ip, c7, c10, 4 @ data write barrier