arch/arm/mm/mm-armv.c

   1 /*
   2  *  linux/arch/arm/mm/mm-armv.c
   3  *
   4  *  Copyright (C) 1998-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  Page table sludge for ARM v3 and v4 processor architectures.
  11  */
  12 #include <linux/config.h>
  13 #include <linux/module.h>
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17 #include <linux/highmem.h>
  18 #include <linux/nodemask.h>
  19
  20 #include <asm/pgalloc.h>
  21 #include <asm/page.h>
  22 #include <asm/io.h>
  23 #include <asm/setup.h>
  24 #include <asm/tlbflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #define CPOLICY_UNCACHED        0
  29 #define CPOLICY_BUFFERED        1
  30 #define CPOLICY_WRITETHROUGH    2
  31 #define CPOLICY_WRITEBACK       3
  32 #define CPOLICY_WRITEALLOC      4
  33
  34 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  35 static unsigned int ecc_mask __initdata = 0;
  36 pgprot_t pgprot_kernel;
  37
  38 EXPORT_SYMBOL(pgprot_kernel);
  39
  40 pmd_t *top_pmd;
  41
  42 struct cachepolicy {
  43         const char      policy[16];
  44         unsigned int    cr_mask;
  45         unsigned int    pmd;
  46         unsigned int    pte;
  47 };
  48
  49 static struct cachepolicy cache_policies[] __initdata = {
  50         {
  51                 .policy         = "uncached",
  52                 .cr_mask        = CR_W|CR_C,
  53                 .pmd            = PMD_SECT_UNCACHED,
  54                 .pte            = 0,
  55         }, {
  56                 .policy         = "buffered",
  57                 .cr_mask        = CR_C,
  58                 .pmd            = PMD_SECT_BUFFERED,
  59                 .pte            = PTE_BUFFERABLE,
  60         }, {
  61                 .policy         = "writethrough",
  62                 .cr_mask        = 0,
  63                 .pmd            = PMD_SECT_WT,
  64                 .pte            = PTE_CACHEABLE,
  65         }, {
  66                 .policy         = "writeback",
  67                 .cr_mask        = 0,
  68                 .pmd            = PMD_SECT_WB,
  69                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  70         }, {
  71                 .policy         = "writealloc",
  72                 .cr_mask        = 0,
  73                 .pmd            = PMD_SECT_WBWA,
  74                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  75         }
  76 };
  77
  78 /*
  79  * These are useful for identifing cache coherency
  80  * problems by allowing the cache or the cache and
  81  * writebuffer to be turned off.  (Note: the write
  82  * buffer should not be on and the cache off).
  83  */
  84 static void __init early_cachepolicy(char **p)
  85 {
  86         int i;
  87
  88         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
  89                 int len = strlen(cache_policies[i].policy);
  90
  91                 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
  92                         cachepolicy = i;
  93                         cr_alignment &= ~cache_policies[i].cr_mask;
  94                         cr_no_alignment &= ~cache_policies[i].cr_mask;
  95                         *p += len;
  96                         break;
  97                 }
  98         }
  99         if (i == ARRAY_SIZE(cache_policies))
 100                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 101         flush_cache_all();
 102         set_cr(cr_alignment);
 103 }
 104
 105 static void __init early_nocache(char **__unused)
 106 {
 107         char *p = "buffered";
 108         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 109         early_cachepolicy(&p);
 110 }
 111
 112 static void __init early_nowrite(char **__unused)
 113 {
 114         char *p = "uncached";
 115         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 116         early_cachepolicy(&p);
 117 }
 118
 119 static void __init early_ecc(char **p)
 120 {
 121         if (memcmp(*p, "on", 2) == 0) {
 122                 ecc_mask = PMD_PROTECTION;
 123                 *p += 2;
 124         } else if (memcmp(*p, "off", 3) == 0) {
 125                 ecc_mask = 0;
 126                 *p += 3;
 127         }
 128 }
 129
 130 __early_param("nocache", early_nocache);
 131 __early_param("nowb", early_nowrite);
 132 __early_param("cachepolicy=", early_cachepolicy);
 133 __early_param("ecc=", early_ecc);
 134
 135 static int __init noalign_setup(char *__unused)
 136 {
 137         cr_alignment &= ~CR_A;
 138         cr_no_alignment &= ~CR_A;
 139         set_cr(cr_alignment);
 140         return 1;
 141 }
 142
 143 __setup("noalign", noalign_setup);
 144
 145 #define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
 146
 147 static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
 148 {
 149         return pmd_offset(pgd, virt);
 150 }
 151
 152 static inline pmd_t *pmd_off_k(unsigned long virt)
 153 {
 154         return pmd_off(pgd_offset_k(virt), virt);
 155 }
 156
 157 /*
 158  * need to get a 16k page for level 1
 159  */
 160 pgd_t *get_pgd_slow(struct mm_struct *mm)
 161 {
 162         pgd_t *new_pgd, *init_pgd;
 163         pmd_t *new_pmd, *init_pmd;
 164         pte_t *new_pte, *init_pte;
 165
 166         new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
 167         if (!new_pgd)
 168                 goto no_pgd;
 169
 170         memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
 171
 172         /*
 173          * Copy over the kernel and IO PGD entries
 174          */
 175         init_pgd = pgd_offset_k(0);
 176         memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
 177                        (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
 178
 179         clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
 180
 181         if (!vectors_high()) {
 182                 /*
 183                  * This lock is here just to satisfy pmd_alloc and pte_lock
 184                  */
 185                 spin_lock(&mm->page_table_lock);
 186
 187                 /*
 188                  * On ARM, first page must always be allocated since it
 189                  * contains the machine vectors.
 190                  */
 191                 new_pmd = pmd_alloc(mm, new_pgd, 0);
 192                 if (!new_pmd)
 193                         goto no_pmd;
 194
 195                 new_pte = pte_alloc_map(mm, new_pmd, 0);
 196                 if (!new_pte)
 197                         goto no_pte;
 198
 199                 init_pmd = pmd_offset(init_pgd, 0);
 200                 init_pte = pte_offset_map_nested(init_pmd, 0);
 201                 set_pte(new_pte, *init_pte);
 202                 pte_unmap_nested(init_pte);
 203                 pte_unmap(new_pte);
 204
 205                 spin_unlock(&mm->page_table_lock);
 206         }
 207
 208         return new_pgd;
 209
 210 no_pte:
 211         spin_unlock(&mm->page_table_lock);
 212         pmd_free(new_pmd);
 213         free_pages((unsigned long)new_pgd, 2);
 214         return NULL;
 215
 216 no_pmd:
 217         spin_unlock(&mm->page_table_lock);
 218         free_pages((unsigned long)new_pgd, 2);
 219         return NULL;
 220
 221 no_pgd:
 222         return NULL;
 223 }
 224
 225 void free_pgd_slow(pgd_t *pgd)
 226 {
 227         pmd_t *pmd;
 228         struct page *pte;
 229
 230         if (!pgd)
 231                 return;
 232
 233         /* pgd is always present and good */
 234         pmd = pmd_off(pgd, 0);
 235         if (pmd_none(*pmd))
 236                 goto free;
 237         if (pmd_bad(*pmd)) {
 238                 pmd_ERROR(*pmd);
 239                 pmd_clear(pmd);
 240                 goto free;
 241         }
 242
 243         pte = pmd_page(*pmd);
 244         pmd_clear(pmd);
 245         dec_page_state(nr_page_table_pages);
 246         pte_free(pte);
 247         pmd_free(pmd);
 248 free:
 249         free_pages((unsigned long) pgd, 2);
 250 }
 251
 252 /*
 253  * Create a SECTION PGD between VIRT and PHYS in domain
 254  * DOMAIN with protection PROT.  This operates on half-
 255  * pgdir entry increments.
 256  */
 257 static inline void
 258 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 259 {
 260         pmd_t *pmdp = pmd_off_k(virt);
 261
 262         if (virt & (1 << 20))
 263                 pmdp++;
 264
 265         *pmdp = __pmd(phys | prot);
 266         flush_pmd_entry(pmdp);
 267 }
 268
 269 /*
 270  * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
 271  */
 272 static inline void
 273 alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
 274 {
 275         int i;
 276
 277         for (i = 0; i < 16; i += 1) {
 278                 alloc_init_section(virt, phys & SUPERSECTION_MASK,
 279                                    prot | PMD_SECT_SUPER);
 280
 281                 virt += (PGDIR_SIZE / 2);
 282                 phys += (PGDIR_SIZE / 2);
 283         }
 284 }
 285
 286 /*
 287  * Add a PAGE mapping between VIRT and PHYS in domain
 288  * DOMAIN with protection PROT.  Note that due to the
 289  * way we map the PTEs, we must allocate two PTE_SIZE'd
 290  * blocks - one for the Linux pte table, and one for
 291  * the hardware pte table.
 292  */
 293 static inline void
 294 alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
 295 {
 296         pmd_t *pmdp = pmd_off_k(virt);
 297         pte_t *ptep;
 298
 299         if (pmd_none(*pmdp)) {
 300                 unsigned long pmdval;
 301                 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
 302                                                sizeof(pte_t));
 303
 304                 pmdval = __pa(ptep) | prot_l1;
 305                 pmdp[0] = __pmd(pmdval);
 306                 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
 307                 flush_pmd_entry(pmdp);
 308         }
 309         ptep = pte_offset_kernel(pmdp, virt);
 310
 311         set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 312 }
 313
 314 /*
 315  * Clear any PGD mapping.  On a two-level page table system,
 316  * the clearance is done by the middle-level functions (pmd)
 317  * rather than the top-level (pgd) functions.
 318  */
 319 static inline void clear_mapping(unsigned long virt)
 320 {
 321         pmd_clear(pmd_off_k(virt));
 322 }
 323
 324 struct mem_types {
 325         unsigned int    prot_pte;
 326         unsigned int    prot_l1;
 327         unsigned int    prot_sect;
 328         unsigned int    domain;
 329 };
 330
 331 static struct mem_types mem_types[] __initdata = {
 332         [MT_DEVICE] = {
 333                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 334                                 L_PTE_WRITE,
 335                 .prot_l1   = PMD_TYPE_TABLE,
 336                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 337                                 PMD_SECT_AP_WRITE,
 338                 .domain    = DOMAIN_IO,
 339         },
 340         [MT_CACHECLEAN] = {
 341                 .prot_sect = PMD_TYPE_SECT,
 342                 .domain    = DOMAIN_KERNEL,
 343         },
 344         [MT_MINICLEAN] = {
 345                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
 346                 .domain    = DOMAIN_KERNEL,
 347         },
 348         [MT_LOW_VECTORS] = {
 349                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 350                                 L_PTE_EXEC,
 351                 .prot_l1   = PMD_TYPE_TABLE,
 352                 .domain    = DOMAIN_USER,
 353         },
 354         [MT_HIGH_VECTORS] = {
 355                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 356                                 L_PTE_USER | L_PTE_EXEC,
 357                 .prot_l1   = PMD_TYPE_TABLE,
 358                 .domain    = DOMAIN_USER,
 359         },
 360         [MT_MEMORY] = {
 361                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 362                 .domain    = DOMAIN_KERNEL,
 363         },
 364         [MT_ROM] = {
 365                 .prot_sect = PMD_TYPE_SECT,
 366                 .domain    = DOMAIN_KERNEL,
 367         },
 368         [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
 369                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 370                                 L_PTE_WRITE,
 371                 .prot_l1   = PMD_TYPE_TABLE,
 372                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 373                                 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
 374                                 PMD_SECT_TEX(1),
 375                 .domain    = DOMAIN_IO,
 376         }
 377 };
 378
 379 /*
 380  * Adjust the PMD section entries according to the CPU in use.
 381  */
 382 static void __init build_mem_type_table(void)
 383 {
 384         struct cachepolicy *cp;
 385         unsigned int cr = get_cr();
 386         unsigned int user_pgprot;
 387         int cpu_arch = cpu_architecture();
 388         int i;
 389
 390 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 391         if (cachepolicy > CPOLICY_BUFFERED)
 392                 cachepolicy = CPOLICY_BUFFERED;
 393 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 394         if (cachepolicy > CPOLICY_WRITETHROUGH)
 395                 cachepolicy = CPOLICY_WRITETHROUGH;
 396 #endif
 397         if (cpu_arch < CPU_ARCH_ARMv5) {
 398                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 399                         cachepolicy = CPOLICY_WRITEBACK;
 400                 ecc_mask = 0;
 401         }
 402
 403         if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
 404                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 405                         if (mem_types[i].prot_l1)
 406                                 mem_types[i].prot_l1 |= PMD_BIT4;
 407                         if (mem_types[i].prot_sect)
 408                                 mem_types[i].prot_sect |= PMD_BIT4;
 409                 }
 410         }
 411
 412         cp = &cache_policies[cachepolicy];
 413         user_pgprot = cp->pte;
 414
 415         /*
 416          * ARMv6 and above have extended page tables.
 417          */
 418         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 419                 /*
 420                  * bit 4 becomes XN which we must clear for the
 421                  * kernel memory mapping.
 422                  */
 423                 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;
 424                 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;
 425                 /*
 426                  * Mark cache clean areas and XIP ROM read only
 427                  * from SVC mode and no access from userspace.
 428                  */
 429                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 430                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 431                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 432
 433                 /*
 434                  * Mark the device area as "shared device"
 435                  */
 436                 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
 437                 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 438
 439                 /*
 440                  * User pages need to be mapped with the ASID
 441                  * (iow, non-global)
 442                  */
 443                 user_pgprot |= L_PTE_ASID;
 444         }
 445
 446         if (cpu_arch >= CPU_ARCH_ARMv5) {
 447                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
 448                 mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
 449         } else {
 450                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte;
 451                 mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte;
 452                 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
 453         }
 454
 455         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 456         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 457         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 458         mem_types[MT_ROM].prot_sect |= cp->pmd;
 459
 460         for (i = 0; i < 16; i++) {
 461                 unsigned long v = pgprot_val(protection_map[i]);
 462                 v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot;
 463                 protection_map[i] = __pgprot(v);
 464         }
 465
 466         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 467                                  L_PTE_DIRTY | L_PTE_WRITE |
 468                                  L_PTE_EXEC | cp->pte);
 469
 470         switch (cp->pmd) {
 471         case PMD_SECT_WT:
 472                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 473                 break;
 474         case PMD_SECT_WB:
 475         case PMD_SECT_WBWA:
 476                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 477                 break;
 478         }
 479         printk("Memory policy: ECC %sabled, Data cache %s\n",
 480                 ecc_mask ? "en" : "dis", cp->policy);
 481 }
 482
 483 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 484
 485 /*
 486  * Create the page directory entries and any necessary
 487  * page tables for the mapping specified by `md'.  We
 488  * are able to cope here with varying sizes and address
 489  * offsets, and we take full advantage of sections and
 490  * supersections.
 491  */
 492 static void __init create_mapping(struct map_desc *md)
 493 {
 494         unsigned long virt, length;
 495         int prot_sect, prot_l1, domain;
 496         pgprot_t prot_pte;
 497         long off;
 498
 499         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 500                 printk(KERN_WARNING "BUG: not creating mapping for "
 501                        "0x%08lx at 0x%08lx in user region\n",
 502                        md->physical, md->virtual);
 503                 return;
 504         }
 505
 506         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 507             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 508                 printk(KERN_WARNING "BUG: mapping for 0x%08lx at 0x%08lx "
 509                        "overlaps vmalloc space\n",
 510                        md->physical, md->virtual);
 511         }
 512
 513         domain    = mem_types[md->type].domain;
 514         prot_pte  = __pgprot(mem_types[md->type].prot_pte);
 515         prot_l1   = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
 516         prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
 517
 518         virt   = md->virtual;
 519         off    = md->physical - virt;
 520         length = md->length;
 521
 522         if (mem_types[md->type].prot_l1 == 0 &&
 523             (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
 524                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 525                        "be mapped using pages, ignoring.\n",
 526                        md->physical, md->virtual);
 527                 return;
 528         }
 529
 530         while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
 531                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 532
 533                 virt   += PAGE_SIZE;
 534                 length -= PAGE_SIZE;
 535         }
 536
 537         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 538          *      Since domain assignments can in fact be arbitrary, the
 539          *      'domain == 0' check below is required to insure that ARMv6
 540          *      supersections are only allocated for domain 0 regardless
 541          *      of the actual domain assignments in use.
 542          */
 543         if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) {
 544                 /* Align to supersection boundary */
 545                 while ((virt & ~SUPERSECTION_MASK || (virt + off) &
 546                         ~SUPERSECTION_MASK) && length >= (PGDIR_SIZE / 2)) {
 547                         alloc_init_section(virt, virt + off, prot_sect);
 548
 549                         virt   += (PGDIR_SIZE / 2);
 550                         length -= (PGDIR_SIZE / 2);
 551                 }
 552
 553                 while (length >= SUPERSECTION_SIZE) {
 554                         alloc_init_supersection(virt, virt + off, prot_sect);
 555
 556                         virt   += SUPERSECTION_SIZE;
 557                         length -= SUPERSECTION_SIZE;
 558                 }
 559         }
 560
 561         /*
 562          * A section mapping covers half a "pgdir" entry.
 563          */
 564         while (length >= (PGDIR_SIZE / 2)) {
 565                 alloc_init_section(virt, virt + off, prot_sect);
 566
 567                 virt   += (PGDIR_SIZE / 2);
 568                 length -= (PGDIR_SIZE / 2);
 569         }
 570
 571         while (length >= PAGE_SIZE) {
 572                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 573
 574                 virt   += PAGE_SIZE;
 575                 length -= PAGE_SIZE;
 576         }
 577 }
 578
 579 /*
 580  * In order to soft-boot, we need to insert a 1:1 mapping in place of
 581  * the user-mode pages.  This will then ensure that we have predictable
 582  * results when turning the mmu off
 583  */
 584 void setup_mm_for_reboot(char mode)
 585 {
 586         unsigned long pmdval;
 587         pgd_t *pgd;
 588         pmd_t *pmd;
 589         int i;
 590         int cpu_arch = cpu_architecture();
 591
 592         if (current->mm && current->mm->pgd)
 593                 pgd = current->mm->pgd;
 594         else
 595                 pgd = init_mm.pgd;
 596
 597         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
 598                 pmdval = (i << PGDIR_SHIFT) |
 599                          PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
 600                          PMD_TYPE_SECT;
 601                 if (cpu_arch <= CPU_ARCH_ARMv5TEJ)
 602                         pmdval |= PMD_BIT4;
 603                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
 604                 pmd[0] = __pmd(pmdval);
 605                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
 606                 flush_pmd_entry(pmd);
 607         }
 608 }
 609
 610 extern void _stext, _etext;
 611
 612 /*
 613  * Setup initial mappings.  We use the page we allocated for zero page to hold
 614  * the mappings, which will get overwritten by the vectors in traps_init().
 615  * The mappings must be in virtual address order.
 616  */
 617 void __init memtable_init(struct meminfo *mi)
 618 {
 619         struct map_desc *init_maps, *p, *q;
 620         unsigned long address = 0;
 621         int i;
 622
 623         build_mem_type_table();
 624
 625         init_maps = p = alloc_bootmem_low_pages(PAGE_SIZE);
 626
 627 #ifdef CONFIG_XIP_KERNEL
 628         p->physical   = CONFIG_XIP_PHYS_ADDR & PMD_MASK;
 629         p->virtual    = (unsigned long)&_stext & PMD_MASK;
 630         p->length     = ((unsigned long)&_etext - p->virtual + ~PMD_MASK) & PMD_MASK;
 631         p->type       = MT_ROM;
 632         p ++;
 633 #endif
 634
 635         for (i = 0; i < mi->nr_banks; i++) {
 636                 if (mi->bank[i].size == 0)
 637                         continue;
 638
 639                 p->physical   = mi->bank[i].start;
 640                 p->virtual    = __phys_to_virt(p->physical);
 641                 p->length     = mi->bank[i].size;
 642                 p->type       = MT_MEMORY;
 643                 p ++;
 644         }
 645
 646 #ifdef FLUSH_BASE
 647         p->physical   = FLUSH_BASE_PHYS;
 648         p->virtual    = FLUSH_BASE;
 649         p->length     = PGDIR_SIZE;
 650         p->type       = MT_CACHECLEAN;
 651         p ++;
 652 #endif
 653
 654 #ifdef FLUSH_BASE_MINICACHE
 655         p->physical   = FLUSH_BASE_PHYS + PGDIR_SIZE;
 656         p->virtual    = FLUSH_BASE_MINICACHE;
 657         p->length     = PGDIR_SIZE;
 658         p->type       = MT_MINICLEAN;
 659         p ++;
 660 #endif
 661
 662         /*
 663          * Go through the initial mappings, but clear out any
 664          * pgdir entries that are not in the description.
 665          */
 666         q = init_maps;
 667         do {
 668                 if (address < q->virtual || q == p) {
 669                         clear_mapping(address);
 670                         address += PGDIR_SIZE;
 671                 } else {
 672                         create_mapping(q);
 673
 674                         address = q->virtual + q->length;
 675                         address = (address + PGDIR_SIZE - 1) & PGDIR_MASK;
 676
 677                         q ++;
 678                 }
 679         } while (address != 0);
 680
 681         /*
 682          * Create a mapping for the machine vectors at the high-vectors
 683          * location (0xffff0000).  If we aren't using high-vectors, also
 684          * create a mapping at the low-vectors virtual address.
 685          */
 686         init_maps->physical   = virt_to_phys(init_maps);
 687         init_maps->virtual    = 0xffff0000;
 688         init_maps->length     = PAGE_SIZE;
 689         init_maps->type       = MT_HIGH_VECTORS;
 690         create_mapping(init_maps);
 691
 692         if (!vectors_high()) {
 693                 init_maps->virtual = 0;
 694                 init_maps->type = MT_LOW_VECTORS;
 695                 create_mapping(init_maps);
 696         }
 697
 698         flush_cache_all();
 699         local_flush_tlb_all();
 700
 701         top_pmd = pmd_off_k(0xffff0000);
 702 }
 703
 704 /*
 705  * Create the architecture specific mappings
 706  */
 707 void __init iotable_init(struct map_desc *io_desc, int nr)
 708 {
 709         int i;
 710
 711         for (i = 0; i < nr; i++)
 712                 create_mapping(io_desc + i);
 713 }