2 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef __MACH_TEGRA_SLEEP_H
18 #define __MACH_TEGRA_SLEEP_H
22 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
24 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
26 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
28 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
30 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
32 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
33 #define PMC_SCRATCH37 0x130
34 #define PMC_SCRATCH38 0x134
35 #define PMC_SCRATCH39 0x138
36 #define PMC_SCRATCH41 0x140
38 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
39 #define CPU_RESETTABLE 2
40 #define CPU_RESETTABLE_SOON 1
41 #define CPU_NOT_RESETTABLE 0
44 /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
45 #define TEGRA_FLUSH_CACHE_LOUIS 0
46 #define TEGRA_FLUSH_CACHE_ALL 1
49 /* waits until the microsecond counter (base) is > rn */
50 .macro wait_until, rn, base, tmp
52 1001: ldr \tmp, [\base]
57 /* returns the offset of the flow controller halt register for a cpu */
58 .macro cpu_to_halt_reg rd, rcpu
61 movne \rd, \rd, lsl #3
66 /* returns the offset of the flow controller csr register for a cpu */
67 .macro cpu_to_csr_reg rd, rcpu
70 movne \rd, \rd, lsl #3
75 /* returns the ID of the current processor */
77 mrc p15, 0, \rd, c0, c0, 5
81 /* loads a 32-bit value into a register without a data access */
82 .macro mov32, reg, val
83 movw \reg, #:lower16:\val
84 movt \reg, #:upper16:\val
87 /* Marco to check CPU part num */
88 .macro check_cpu_part_num part_num, tmp1, tmp2
89 mrc p15, 0, \tmp1, c0, c0, 0
90 ubfx \tmp1, \tmp1, #4, #12
91 mov32 \tmp2, \part_num
95 /* Macro to exit SMP coherency. */
96 .macro exit_smp, tmp1, tmp2
97 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
98 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
99 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
101 #ifdef CONFIG_HAVE_ARM_SCU
102 check_cpu_part_num 0xc09, \tmp1, \tmp2
103 mrceq p15, 0, \tmp1, c0, c0, 5
104 andeq \tmp1, \tmp1, #0xF
105 moveq \tmp1, \tmp1, lsl #2
107 moveq \tmp2, \tmp2, lsl \tmp1
108 ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
109 streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
114 /* Macro to check Tegra revision */
115 #define APB_MISC_GP_HIDREV 0x804
116 .macro tegra_get_soc_id base, tmp1
118 ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
119 and \tmp1, \tmp1, #0xff00
120 mov \tmp1, \tmp1, lsr #8
124 void tegra_pen_lock(void);
125 void tegra_pen_unlock(void);
126 void tegra_resume(void);
127 int tegra_sleep_cpu_finish(unsigned long);
128 void tegra_disable_clean_inv_dcache(u32 flag);
130 #ifdef CONFIG_HOTPLUG_CPU
131 void tegra20_hotplug_shutdown(void);
132 void tegra30_hotplug_shutdown(void);
133 void tegra_hotplug_init(void);
135 static inline void tegra_hotplug_init(void) {}
138 void tegra20_cpu_shutdown(int cpu);
139 int tegra20_cpu_is_resettable_soon(void);
140 void tegra20_cpu_clear_resettable(void);
141 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
142 void tegra20_cpu_set_resettable_soon(void);
144 static inline void tegra20_cpu_set_resettable_soon(void) {}
147 int tegra20_sleep_cpu_secondary_finish(unsigned long);
148 void tegra20_tear_down_cpu(void);
149 int tegra30_sleep_cpu_secondary_finish(unsigned long);
150 void tegra30_tear_down_cpu(void);