2 * R-Car Generation 2 Power management support
4 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
5 * Copyright (C) 2011 Renesas Solutions Corp.
6 * Copyright (C) 2011 Magnus Damm
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/ioport.h>
16 #include <linux/of_address.h>
17 #include <linux/smp.h>
19 #include <asm/cputype.h>
21 #include "rcar-gen2.h"
24 #define RST 0xe6160000
26 #define CA15BAR 0x0020 /* CA15 Boot Address Register */
27 #define CA7BAR 0x0030 /* CA7 Boot Address Register */
28 #define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
29 #define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
31 /* SYS Boot Address Register */
32 #define SBAR_BAREN BIT(4) /* SBAR is valid */
34 /* Reset Control Registers */
35 #define CA15RESCNT_CODE 0xa5a50000
36 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
37 #define CA7RESCNT_CODE 0x5a5a0000
38 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
41 #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
43 static inline u32 phys_to_sbar(phys_addr_t addr)
45 return (addr >> 8) & 0xfffffc00;
48 void __init rcar_gen2_pm_init(void)
53 struct device_node *np;
62 for_each_of_cpu_node(np) {
63 if (of_device_is_compatible(np, "arm,cortex-a15"))
65 else if (of_device_is_compatible(np, "arm,cortex-a7"))
69 np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
71 /* No smp-sram in DT, fall back to hardcoded address */
72 res = (struct resource)DEFINE_RES_MEM(ICRAM1,
77 error = of_address_to_resource(np, 0, &res);
79 pr_err("Failed to get smp-sram address: %d\n", error);
84 /* RAM for jump stub, because BAR requires 256KB aligned address */
85 if (res.start & (256 * 1024 - 1) ||
86 resource_size(&res) < shmobile_boot_size) {
87 pr_err("Invalid smp-sram region\n");
91 p = ioremap(res.start, resource_size(&res));
95 * install the reset vector, use the largest version if we have enough
98 if (resource_size(&res) >= shmobile_boot_size_gen2) {
99 shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
100 memcpy_toio(p, shmobile_boot_vector_gen2,
101 shmobile_boot_size_gen2);
103 memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
107 /* setup reset vectors */
108 p = ioremap_nocache(RST, 0x63);
109 bar = phys_to_sbar(res.start);
111 writel_relaxed(bar, p + CA15BAR);
112 writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
114 /* de-assert reset for CA15 CPUs */
115 writel_relaxed((readl_relaxed(p + CA15RESCNT) &
116 ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
120 writel_relaxed(bar, p + CA7BAR);
121 writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
123 /* de-assert reset for CA7 CPUs */
124 writel_relaxed((readl_relaxed(p + CA7RESCNT) &
125 ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
130 shmobile_smp_apmu_suspend_init();