arch/arm/mach-omap2/sram.c

   1 /*
   2  *
   3  * OMAP SRAM detection and management
   4  *
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Written by Tony Lindgren <tony@atomide.com>
   7  *
   8  * Copyright (C) 2009-2012 Texas Instruments
   9  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/fncpy.h>
  22 #include <asm/tlb.h>
  23 #include <asm/cacheflush.h>
  24
  25 #include <asm/mach/map.h>
  26
  27 #include "soc.h"
  28 #include "iomap.h"
  29 #include "prm2xxx_3xxx.h"
  30 #include "sdrc.h"
  31 #include "sram.h"
  32
  33 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  34 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  35 #ifdef CONFIG_OMAP4_ERRATA_I688
  36 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  37 #else
  38 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  39 #endif
  40 #define OMAP5_SRAM_PA           0x40300000
  41
  42 #define SRAM_BOOTLOADER_SZ      0x00
  43
  44 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  45 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  46 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  47
  48 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  49 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  50 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  51 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  52 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  53
  54 #define GP_DEVICE               0x300
  55
  56 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  57
  58 static unsigned long omap_sram_start;
  59 static unsigned long omap_sram_skip;
  60 static unsigned long omap_sram_size;
  61
  62 /*
  63  * Depending on the target RAMFS firewall setup, the public usable amount of
  64  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  65  * device allows ARM11 but not other initiators for full size. This
  66  * functionality seems ok until some nice security API happens.
  67  */
  68 static int is_sram_locked(void)
  69 {
  70         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  71                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  72                 if (cpu_is_omap242x()) {
  73                         writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  74                         writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  75                         writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  76                 }
  77                 if (cpu_is_omap34xx()) {
  78                         writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  79                         writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  80                         writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  81                         writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
  82                         writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  83                 }
  84                 return 0;
  85         } else
  86                 return 1; /* assume locked with no PPA or security driver */
  87 }
  88
  89 /*
  90  * The amount of SRAM depends on the core type.
  91  * Note that we cannot try to test for SRAM here because writes
  92  * to secure SRAM will hang the system. Also the SRAM is not
  93  * yet mapped at this point.
  94  */
  95 static void __init omap_detect_sram(void)
  96 {
  97         omap_sram_skip = SRAM_BOOTLOADER_SZ;
  98         if (is_sram_locked()) {
  99                 if (cpu_is_omap34xx()) {
 100                         omap_sram_start = OMAP3_SRAM_PUB_PA;
 101                         if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 102                             (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 103                                 omap_sram_size = 0x7000; /* 28K */
 104                                 omap_sram_skip += SZ_16K;
 105                         } else {
 106                                 omap_sram_size = 0x8000; /* 32K */
 107                         }
 108                 } else if (cpu_is_omap44xx()) {
 109                         omap_sram_start = OMAP4_SRAM_PUB_PA;
 110                         omap_sram_size = 0xa000; /* 40K */
 111                 } else if (soc_is_omap54xx()) {
 112                         omap_sram_start = OMAP5_SRAM_PA;
 113                         omap_sram_size = SZ_128K; /* 128KB */
 114                 } else {
 115                         omap_sram_start = OMAP2_SRAM_PUB_PA;
 116                         omap_sram_size = 0x800; /* 2K */
 117                 }
 118         } else {
 119                 if (soc_is_am33xx()) {
 120                         omap_sram_start = AM33XX_SRAM_PA;
 121                         omap_sram_size = 0x10000; /* 64K */
 122                 } else if (soc_is_am43xx()) {
 123                         omap_sram_start = AM33XX_SRAM_PA;
 124                         omap_sram_size = SZ_256K;
 125                 } else if (cpu_is_omap34xx()) {
 126                         omap_sram_start = OMAP3_SRAM_PA;
 127                         omap_sram_size = 0x10000; /* 64K */
 128                 } else if (cpu_is_omap44xx()) {
 129                         omap_sram_start = OMAP4_SRAM_PA;
 130                         omap_sram_size = 0xe000; /* 56K */
 131                 } else if (soc_is_omap54xx()) {
 132                         omap_sram_start = OMAP5_SRAM_PA;
 133                         omap_sram_size = SZ_128K; /* 128KB */
 134                 } else {
 135                         omap_sram_start = OMAP2_SRAM_PA;
 136                         if (cpu_is_omap242x())
 137                                 omap_sram_size = 0xa0000; /* 640K */
 138                         else if (cpu_is_omap243x())
 139                                 omap_sram_size = 0x10000; /* 64K */
 140                 }
 141         }
 142 }
 143
 144 /*
 145  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 146  */
 147 static void __init omap2_map_sram(void)
 148 {
 149         int cached = 1;
 150
 151 #ifdef CONFIG_OMAP4_ERRATA_I688
 152         if (cpu_is_omap44xx()) {
 153                 omap_sram_start += PAGE_SIZE;
 154                 omap_sram_size -= SZ_16K;
 155         }
 156 #endif
 157         if (cpu_is_omap34xx()) {
 158                 /*
 159                  * SRAM must be marked as non-cached on OMAP3 since the
 160                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 161                  * SDRAM controller disabled, and if it is marked cached,
 162                  * the ARM may attempt to write cache lines back to SDRAM
 163                  * which will cause the system to hang.
 164                  */
 165                 cached = 0;
 166         }
 167
 168         omap_map_sram(omap_sram_start, omap_sram_size,
 169                         omap_sram_skip, cached);
 170 }
 171
 172 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 173                               u32 base_cs, u32 force_unlock);
 174
 175 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 176                    u32 base_cs, u32 force_unlock)
 177 {
 178         BUG_ON(!_omap2_sram_ddr_init);
 179         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 180                              base_cs, force_unlock);
 181 }
 182
 183 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 184                                           u32 mem_type);
 185
 186 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 187 {
 188         BUG_ON(!_omap2_sram_reprogram_sdrc);
 189         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 190 }
 191
 192 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 193
 194 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 195 {
 196         BUG_ON(!_omap2_set_prcm);
 197         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 198 }
 199
 200 #ifdef CONFIG_SOC_OMAP2420
 201 static int __init omap242x_sram_init(void)
 202 {
 203         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 204                                         omap242x_sram_ddr_init_sz);
 205
 206         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 207                                             omap242x_sram_reprogram_sdrc_sz);
 208
 209         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 210                                          omap242x_sram_set_prcm_sz);
 211
 212         return 0;
 213 }
 214 #else
 215 static inline int omap242x_sram_init(void)
 216 {
 217         return 0;
 218 }
 219 #endif
 220
 221 #ifdef CONFIG_SOC_OMAP2430
 222 static int __init omap243x_sram_init(void)
 223 {
 224         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 225                                         omap243x_sram_ddr_init_sz);
 226
 227         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 228                                             omap243x_sram_reprogram_sdrc_sz);
 229
 230         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 231                                          omap243x_sram_set_prcm_sz);
 232
 233         return 0;
 234 }
 235 #else
 236 static inline int omap243x_sram_init(void)
 237 {
 238         return 0;
 239 }
 240 #endif
 241
 242 #ifdef CONFIG_ARCH_OMAP3
 243
 244 static u32 (*_omap3_sram_configure_core_dpll)(
 245                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 246                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 247                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 248                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 249                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 250
 251 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 252                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 253                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 254                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 255                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 256 {
 257         BUG_ON(!_omap3_sram_configure_core_dpll);
 258         return _omap3_sram_configure_core_dpll(
 259                         m2, unlock_dll, f, inc,
 260                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 261                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 262                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 263                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 264 }
 265
 266 void omap3_sram_restore_context(void)
 267 {
 268         omap_sram_reset();
 269
 270         _omap3_sram_configure_core_dpll =
 271                 omap_sram_push(omap3_sram_configure_core_dpll,
 272                                omap3_sram_configure_core_dpll_sz);
 273         omap_push_sram_idle();
 274 }
 275
 276 static inline int omap34xx_sram_init(void)
 277 {
 278         omap3_sram_restore_context();
 279         return 0;
 280 }
 281 #else
 282 static inline int omap34xx_sram_init(void)
 283 {
 284         return 0;
 285 }
 286 #endif /* CONFIG_ARCH_OMAP3 */
 287
 288 static inline int am33xx_sram_init(void)
 289 {
 290         return 0;
 291 }
 292
 293 int __init omap_sram_init(void)
 294 {
 295         omap_detect_sram();
 296         omap2_map_sram();
 297
 298         if (cpu_is_omap242x())
 299                 omap242x_sram_init();
 300         else if (cpu_is_omap2430())
 301                 omap243x_sram_init();
 302         else if (soc_is_am33xx())
 303                 am33xx_sram_init();
 304         else if (cpu_is_omap34xx())
 305                 omap34xx_sram_init();
 306
 307         return 0;
 308 }