arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .flags          = HWMOD_CLKDM_NOAUTO,
 363         .prcm = {
 364                 .omap4 = {
 365                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 366                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 367                         .modulemode   = MODULEMODE_SWCTRL,
 368                 },
 369         },
 370 };
 371
 372 /* dcan2 */
 373 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 374         .name           = "dcan2",
 375         .class          = &dra7xx_dcan_hwmod_class,
 376         .clkdm_name     = "l4per2_clkdm",
 377         .main_clk       = "sys_clkin1",
 378         .flags          = HWMOD_CLKDM_NOAUTO,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 382                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 383                         .modulemode   = MODULEMODE_SWCTRL,
 384                 },
 385         },
 386 };
 387
 388 /* pwmss  */
 389 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 390         .rev_offs       = 0x0,
 391         .sysc_offs      = 0x4,
 392         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 393         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 394         .sysc_fields    = &omap_hwmod_sysc_type2,
 395 };
 396
 397 /*
 398  * epwmss class
 399  */
 400 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 401         .name           = "epwmss",
 402         .sysc           = &dra7xx_epwmss_sysc,
 403 };
 404
 405 /* epwmss0 */
 406 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 407         .name           = "epwmss0",
 408         .class          = &dra7xx_epwmss_hwmod_class,
 409         .clkdm_name     = "l4per2_clkdm",
 410         .main_clk       = "l4_root_clk_div",
 411         .prcm           = {
 412                 .omap4  = {
 413                         .modulemode     = MODULEMODE_SWCTRL,
 414                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 415                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 416                 },
 417         },
 418 };
 419
 420 /* epwmss1 */
 421 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 422         .name           = "epwmss1",
 423         .class          = &dra7xx_epwmss_hwmod_class,
 424         .clkdm_name     = "l4per2_clkdm",
 425         .main_clk       = "l4_root_clk_div",
 426         .prcm           = {
 427                 .omap4  = {
 428                         .modulemode     = MODULEMODE_SWCTRL,
 429                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 430                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 431                 },
 432         },
 433 };
 434
 435 /* epwmss2 */
 436 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 437         .name           = "epwmss2",
 438         .class          = &dra7xx_epwmss_hwmod_class,
 439         .clkdm_name     = "l4per2_clkdm",
 440         .main_clk       = "l4_root_clk_div",
 441         .prcm           = {
 442                 .omap4  = {
 443                         .modulemode     = MODULEMODE_SWCTRL,
 444                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 445                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 446                 },
 447         },
 448 };
 449
 450 /*
 451  * 'dma' class
 452  *
 453  */
 454
 455 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 456         .rev_offs       = 0x0000,
 457         .sysc_offs      = 0x002c,
 458         .syss_offs      = 0x0028,
 459         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 460                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 461                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 462                            SYSS_HAS_RESET_STATUS),
 463         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 464                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 465                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 466         .sysc_fields    = &omap_hwmod_sysc_type1,
 467 };
 468
 469 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 470         .name   = "dma",
 471         .sysc   = &dra7xx_dma_sysc,
 472 };
 473
 474 /* dma dev_attr */
 475 static struct omap_dma_dev_attr dma_dev_attr = {
 476         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 477                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 478         .lch_count      = 32,
 479 };
 480
 481 /* dma_system */
 482 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 483         .name           = "dma_system",
 484         .class          = &dra7xx_dma_hwmod_class,
 485         .clkdm_name     = "dma_clkdm",
 486         .main_clk       = "l3_iclk_div",
 487         .prcm = {
 488                 .omap4 = {
 489                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 490                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 491                 },
 492         },
 493         .dev_attr       = &dma_dev_attr,
 494 };
 495
 496 /*
 497  * 'tpcc' class
 498  *
 499  */
 500 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 501         .name           = "tpcc",
 502 };
 503
 504 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 505         .name           = "tpcc",
 506         .class          = &dra7xx_tpcc_hwmod_class,
 507         .clkdm_name     = "l3main1_clkdm",
 508         .main_clk       = "l3_iclk_div",
 509         .prcm           = {
 510                 .omap4  = {
 511                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 512                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 513                 },
 514         },
 515 };
 516
 517 /*
 518  * 'tptc' class
 519  *
 520  */
 521 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 522         .name           = "tptc",
 523 };
 524
 525 /* tptc0 */
 526 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 527         .name           = "tptc0",
 528         .class          = &dra7xx_tptc_hwmod_class,
 529         .clkdm_name     = "l3main1_clkdm",
 530         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 531         .main_clk       = "l3_iclk_div",
 532         .prcm           = {
 533                 .omap4  = {
 534                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 535                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 536                         .modulemode   = MODULEMODE_HWCTRL,
 537                 },
 538         },
 539 };
 540
 541 /* tptc1 */
 542 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 543         .name           = "tptc1",
 544         .class          = &dra7xx_tptc_hwmod_class,
 545         .clkdm_name     = "l3main1_clkdm",
 546         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 547         .main_clk       = "l3_iclk_div",
 548         .prcm           = {
 549                 .omap4  = {
 550                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 551                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 552                         .modulemode   = MODULEMODE_HWCTRL,
 553                 },
 554         },
 555 };
 556
 557 /*
 558  * 'dss' class
 559  *
 560  */
 561
 562 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 563         .rev_offs       = 0x0000,
 564         .syss_offs      = 0x0014,
 565         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 566 };
 567
 568 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 569         .name   = "dss",
 570         .sysc   = &dra7xx_dss_sysc,
 571         .reset  = omap_dss_reset,
 572 };
 573
 574 /* dss */
 575 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 576         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 577         { .dma_req = -1 }
 578 };
 579
 580 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 581         { .role = "dss_clk", .clk = "dss_dss_clk" },
 582         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 583         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 584         { .role = "video2_clk", .clk = "dss_video2_clk" },
 585         { .role = "video1_clk", .clk = "dss_video1_clk" },
 586         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 587         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 588 };
 589
 590 static struct omap_hwmod dra7xx_dss_hwmod = {
 591         .name           = "dss_core",
 592         .class          = &dra7xx_dss_hwmod_class,
 593         .clkdm_name     = "dss_clkdm",
 594         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 595         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 596         .main_clk       = "dss_dss_clk",
 597         .prcm = {
 598                 .omap4 = {
 599                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 600                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 601                         .modulemode   = MODULEMODE_SWCTRL,
 602                 },
 603         },
 604         .opt_clks       = dss_opt_clks,
 605         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 606 };
 607
 608 /*
 609  * 'dispc' class
 610  * display controller
 611  */
 612
 613 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 614         .rev_offs       = 0x0000,
 615         .sysc_offs      = 0x0010,
 616         .syss_offs      = 0x0014,
 617         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 618                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 619                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 620                            SYSS_HAS_RESET_STATUS),
 621         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 622                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 623         .sysc_fields    = &omap_hwmod_sysc_type1,
 624 };
 625
 626 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 627         .name   = "dispc",
 628         .sysc   = &dra7xx_dispc_sysc,
 629 };
 630
 631 /* dss_dispc */
 632 /* dss_dispc dev_attr */
 633 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 634         .has_framedonetv_irq    = 1,
 635         .manager_count          = 4,
 636 };
 637
 638 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 639         .name           = "dss_dispc",
 640         .class          = &dra7xx_dispc_hwmod_class,
 641         .clkdm_name     = "dss_clkdm",
 642         .main_clk       = "dss_dss_clk",
 643         .prcm = {
 644                 .omap4 = {
 645                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 646                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 647                 },
 648         },
 649         .dev_attr       = &dss_dispc_dev_attr,
 650         .parent_hwmod   = &dra7xx_dss_hwmod,
 651 };
 652
 653 /*
 654  * 'hdmi' class
 655  * hdmi controller
 656  */
 657
 658 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 659         .rev_offs       = 0x0000,
 660         .sysc_offs      = 0x0010,
 661         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 662                            SYSC_HAS_SOFTRESET),
 663         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 664                            SIDLE_SMART_WKUP),
 665         .sysc_fields    = &omap_hwmod_sysc_type2,
 666 };
 667
 668 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 669         .name   = "hdmi",
 670         .sysc   = &dra7xx_hdmi_sysc,
 671 };
 672
 673 /* dss_hdmi */
 674
 675 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 676         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 677 };
 678
 679 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 680         .name           = "dss_hdmi",
 681         .class          = &dra7xx_hdmi_hwmod_class,
 682         .clkdm_name     = "dss_clkdm",
 683         .main_clk       = "dss_48mhz_clk",
 684         .prcm = {
 685                 .omap4 = {
 686                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 687                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 688                 },
 689         },
 690         .opt_clks       = dss_hdmi_opt_clks,
 691         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 692         .parent_hwmod   = &dra7xx_dss_hwmod,
 693 };
 694
 695 /* AES (the 'P' (public) device) */
 696 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 697         .rev_offs       = 0x0080,
 698         .sysc_offs      = 0x0084,
 699         .syss_offs      = 0x0088,
 700         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 701 };
 702
 703 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 704         .name   = "aes",
 705         .sysc   = &dra7xx_aes_sysc,
 706         .rev    = 2,
 707 };
 708
 709 /* AES1 */
 710 static struct omap_hwmod dra7xx_aes1_hwmod = {
 711         .name           = "aes1",
 712         .class          = &dra7xx_aes_hwmod_class,
 713         .clkdm_name     = "l4sec_clkdm",
 714         .main_clk       = "l3_iclk_div",
 715         .prcm = {
 716                 .omap4 = {
 717                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 718                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 719                         .modulemode   = MODULEMODE_HWCTRL,
 720                 },
 721         },
 722 };
 723
 724 /* AES2 */
 725 static struct omap_hwmod dra7xx_aes2_hwmod = {
 726         .name           = "aes2",
 727         .class          = &dra7xx_aes_hwmod_class,
 728         .clkdm_name     = "l4sec_clkdm",
 729         .main_clk       = "l3_iclk_div",
 730         .prcm = {
 731                 .omap4 = {
 732                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 733                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 734                         .modulemode   = MODULEMODE_HWCTRL,
 735                 },
 736         },
 737 };
 738
 739 /* sha0 HIB2 (the 'P' (public) device) */
 740 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 741         .rev_offs       = 0x100,
 742         .sysc_offs      = 0x110,
 743         .syss_offs      = 0x114,
 744         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 745 };
 746
 747 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 748         .name           = "sham",
 749         .sysc           = &dra7xx_sha0_sysc,
 750         .rev            = 2,
 751 };
 752
 753 struct omap_hwmod dra7xx_sha0_hwmod = {
 754         .name           = "sham",
 755         .class          = &dra7xx_sha0_hwmod_class,
 756         .clkdm_name     = "l4sec_clkdm",
 757         .main_clk       = "l3_iclk_div",
 758         .prcm           = {
 759                 .omap4 = {
 760                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 761                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 762                         .modulemode   = MODULEMODE_HWCTRL,
 763                 },
 764         },
 765 };
 766
 767 /*
 768  * 'elm' class
 769  *
 770  */
 771
 772 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 773         .rev_offs       = 0x0000,
 774         .sysc_offs      = 0x0010,
 775         .syss_offs      = 0x0014,
 776         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 777                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 778                            SYSS_HAS_RESET_STATUS),
 779         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 780                            SIDLE_SMART_WKUP),
 781         .sysc_fields    = &omap_hwmod_sysc_type1,
 782 };
 783
 784 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 785         .name   = "elm",
 786         .sysc   = &dra7xx_elm_sysc,
 787 };
 788
 789 /* elm */
 790
 791 static struct omap_hwmod dra7xx_elm_hwmod = {
 792         .name           = "elm",
 793         .class          = &dra7xx_elm_hwmod_class,
 794         .clkdm_name     = "l4per_clkdm",
 795         .main_clk       = "l3_iclk_div",
 796         .prcm = {
 797                 .omap4 = {
 798                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 799                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 800                 },
 801         },
 802 };
 803
 804 /*
 805  * 'gpio' class
 806  *
 807  */
 808
 809 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 810         .rev_offs       = 0x0000,
 811         .sysc_offs      = 0x0010,
 812         .syss_offs      = 0x0114,
 813         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 814                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 815                            SYSS_HAS_RESET_STATUS),
 816         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 817                            SIDLE_SMART_WKUP),
 818         .sysc_fields    = &omap_hwmod_sysc_type1,
 819 };
 820
 821 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 822         .name   = "gpio",
 823         .sysc   = &dra7xx_gpio_sysc,
 824         .rev    = 2,
 825 };
 826
 827 /* gpio dev_attr */
 828 static struct omap_gpio_dev_attr gpio_dev_attr = {
 829         .bank_width     = 32,
 830         .dbck_flag      = true,
 831 };
 832
 833 /* gpio1 */
 834 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 835         { .role = "dbclk", .clk = "gpio1_dbclk" },
 836 };
 837
 838 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 839         .name           = "gpio1",
 840         .class          = &dra7xx_gpio_hwmod_class,
 841         .clkdm_name     = "wkupaon_clkdm",
 842         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 843         .main_clk       = "wkupaon_iclk_mux",
 844         .prcm = {
 845                 .omap4 = {
 846                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 847                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 848                         .modulemode   = MODULEMODE_HWCTRL,
 849                 },
 850         },
 851         .opt_clks       = gpio1_opt_clks,
 852         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 853         .dev_attr       = &gpio_dev_attr,
 854 };
 855
 856 /* gpio2 */
 857 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 858         { .role = "dbclk", .clk = "gpio2_dbclk" },
 859 };
 860
 861 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 862         .name           = "gpio2",
 863         .class          = &dra7xx_gpio_hwmod_class,
 864         .clkdm_name     = "l4per_clkdm",
 865         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 866         .main_clk       = "l3_iclk_div",
 867         .prcm = {
 868                 .omap4 = {
 869                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 870                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 871                         .modulemode   = MODULEMODE_HWCTRL,
 872                 },
 873         },
 874         .opt_clks       = gpio2_opt_clks,
 875         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 876         .dev_attr       = &gpio_dev_attr,
 877 };
 878
 879 /* gpio3 */
 880 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 881         { .role = "dbclk", .clk = "gpio3_dbclk" },
 882 };
 883
 884 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 885         .name           = "gpio3",
 886         .class          = &dra7xx_gpio_hwmod_class,
 887         .clkdm_name     = "l4per_clkdm",
 888         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 889         .main_clk       = "l3_iclk_div",
 890         .prcm = {
 891                 .omap4 = {
 892                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 893                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 894                         .modulemode   = MODULEMODE_HWCTRL,
 895                 },
 896         },
 897         .opt_clks       = gpio3_opt_clks,
 898         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 899         .dev_attr       = &gpio_dev_attr,
 900 };
 901
 902 /* gpio4 */
 903 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 904         { .role = "dbclk", .clk = "gpio4_dbclk" },
 905 };
 906
 907 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 908         .name           = "gpio4",
 909         .class          = &dra7xx_gpio_hwmod_class,
 910         .clkdm_name     = "l4per_clkdm",
 911         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 912         .main_clk       = "l3_iclk_div",
 913         .prcm = {
 914                 .omap4 = {
 915                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 916                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 917                         .modulemode   = MODULEMODE_HWCTRL,
 918                 },
 919         },
 920         .opt_clks       = gpio4_opt_clks,
 921         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 922         .dev_attr       = &gpio_dev_attr,
 923 };
 924
 925 /* gpio5 */
 926 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 927         { .role = "dbclk", .clk = "gpio5_dbclk" },
 928 };
 929
 930 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 931         .name           = "gpio5",
 932         .class          = &dra7xx_gpio_hwmod_class,
 933         .clkdm_name     = "l4per_clkdm",
 934         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 935         .main_clk       = "l3_iclk_div",
 936         .prcm = {
 937                 .omap4 = {
 938                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 939                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 940                         .modulemode   = MODULEMODE_HWCTRL,
 941                 },
 942         },
 943         .opt_clks       = gpio5_opt_clks,
 944         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 945         .dev_attr       = &gpio_dev_attr,
 946 };
 947
 948 /* gpio6 */
 949 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 950         { .role = "dbclk", .clk = "gpio6_dbclk" },
 951 };
 952
 953 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 954         .name           = "gpio6",
 955         .class          = &dra7xx_gpio_hwmod_class,
 956         .clkdm_name     = "l4per_clkdm",
 957         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 958         .main_clk       = "l3_iclk_div",
 959         .prcm = {
 960                 .omap4 = {
 961                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 962                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 963                         .modulemode   = MODULEMODE_HWCTRL,
 964                 },
 965         },
 966         .opt_clks       = gpio6_opt_clks,
 967         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 968         .dev_attr       = &gpio_dev_attr,
 969 };
 970
 971 /* gpio7 */
 972 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 973         { .role = "dbclk", .clk = "gpio7_dbclk" },
 974 };
 975
 976 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 977         .name           = "gpio7",
 978         .class          = &dra7xx_gpio_hwmod_class,
 979         .clkdm_name     = "l4per_clkdm",
 980         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 981         .main_clk       = "l3_iclk_div",
 982         .prcm = {
 983                 .omap4 = {
 984                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 985                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 986                         .modulemode   = MODULEMODE_HWCTRL,
 987                 },
 988         },
 989         .opt_clks       = gpio7_opt_clks,
 990         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 991         .dev_attr       = &gpio_dev_attr,
 992 };
 993
 994 /* gpio8 */
 995 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 996         { .role = "dbclk", .clk = "gpio8_dbclk" },
 997 };
 998
 999 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1000         .name           = "gpio8",
1001         .class          = &dra7xx_gpio_hwmod_class,
1002         .clkdm_name     = "l4per_clkdm",
1003         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1004         .main_clk       = "l3_iclk_div",
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1008                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1009                         .modulemode   = MODULEMODE_HWCTRL,
1010                 },
1011         },
1012         .opt_clks       = gpio8_opt_clks,
1013         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1014         .dev_attr       = &gpio_dev_attr,
1015 };
1016
1017 /*
1018  * 'gpmc' class
1019  *
1020  */
1021
1022 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1023         .rev_offs       = 0x0000,
1024         .sysc_offs      = 0x0010,
1025         .syss_offs      = 0x0014,
1026         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1027                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1028         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1029         .sysc_fields    = &omap_hwmod_sysc_type1,
1030 };
1031
1032 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1033         .name   = "gpmc",
1034         .sysc   = &dra7xx_gpmc_sysc,
1035 };
1036
1037 /* gpmc */
1038
1039 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1040         .name           = "gpmc",
1041         .class          = &dra7xx_gpmc_hwmod_class,
1042         .clkdm_name     = "l3main1_clkdm",
1043         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1044         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1045         .main_clk       = "l3_iclk_div",
1046         .prcm = {
1047                 .omap4 = {
1048                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1049                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1050                         .modulemode   = MODULEMODE_HWCTRL,
1051                 },
1052         },
1053 };
1054
1055 /*
1056  * 'hdq1w' class
1057  *
1058  */
1059
1060 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1061         .rev_offs       = 0x0000,
1062         .sysc_offs      = 0x0014,
1063         .syss_offs      = 0x0018,
1064         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1065                            SYSS_HAS_RESET_STATUS),
1066         .sysc_fields    = &omap_hwmod_sysc_type1,
1067 };
1068
1069 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1070         .name   = "hdq1w",
1071         .sysc   = &dra7xx_hdq1w_sysc,
1072 };
1073
1074 /* hdq1w */
1075
1076 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1077         .name           = "hdq1w",
1078         .class          = &dra7xx_hdq1w_hwmod_class,
1079         .clkdm_name     = "l4per_clkdm",
1080         .flags          = HWMOD_INIT_NO_RESET,
1081         .main_clk       = "func_12m_fclk",
1082         .prcm = {
1083                 .omap4 = {
1084                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1085                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1086                         .modulemode   = MODULEMODE_SWCTRL,
1087                 },
1088         },
1089 };
1090
1091 /*
1092  * 'i2c' class
1093  *
1094  */
1095
1096 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1097         .sysc_offs      = 0x0010,
1098         .syss_offs      = 0x0090,
1099         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1100                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1101                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1102         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1103                            SIDLE_SMART_WKUP),
1104         .sysc_fields    = &omap_hwmod_sysc_type1,
1105 };
1106
1107 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1108         .name   = "i2c",
1109         .sysc   = &dra7xx_i2c_sysc,
1110         .reset  = &omap_i2c_reset,
1111         .rev    = OMAP_I2C_IP_VERSION_2,
1112 };
1113
1114 /* i2c dev_attr */
1115 static struct omap_i2c_dev_attr i2c_dev_attr = {
1116         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1117 };
1118
1119 /* i2c1 */
1120 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1121         .name           = "i2c1",
1122         .class          = &dra7xx_i2c_hwmod_class,
1123         .clkdm_name     = "l4per_clkdm",
1124         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1125         .main_clk       = "func_96m_fclk",
1126         .prcm = {
1127                 .omap4 = {
1128                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1129                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1130                         .modulemode   = MODULEMODE_SWCTRL,
1131                 },
1132         },
1133         .dev_attr       = &i2c_dev_attr,
1134 };
1135
1136 /* i2c2 */
1137 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1138         .name           = "i2c2",
1139         .class          = &dra7xx_i2c_hwmod_class,
1140         .clkdm_name     = "l4per_clkdm",
1141         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1142         .main_clk       = "func_96m_fclk",
1143         .prcm = {
1144                 .omap4 = {
1145                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1146                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1147                         .modulemode   = MODULEMODE_SWCTRL,
1148                 },
1149         },
1150         .dev_attr       = &i2c_dev_attr,
1151 };
1152
1153 /* i2c3 */
1154 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1155         .name           = "i2c3",
1156         .class          = &dra7xx_i2c_hwmod_class,
1157         .clkdm_name     = "l4per_clkdm",
1158         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1159         .main_clk       = "func_96m_fclk",
1160         .prcm = {
1161                 .omap4 = {
1162                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1163                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1164                         .modulemode   = MODULEMODE_SWCTRL,
1165                 },
1166         },
1167         .dev_attr       = &i2c_dev_attr,
1168 };
1169
1170 /* i2c4 */
1171 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1172         .name           = "i2c4",
1173         .class          = &dra7xx_i2c_hwmod_class,
1174         .clkdm_name     = "l4per_clkdm",
1175         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1176         .main_clk       = "func_96m_fclk",
1177         .prcm = {
1178                 .omap4 = {
1179                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1180                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1181                         .modulemode   = MODULEMODE_SWCTRL,
1182                 },
1183         },
1184         .dev_attr       = &i2c_dev_attr,
1185 };
1186
1187 /* i2c5 */
1188 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1189         .name           = "i2c5",
1190         .class          = &dra7xx_i2c_hwmod_class,
1191         .clkdm_name     = "ipu_clkdm",
1192         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1193         .main_clk       = "func_96m_fclk",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1197                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_SWCTRL,
1199                 },
1200         },
1201         .dev_attr       = &i2c_dev_attr,
1202 };
1203
1204 /*
1205  * 'mailbox' class
1206  *
1207  */
1208
1209 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1210         .rev_offs       = 0x0000,
1211         .sysc_offs      = 0x0010,
1212         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1213                            SYSC_HAS_SOFTRESET),
1214         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1215         .sysc_fields    = &omap_hwmod_sysc_type2,
1216 };
1217
1218 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1219         .name   = "mailbox",
1220         .sysc   = &dra7xx_mailbox_sysc,
1221 };
1222
1223 /* mailbox1 */
1224 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1225         .name           = "mailbox1",
1226         .class          = &dra7xx_mailbox_hwmod_class,
1227         .clkdm_name     = "l4cfg_clkdm",
1228         .prcm = {
1229                 .omap4 = {
1230                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1231                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1232                 },
1233         },
1234 };
1235
1236 /* mailbox2 */
1237 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1238         .name           = "mailbox2",
1239         .class          = &dra7xx_mailbox_hwmod_class,
1240         .clkdm_name     = "l4cfg_clkdm",
1241         .prcm = {
1242                 .omap4 = {
1243                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1244                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1245                 },
1246         },
1247 };
1248
1249 /* mailbox3 */
1250 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1251         .name           = "mailbox3",
1252         .class          = &dra7xx_mailbox_hwmod_class,
1253         .clkdm_name     = "l4cfg_clkdm",
1254         .prcm = {
1255                 .omap4 = {
1256                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1257                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1258                 },
1259         },
1260 };
1261
1262 /* mailbox4 */
1263 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1264         .name           = "mailbox4",
1265         .class          = &dra7xx_mailbox_hwmod_class,
1266         .clkdm_name     = "l4cfg_clkdm",
1267         .prcm = {
1268                 .omap4 = {
1269                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1270                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1271                 },
1272         },
1273 };
1274
1275 /* mailbox5 */
1276 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1277         .name           = "mailbox5",
1278         .class          = &dra7xx_mailbox_hwmod_class,
1279         .clkdm_name     = "l4cfg_clkdm",
1280         .prcm = {
1281                 .omap4 = {
1282                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1283                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1284                 },
1285         },
1286 };
1287
1288 /* mailbox6 */
1289 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1290         .name           = "mailbox6",
1291         .class          = &dra7xx_mailbox_hwmod_class,
1292         .clkdm_name     = "l4cfg_clkdm",
1293         .prcm = {
1294                 .omap4 = {
1295                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1296                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1297                 },
1298         },
1299 };
1300
1301 /* mailbox7 */
1302 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1303         .name           = "mailbox7",
1304         .class          = &dra7xx_mailbox_hwmod_class,
1305         .clkdm_name     = "l4cfg_clkdm",
1306         .prcm = {
1307                 .omap4 = {
1308                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1309                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1310                 },
1311         },
1312 };
1313
1314 /* mailbox8 */
1315 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1316         .name           = "mailbox8",
1317         .class          = &dra7xx_mailbox_hwmod_class,
1318         .clkdm_name     = "l4cfg_clkdm",
1319         .prcm = {
1320                 .omap4 = {
1321                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1322                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1323                 },
1324         },
1325 };
1326
1327 /* mailbox9 */
1328 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1329         .name           = "mailbox9",
1330         .class          = &dra7xx_mailbox_hwmod_class,
1331         .clkdm_name     = "l4cfg_clkdm",
1332         .prcm = {
1333                 .omap4 = {
1334                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1335                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1336                 },
1337         },
1338 };
1339
1340 /* mailbox10 */
1341 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1342         .name           = "mailbox10",
1343         .class          = &dra7xx_mailbox_hwmod_class,
1344         .clkdm_name     = "l4cfg_clkdm",
1345         .prcm = {
1346                 .omap4 = {
1347                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1348                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1349                 },
1350         },
1351 };
1352
1353 /* mailbox11 */
1354 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1355         .name           = "mailbox11",
1356         .class          = &dra7xx_mailbox_hwmod_class,
1357         .clkdm_name     = "l4cfg_clkdm",
1358         .prcm = {
1359                 .omap4 = {
1360                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1361                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1362                 },
1363         },
1364 };
1365
1366 /* mailbox12 */
1367 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1368         .name           = "mailbox12",
1369         .class          = &dra7xx_mailbox_hwmod_class,
1370         .clkdm_name     = "l4cfg_clkdm",
1371         .prcm = {
1372                 .omap4 = {
1373                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1374                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1375                 },
1376         },
1377 };
1378
1379 /* mailbox13 */
1380 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1381         .name           = "mailbox13",
1382         .class          = &dra7xx_mailbox_hwmod_class,
1383         .clkdm_name     = "l4cfg_clkdm",
1384         .prcm = {
1385                 .omap4 = {
1386                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1387                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1388                 },
1389         },
1390 };
1391
1392 /*
1393  * 'mcspi' class
1394  *
1395  */
1396
1397 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1398         .rev_offs       = 0x0000,
1399         .sysc_offs      = 0x0010,
1400         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1401                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1402         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1403                            SIDLE_SMART_WKUP),
1404         .sysc_fields    = &omap_hwmod_sysc_type2,
1405 };
1406
1407 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1408         .name   = "mcspi",
1409         .sysc   = &dra7xx_mcspi_sysc,
1410         .rev    = OMAP4_MCSPI_REV,
1411 };
1412
1413 /* mcspi1 */
1414 /* mcspi1 dev_attr */
1415 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1416         .num_chipselect = 4,
1417 };
1418
1419 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1420         .name           = "mcspi1",
1421         .class          = &dra7xx_mcspi_hwmod_class,
1422         .clkdm_name     = "l4per_clkdm",
1423         .main_clk       = "func_48m_fclk",
1424         .prcm = {
1425                 .omap4 = {
1426                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1427                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1428                         .modulemode   = MODULEMODE_SWCTRL,
1429                 },
1430         },
1431         .dev_attr       = &mcspi1_dev_attr,
1432 };
1433
1434 /* mcspi2 */
1435 /* mcspi2 dev_attr */
1436 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1437         .num_chipselect = 2,
1438 };
1439
1440 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1441         .name           = "mcspi2",
1442         .class          = &dra7xx_mcspi_hwmod_class,
1443         .clkdm_name     = "l4per_clkdm",
1444         .main_clk       = "func_48m_fclk",
1445         .prcm = {
1446                 .omap4 = {
1447                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1448                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1449                         .modulemode   = MODULEMODE_SWCTRL,
1450                 },
1451         },
1452         .dev_attr       = &mcspi2_dev_attr,
1453 };
1454
1455 /* mcspi3 */
1456 /* mcspi3 dev_attr */
1457 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1458         .num_chipselect = 2,
1459 };
1460
1461 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1462         .name           = "mcspi3",
1463         .class          = &dra7xx_mcspi_hwmod_class,
1464         .clkdm_name     = "l4per_clkdm",
1465         .main_clk       = "func_48m_fclk",
1466         .prcm = {
1467                 .omap4 = {
1468                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1469                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1470                         .modulemode   = MODULEMODE_SWCTRL,
1471                 },
1472         },
1473         .dev_attr       = &mcspi3_dev_attr,
1474 };
1475
1476 /* mcspi4 */
1477 /* mcspi4 dev_attr */
1478 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1479         .num_chipselect = 1,
1480 };
1481
1482 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1483         .name           = "mcspi4",
1484         .class          = &dra7xx_mcspi_hwmod_class,
1485         .clkdm_name     = "l4per_clkdm",
1486         .main_clk       = "func_48m_fclk",
1487         .prcm = {
1488                 .omap4 = {
1489                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1490                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1491                         .modulemode   = MODULEMODE_SWCTRL,
1492                 },
1493         },
1494         .dev_attr       = &mcspi4_dev_attr,
1495 };
1496
1497 /*
1498  * 'mcasp' class
1499  *
1500  */
1501 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1502         .sysc_offs      = 0x0004,
1503         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1504         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1505         .sysc_fields    = &omap_hwmod_sysc_type3,
1506 };
1507
1508 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1509         .name   = "mcasp",
1510         .sysc   = &dra7xx_mcasp_sysc,
1511 };
1512
1513 /* mcasp1 */
1514 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1515         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1516         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1517 };
1518
1519 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1520         .name           = "mcasp1",
1521         .class          = &dra7xx_mcasp_hwmod_class,
1522         .clkdm_name     = "ipu_clkdm",
1523         .main_clk       = "mcasp1_aux_gfclk_mux",
1524         .flags          = HWMOD_OPT_CLKS_NEEDED,
1525         .prcm = {
1526                 .omap4 = {
1527                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1528                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1529                         .modulemode   = MODULEMODE_SWCTRL,
1530                 },
1531         },
1532         .opt_clks       = mcasp1_opt_clks,
1533         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1534 };
1535
1536 /* mcasp2 */
1537 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1538         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1539         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1540 };
1541
1542 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1543         .name           = "mcasp2",
1544         .class          = &dra7xx_mcasp_hwmod_class,
1545         .clkdm_name     = "l4per2_clkdm",
1546         .main_clk       = "mcasp2_aux_gfclk_mux",
1547         .flags          = HWMOD_OPT_CLKS_NEEDED,
1548         .prcm = {
1549                 .omap4 = {
1550                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1551                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1552                         .modulemode   = MODULEMODE_SWCTRL,
1553                 },
1554         },
1555         .opt_clks       = mcasp2_opt_clks,
1556         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1557 };
1558
1559 /* mcasp3 */
1560 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1561         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1562 };
1563
1564 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1565         .name           = "mcasp3",
1566         .class          = &dra7xx_mcasp_hwmod_class,
1567         .clkdm_name     = "l4per2_clkdm",
1568         .main_clk       = "mcasp3_aux_gfclk_mux",
1569         .flags          = HWMOD_OPT_CLKS_NEEDED,
1570         .prcm = {
1571                 .omap4 = {
1572                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1573                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1574                         .modulemode   = MODULEMODE_SWCTRL,
1575                 },
1576         },
1577         .opt_clks       = mcasp3_opt_clks,
1578         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1579 };
1580
1581 /* mcasp4 */
1582 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1583         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1584 };
1585
1586 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1587         .name           = "mcasp4",
1588         .class          = &dra7xx_mcasp_hwmod_class,
1589         .clkdm_name     = "l4per2_clkdm",
1590         .main_clk       = "mcasp4_aux_gfclk_mux",
1591         .flags          = HWMOD_OPT_CLKS_NEEDED,
1592         .prcm = {
1593                 .omap4 = {
1594                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1595                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1596                         .modulemode   = MODULEMODE_SWCTRL,
1597                 },
1598         },
1599         .opt_clks       = mcasp4_opt_clks,
1600         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1601 };
1602
1603 /* mcasp5 */
1604 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1605         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1606 };
1607
1608 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1609         .name           = "mcasp5",
1610         .class          = &dra7xx_mcasp_hwmod_class,
1611         .clkdm_name     = "l4per2_clkdm",
1612         .main_clk       = "mcasp5_aux_gfclk_mux",
1613         .flags          = HWMOD_OPT_CLKS_NEEDED,
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1617                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .opt_clks       = mcasp5_opt_clks,
1622         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1623 };
1624
1625 /* mcasp6 */
1626 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1627         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1628 };
1629
1630 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1631         .name           = "mcasp6",
1632         .class          = &dra7xx_mcasp_hwmod_class,
1633         .clkdm_name     = "l4per2_clkdm",
1634         .main_clk       = "mcasp6_aux_gfclk_mux",
1635         .flags          = HWMOD_OPT_CLKS_NEEDED,
1636         .prcm = {
1637                 .omap4 = {
1638                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1639                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1640                         .modulemode   = MODULEMODE_SWCTRL,
1641                 },
1642         },
1643         .opt_clks       = mcasp6_opt_clks,
1644         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1645 };
1646
1647 /* mcasp7 */
1648 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1649         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1650 };
1651
1652 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1653         .name           = "mcasp7",
1654         .class          = &dra7xx_mcasp_hwmod_class,
1655         .clkdm_name     = "l4per2_clkdm",
1656         .main_clk       = "mcasp7_aux_gfclk_mux",
1657         .flags          = HWMOD_OPT_CLKS_NEEDED,
1658         .prcm = {
1659                 .omap4 = {
1660                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1661                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1662                         .modulemode   = MODULEMODE_SWCTRL,
1663                 },
1664         },
1665         .opt_clks       = mcasp7_opt_clks,
1666         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1667 };
1668
1669 /* mcasp8 */
1670 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1671         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1672 };
1673
1674 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1675         .name           = "mcasp8",
1676         .class          = &dra7xx_mcasp_hwmod_class,
1677         .clkdm_name     = "l4per2_clkdm",
1678         .main_clk       = "mcasp8_aux_gfclk_mux",
1679         .flags          = HWMOD_OPT_CLKS_NEEDED,
1680         .prcm = {
1681                 .omap4 = {
1682                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1683                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1684                         .modulemode   = MODULEMODE_SWCTRL,
1685                 },
1686         },
1687         .opt_clks       = mcasp8_opt_clks,
1688         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1689 };
1690
1691 /*
1692  * 'mmc' class
1693  *
1694  */
1695
1696 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1697         .rev_offs       = 0x0000,
1698         .sysc_offs      = 0x0010,
1699         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1700                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1701                            SYSC_HAS_SOFTRESET),
1702         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1703                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1704                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1705         .sysc_fields    = &omap_hwmod_sysc_type2,
1706 };
1707
1708 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1709         .name   = "mmc",
1710         .sysc   = &dra7xx_mmc_sysc,
1711 };
1712
1713 /* mmc1 */
1714 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1715         { .role = "clk32k", .clk = "mmc1_clk32k" },
1716 };
1717
1718 /* mmc1 dev_attr */
1719 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1720         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1721 };
1722
1723 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1724         .name           = "mmc1",
1725         .class          = &dra7xx_mmc_hwmod_class,
1726         .clkdm_name     = "l3init_clkdm",
1727         .main_clk       = "mmc1_fclk_div",
1728         .prcm = {
1729                 .omap4 = {
1730                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1731                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1732                         .modulemode   = MODULEMODE_SWCTRL,
1733                 },
1734         },
1735         .opt_clks       = mmc1_opt_clks,
1736         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1737         .dev_attr       = &mmc1_dev_attr,
1738 };
1739
1740 /* mmc2 */
1741 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1742         { .role = "clk32k", .clk = "mmc2_clk32k" },
1743 };
1744
1745 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1746         .name           = "mmc2",
1747         .class          = &dra7xx_mmc_hwmod_class,
1748         .clkdm_name     = "l3init_clkdm",
1749         .main_clk       = "mmc2_fclk_div",
1750         .prcm = {
1751                 .omap4 = {
1752                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1753                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1754                         .modulemode   = MODULEMODE_SWCTRL,
1755                 },
1756         },
1757         .opt_clks       = mmc2_opt_clks,
1758         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1759 };
1760
1761 /* mmc3 */
1762 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1763         { .role = "clk32k", .clk = "mmc3_clk32k" },
1764 };
1765
1766 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1767         .name           = "mmc3",
1768         .class          = &dra7xx_mmc_hwmod_class,
1769         .clkdm_name     = "l4per_clkdm",
1770         .main_clk       = "mmc3_gfclk_div",
1771         .prcm = {
1772                 .omap4 = {
1773                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1774                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1775                         .modulemode   = MODULEMODE_SWCTRL,
1776                 },
1777         },
1778         .opt_clks       = mmc3_opt_clks,
1779         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1780 };
1781
1782 /* mmc4 */
1783 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1784         { .role = "clk32k", .clk = "mmc4_clk32k" },
1785 };
1786
1787 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1788         .name           = "mmc4",
1789         .class          = &dra7xx_mmc_hwmod_class,
1790         .clkdm_name     = "l4per_clkdm",
1791         .main_clk       = "mmc4_gfclk_div",
1792         .prcm = {
1793                 .omap4 = {
1794                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1795                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1796                         .modulemode   = MODULEMODE_SWCTRL,
1797                 },
1798         },
1799         .opt_clks       = mmc4_opt_clks,
1800         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1801 };
1802
1803 /*
1804  * 'mpu' class
1805  *
1806  */
1807
1808 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1809         .name   = "mpu",
1810 };
1811
1812 /* mpu */
1813 static struct omap_hwmod dra7xx_mpu_hwmod = {
1814         .name           = "mpu",
1815         .class          = &dra7xx_mpu_hwmod_class,
1816         .clkdm_name     = "mpu_clkdm",
1817         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1818         .main_clk       = "dpll_mpu_m2_ck",
1819         .prcm = {
1820                 .omap4 = {
1821                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1822                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1823                 },
1824         },
1825 };
1826
1827 /*
1828  * 'ocp2scp' class
1829  *
1830  */
1831
1832 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1833         .rev_offs       = 0x0000,
1834         .sysc_offs      = 0x0010,
1835         .syss_offs      = 0x0014,
1836         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1837                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1838         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1839         .sysc_fields    = &omap_hwmod_sysc_type1,
1840 };
1841
1842 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1843         .name   = "ocp2scp",
1844         .sysc   = &dra7xx_ocp2scp_sysc,
1845 };
1846
1847 /* ocp2scp1 */
1848 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1849         .name           = "ocp2scp1",
1850         .class          = &dra7xx_ocp2scp_hwmod_class,
1851         .clkdm_name     = "l3init_clkdm",
1852         .main_clk       = "l4_root_clk_div",
1853         .prcm = {
1854                 .omap4 = {
1855                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1856                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1857                         .modulemode   = MODULEMODE_HWCTRL,
1858                 },
1859         },
1860 };
1861
1862 /* ocp2scp3 */
1863 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1864         .name           = "ocp2scp3",
1865         .class          = &dra7xx_ocp2scp_hwmod_class,
1866         .clkdm_name     = "l3init_clkdm",
1867         .main_clk       = "l4_root_clk_div",
1868         .prcm = {
1869                 .omap4 = {
1870                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1871                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1872                         .modulemode   = MODULEMODE_HWCTRL,
1873                 },
1874         },
1875 };
1876
1877 /*
1878  * 'PCIE' class
1879  *
1880  */
1881
1882 /*
1883  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1884  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1885  * associated with an IP automatically leaving the driver to handle that
1886  * by itself. This does not work for PCIeSS which needs the reset lines
1887  * deasserted for the driver to start accessing registers.
1888  *
1889  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1890  * lines after asserting them.
1891  */
1892 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1893 {
1894         int i;
1895
1896         for (i = 0; i < oh->rst_lines_cnt; i++) {
1897                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1898                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1899         }
1900
1901         return 0;
1902 }
1903
1904 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1905         .name   = "pcie",
1906         .reset  = dra7xx_pciess_reset,
1907 };
1908
1909 /* pcie1 */
1910 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1911         { .name = "pcie", .rst_shift = 0 },
1912 };
1913
1914 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1915         .name           = "pcie1",
1916         .class          = &dra7xx_pciess_hwmod_class,
1917         .clkdm_name     = "pcie_clkdm",
1918         .rst_lines      = dra7xx_pciess1_resets,
1919         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1920         .main_clk       = "l4_root_clk_div",
1921         .prcm = {
1922                 .omap4 = {
1923                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1924                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1925                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1926                         .modulemode   = MODULEMODE_SWCTRL,
1927                 },
1928         },
1929 };
1930
1931 /* pcie2 */
1932 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1933         { .name = "pcie", .rst_shift = 1 },
1934 };
1935
1936 /* pcie2 */
1937 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1938         .name           = "pcie2",
1939         .class          = &dra7xx_pciess_hwmod_class,
1940         .clkdm_name     = "pcie_clkdm",
1941         .rst_lines      = dra7xx_pciess2_resets,
1942         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1943         .main_clk       = "l4_root_clk_div",
1944         .prcm = {
1945                 .omap4 = {
1946                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1947                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1948                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1949                         .modulemode   = MODULEMODE_SWCTRL,
1950                 },
1951         },
1952 };
1953
1954 /*
1955  * 'qspi' class
1956  *
1957  */
1958
1959 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1960         .sysc_offs      = 0x0010,
1961         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1962         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1963                            SIDLE_SMART_WKUP),
1964         .sysc_fields    = &omap_hwmod_sysc_type2,
1965 };
1966
1967 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1968         .name   = "qspi",
1969         .sysc   = &dra7xx_qspi_sysc,
1970 };
1971
1972 /* qspi */
1973 static struct omap_hwmod dra7xx_qspi_hwmod = {
1974         .name           = "qspi",
1975         .class          = &dra7xx_qspi_hwmod_class,
1976         .clkdm_name     = "l4per2_clkdm",
1977         .main_clk       = "qspi_gfclk_div",
1978         .prcm = {
1979                 .omap4 = {
1980                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1981                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1982                         .modulemode   = MODULEMODE_SWCTRL,
1983                 },
1984         },
1985 };
1986
1987 /*
1988  * 'rtcss' class
1989  *
1990  */
1991 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1992         .sysc_offs      = 0x0078,
1993         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1994         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1995                            SIDLE_SMART_WKUP),
1996         .sysc_fields    = &omap_hwmod_sysc_type3,
1997 };
1998
1999 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2000         .name   = "rtcss",
2001         .sysc   = &dra7xx_rtcss_sysc,
2002         .unlock = &omap_hwmod_rtc_unlock,
2003         .lock   = &omap_hwmod_rtc_lock,
2004 };
2005
2006 /* rtcss */
2007 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2008         .name           = "rtcss",
2009         .class          = &dra7xx_rtcss_hwmod_class,
2010         .clkdm_name     = "rtc_clkdm",
2011         .main_clk       = "sys_32k_ck",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2015                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019 };
2020
2021 /*
2022  * 'sata' class
2023  *
2024  */
2025
2026 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2027         .sysc_offs      = 0x0000,
2028         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2029         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2030                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2031                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2032         .sysc_fields    = &omap_hwmod_sysc_type2,
2033 };
2034
2035 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2036         .name   = "sata",
2037         .sysc   = &dra7xx_sata_sysc,
2038 };
2039
2040 /* sata */
2041
2042 static struct omap_hwmod dra7xx_sata_hwmod = {
2043         .name           = "sata",
2044         .class          = &dra7xx_sata_hwmod_class,
2045         .clkdm_name     = "l3init_clkdm",
2046         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2047         .main_clk       = "func_48m_fclk",
2048         .mpu_rt_idx     = 1,
2049         .prcm = {
2050                 .omap4 = {
2051                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2052                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2053                         .modulemode   = MODULEMODE_SWCTRL,
2054                 },
2055         },
2056 };
2057
2058 /*
2059  * 'smartreflex' class
2060  *
2061  */
2062
2063 /* The IP is not compliant to type1 / type2 scheme */
2064 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2065         .sidle_shift    = 24,
2066         .enwkup_shift   = 26,
2067 };
2068
2069 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2070         .sysc_offs      = 0x0038,
2071         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2072         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2073                            SIDLE_SMART_WKUP),
2074         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2075 };
2076
2077 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2078         .name   = "smartreflex",
2079         .sysc   = &dra7xx_smartreflex_sysc,
2080         .rev    = 2,
2081 };
2082
2083 /* smartreflex_core */
2084 /* smartreflex_core dev_attr */
2085 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2086         .sensor_voltdm_name     = "core",
2087 };
2088
2089 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2090         .name           = "smartreflex_core",
2091         .class          = &dra7xx_smartreflex_hwmod_class,
2092         .clkdm_name     = "coreaon_clkdm",
2093         .main_clk       = "wkupaon_iclk_mux",
2094         .prcm = {
2095                 .omap4 = {
2096                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2097                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2098                         .modulemode   = MODULEMODE_SWCTRL,
2099                 },
2100         },
2101         .dev_attr       = &smartreflex_core_dev_attr,
2102 };
2103
2104 /* smartreflex_mpu */
2105 /* smartreflex_mpu dev_attr */
2106 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2107         .sensor_voltdm_name     = "mpu",
2108 };
2109
2110 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2111         .name           = "smartreflex_mpu",
2112         .class          = &dra7xx_smartreflex_hwmod_class,
2113         .clkdm_name     = "coreaon_clkdm",
2114         .main_clk       = "wkupaon_iclk_mux",
2115         .prcm = {
2116                 .omap4 = {
2117                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2118                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2119                         .modulemode   = MODULEMODE_SWCTRL,
2120                 },
2121         },
2122         .dev_attr       = &smartreflex_mpu_dev_attr,
2123 };
2124
2125 /*
2126  * 'spinlock' class
2127  *
2128  */
2129
2130 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2131         .rev_offs       = 0x0000,
2132         .sysc_offs      = 0x0010,
2133         .syss_offs      = 0x0014,
2134         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2135                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2136                            SYSS_HAS_RESET_STATUS),
2137         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2138         .sysc_fields    = &omap_hwmod_sysc_type1,
2139 };
2140
2141 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2142         .name   = "spinlock",
2143         .sysc   = &dra7xx_spinlock_sysc,
2144 };
2145
2146 /* spinlock */
2147 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2148         .name           = "spinlock",
2149         .class          = &dra7xx_spinlock_hwmod_class,
2150         .clkdm_name     = "l4cfg_clkdm",
2151         .main_clk       = "l3_iclk_div",
2152         .prcm = {
2153                 .omap4 = {
2154                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2155                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2156                 },
2157         },
2158 };
2159
2160 /*
2161  * 'timer' class
2162  *
2163  * This class contains several variants: ['timer_1ms', 'timer_secure',
2164  * 'timer']
2165  */
2166
2167 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2168         .rev_offs       = 0x0000,
2169         .sysc_offs      = 0x0010,
2170         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2171                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2172         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2173                            SIDLE_SMART_WKUP),
2174         .sysc_fields    = &omap_hwmod_sysc_type2,
2175 };
2176
2177 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2178         .name   = "timer",
2179         .sysc   = &dra7xx_timer_1ms_sysc,
2180 };
2181
2182 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2183         .rev_offs       = 0x0000,
2184         .sysc_offs      = 0x0010,
2185         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2186                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2187         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2188                            SIDLE_SMART_WKUP),
2189         .sysc_fields    = &omap_hwmod_sysc_type2,
2190 };
2191
2192 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2193         .name   = "timer",
2194         .sysc   = &dra7xx_timer_sysc,
2195 };
2196
2197 /* timer1 */
2198 static struct omap_hwmod dra7xx_timer1_hwmod = {
2199         .name           = "timer1",
2200         .class          = &dra7xx_timer_1ms_hwmod_class,
2201         .clkdm_name     = "wkupaon_clkdm",
2202         .main_clk       = "timer1_gfclk_mux",
2203         .prcm = {
2204                 .omap4 = {
2205                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2206                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2207                         .modulemode   = MODULEMODE_SWCTRL,
2208                 },
2209         },
2210 };
2211
2212 /* timer2 */
2213 static struct omap_hwmod dra7xx_timer2_hwmod = {
2214         .name           = "timer2",
2215         .class          = &dra7xx_timer_1ms_hwmod_class,
2216         .clkdm_name     = "l4per_clkdm",
2217         .main_clk       = "timer2_gfclk_mux",
2218         .prcm = {
2219                 .omap4 = {
2220                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2221                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2222                         .modulemode   = MODULEMODE_SWCTRL,
2223                 },
2224         },
2225 };
2226
2227 /* timer3 */
2228 static struct omap_hwmod dra7xx_timer3_hwmod = {
2229         .name           = "timer3",
2230         .class          = &dra7xx_timer_hwmod_class,
2231         .clkdm_name     = "l4per_clkdm",
2232         .main_clk       = "timer3_gfclk_mux",
2233         .prcm = {
2234                 .omap4 = {
2235                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2236                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2237                         .modulemode   = MODULEMODE_SWCTRL,
2238                 },
2239         },
2240 };
2241
2242 /* timer4 */
2243 static struct omap_hwmod dra7xx_timer4_hwmod = {
2244         .name           = "timer4",
2245         .class          = &dra7xx_timer_hwmod_class,
2246         .clkdm_name     = "l4per_clkdm",
2247         .main_clk       = "timer4_gfclk_mux",
2248         .prcm = {
2249                 .omap4 = {
2250                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2251                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2252                         .modulemode   = MODULEMODE_SWCTRL,
2253                 },
2254         },
2255 };
2256
2257 /* timer5 */
2258 static struct omap_hwmod dra7xx_timer5_hwmod = {
2259         .name           = "timer5",
2260         .class          = &dra7xx_timer_hwmod_class,
2261         .clkdm_name     = "ipu_clkdm",
2262         .main_clk       = "timer5_gfclk_mux",
2263         .prcm = {
2264                 .omap4 = {
2265                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2266                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2267                         .modulemode   = MODULEMODE_SWCTRL,
2268                 },
2269         },
2270 };
2271
2272 /* timer6 */
2273 static struct omap_hwmod dra7xx_timer6_hwmod = {
2274         .name           = "timer6",
2275         .class          = &dra7xx_timer_hwmod_class,
2276         .clkdm_name     = "ipu_clkdm",
2277         .main_clk       = "timer6_gfclk_mux",
2278         .prcm = {
2279                 .omap4 = {
2280                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2281                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2282                         .modulemode   = MODULEMODE_SWCTRL,
2283                 },
2284         },
2285 };
2286
2287 /* timer7 */
2288 static struct omap_hwmod dra7xx_timer7_hwmod = {
2289         .name           = "timer7",
2290         .class          = &dra7xx_timer_hwmod_class,
2291         .clkdm_name     = "ipu_clkdm",
2292         .main_clk       = "timer7_gfclk_mux",
2293         .prcm = {
2294                 .omap4 = {
2295                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2296                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2297                         .modulemode   = MODULEMODE_SWCTRL,
2298                 },
2299         },
2300 };
2301
2302 /* timer8 */
2303 static struct omap_hwmod dra7xx_timer8_hwmod = {
2304         .name           = "timer8",
2305         .class          = &dra7xx_timer_hwmod_class,
2306         .clkdm_name     = "ipu_clkdm",
2307         .main_clk       = "timer8_gfclk_mux",
2308         .prcm = {
2309                 .omap4 = {
2310                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2311                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2312                         .modulemode   = MODULEMODE_SWCTRL,
2313                 },
2314         },
2315 };
2316
2317 /* timer9 */
2318 static struct omap_hwmod dra7xx_timer9_hwmod = {
2319         .name           = "timer9",
2320         .class          = &dra7xx_timer_hwmod_class,
2321         .clkdm_name     = "l4per_clkdm",
2322         .main_clk       = "timer9_gfclk_mux",
2323         .prcm = {
2324                 .omap4 = {
2325                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2326                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2327                         .modulemode   = MODULEMODE_SWCTRL,
2328                 },
2329         },
2330 };
2331
2332 /* timer10 */
2333 static struct omap_hwmod dra7xx_timer10_hwmod = {
2334         .name           = "timer10",
2335         .class          = &dra7xx_timer_1ms_hwmod_class,
2336         .clkdm_name     = "l4per_clkdm",
2337         .main_clk       = "timer10_gfclk_mux",
2338         .prcm = {
2339                 .omap4 = {
2340                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2341                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2342                         .modulemode   = MODULEMODE_SWCTRL,
2343                 },
2344         },
2345 };
2346
2347 /* timer11 */
2348 static struct omap_hwmod dra7xx_timer11_hwmod = {
2349         .name           = "timer11",
2350         .class          = &dra7xx_timer_hwmod_class,
2351         .clkdm_name     = "l4per_clkdm",
2352         .main_clk       = "timer11_gfclk_mux",
2353         .prcm = {
2354                 .omap4 = {
2355                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2356                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2357                         .modulemode   = MODULEMODE_SWCTRL,
2358                 },
2359         },
2360 };
2361
2362 /* timer12 */
2363 static struct omap_hwmod dra7xx_timer12_hwmod = {
2364         .name           = "timer12",
2365         .class          = &dra7xx_timer_hwmod_class,
2366         .clkdm_name     = "wkupaon_clkdm",
2367         .main_clk       = "secure_32k_clk_src_ck",
2368         .prcm = {
2369                 .omap4 = {
2370                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2371                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2372                 },
2373         },
2374 };
2375
2376 /* timer13 */
2377 static struct omap_hwmod dra7xx_timer13_hwmod = {
2378         .name           = "timer13",
2379         .class          = &dra7xx_timer_hwmod_class,
2380         .clkdm_name     = "l4per3_clkdm",
2381         .main_clk       = "timer13_gfclk_mux",
2382         .prcm = {
2383                 .omap4 = {
2384                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2385                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2386                         .modulemode   = MODULEMODE_SWCTRL,
2387                 },
2388         },
2389 };
2390
2391 /* timer14 */
2392 static struct omap_hwmod dra7xx_timer14_hwmod = {
2393         .name           = "timer14",
2394         .class          = &dra7xx_timer_hwmod_class,
2395         .clkdm_name     = "l4per3_clkdm",
2396         .main_clk       = "timer14_gfclk_mux",
2397         .prcm = {
2398                 .omap4 = {
2399                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2400                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2401                         .modulemode   = MODULEMODE_SWCTRL,
2402                 },
2403         },
2404 };
2405
2406 /* timer15 */
2407 static struct omap_hwmod dra7xx_timer15_hwmod = {
2408         .name           = "timer15",
2409         .class          = &dra7xx_timer_hwmod_class,
2410         .clkdm_name     = "l4per3_clkdm",
2411         .main_clk       = "timer15_gfclk_mux",
2412         .prcm = {
2413                 .omap4 = {
2414                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2415                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2416                         .modulemode   = MODULEMODE_SWCTRL,
2417                 },
2418         },
2419 };
2420
2421 /* timer16 */
2422 static struct omap_hwmod dra7xx_timer16_hwmod = {
2423         .name           = "timer16",
2424         .class          = &dra7xx_timer_hwmod_class,
2425         .clkdm_name     = "l4per3_clkdm",
2426         .main_clk       = "timer16_gfclk_mux",
2427         .prcm = {
2428                 .omap4 = {
2429                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2430                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2431                         .modulemode   = MODULEMODE_SWCTRL,
2432                 },
2433         },
2434 };
2435
2436 /*
2437  * 'uart' class
2438  *
2439  */
2440
2441 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2442         .rev_offs       = 0x0050,
2443         .sysc_offs      = 0x0054,
2444         .syss_offs      = 0x0058,
2445         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2446                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2447                            SYSS_HAS_RESET_STATUS),
2448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2449                            SIDLE_SMART_WKUP),
2450         .sysc_fields    = &omap_hwmod_sysc_type1,
2451 };
2452
2453 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2454         .name   = "uart",
2455         .sysc   = &dra7xx_uart_sysc,
2456 };
2457
2458 /* uart1 */
2459 static struct omap_hwmod dra7xx_uart1_hwmod = {
2460         .name           = "uart1",
2461         .class          = &dra7xx_uart_hwmod_class,
2462         .clkdm_name     = "l4per_clkdm",
2463         .main_clk       = "uart1_gfclk_mux",
2464         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2465         .prcm = {
2466                 .omap4 = {
2467                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2468                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2469                         .modulemode   = MODULEMODE_SWCTRL,
2470                 },
2471         },
2472 };
2473
2474 /* uart2 */
2475 static struct omap_hwmod dra7xx_uart2_hwmod = {
2476         .name           = "uart2",
2477         .class          = &dra7xx_uart_hwmod_class,
2478         .clkdm_name     = "l4per_clkdm",
2479         .main_clk       = "uart2_gfclk_mux",
2480         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2481         .prcm = {
2482                 .omap4 = {
2483                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2484                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2485                         .modulemode   = MODULEMODE_SWCTRL,
2486                 },
2487         },
2488 };
2489
2490 /* uart3 */
2491 static struct omap_hwmod dra7xx_uart3_hwmod = {
2492         .name           = "uart3",
2493         .class          = &dra7xx_uart_hwmod_class,
2494         .clkdm_name     = "l4per_clkdm",
2495         .main_clk       = "uart3_gfclk_mux",
2496         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2497         .prcm = {
2498                 .omap4 = {
2499                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2500                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2501                         .modulemode   = MODULEMODE_SWCTRL,
2502                 },
2503         },
2504 };
2505
2506 /* uart4 */
2507 static struct omap_hwmod dra7xx_uart4_hwmod = {
2508         .name           = "uart4",
2509         .class          = &dra7xx_uart_hwmod_class,
2510         .clkdm_name     = "l4per_clkdm",
2511         .main_clk       = "uart4_gfclk_mux",
2512         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2513         .prcm = {
2514                 .omap4 = {
2515                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2516                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2517                         .modulemode   = MODULEMODE_SWCTRL,
2518                 },
2519         },
2520 };
2521
2522 /* uart5 */
2523 static struct omap_hwmod dra7xx_uart5_hwmod = {
2524         .name           = "uart5",
2525         .class          = &dra7xx_uart_hwmod_class,
2526         .clkdm_name     = "l4per_clkdm",
2527         .main_clk       = "uart5_gfclk_mux",
2528         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2529         .prcm = {
2530                 .omap4 = {
2531                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2532                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2533                         .modulemode   = MODULEMODE_SWCTRL,
2534                 },
2535         },
2536 };
2537
2538 /* uart6 */
2539 static struct omap_hwmod dra7xx_uart6_hwmod = {
2540         .name           = "uart6",
2541         .class          = &dra7xx_uart_hwmod_class,
2542         .clkdm_name     = "ipu_clkdm",
2543         .main_clk       = "uart6_gfclk_mux",
2544         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2545         .prcm = {
2546                 .omap4 = {
2547                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2548                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2549                         .modulemode   = MODULEMODE_SWCTRL,
2550                 },
2551         },
2552 };
2553
2554 /* uart7 */
2555 static struct omap_hwmod dra7xx_uart7_hwmod = {
2556         .name           = "uart7",
2557         .class          = &dra7xx_uart_hwmod_class,
2558         .clkdm_name     = "l4per2_clkdm",
2559         .main_clk       = "uart7_gfclk_mux",
2560         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2561         .prcm = {
2562                 .omap4 = {
2563                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2564                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2565                         .modulemode   = MODULEMODE_SWCTRL,
2566                 },
2567         },
2568 };
2569
2570 /* uart8 */
2571 static struct omap_hwmod dra7xx_uart8_hwmod = {
2572         .name           = "uart8",
2573         .class          = &dra7xx_uart_hwmod_class,
2574         .clkdm_name     = "l4per2_clkdm",
2575         .main_clk       = "uart8_gfclk_mux",
2576         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2577         .prcm = {
2578                 .omap4 = {
2579                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2580                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2581                         .modulemode   = MODULEMODE_SWCTRL,
2582                 },
2583         },
2584 };
2585
2586 /* uart9 */
2587 static struct omap_hwmod dra7xx_uart9_hwmod = {
2588         .name           = "uart9",
2589         .class          = &dra7xx_uart_hwmod_class,
2590         .clkdm_name     = "l4per2_clkdm",
2591         .main_clk       = "uart9_gfclk_mux",
2592         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2593         .prcm = {
2594                 .omap4 = {
2595                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2596                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2597                         .modulemode   = MODULEMODE_SWCTRL,
2598                 },
2599         },
2600 };
2601
2602 /* uart10 */
2603 static struct omap_hwmod dra7xx_uart10_hwmod = {
2604         .name           = "uart10",
2605         .class          = &dra7xx_uart_hwmod_class,
2606         .clkdm_name     = "wkupaon_clkdm",
2607         .main_clk       = "uart10_gfclk_mux",
2608         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2609         .prcm = {
2610                 .omap4 = {
2611                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2612                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2613                         .modulemode   = MODULEMODE_SWCTRL,
2614                 },
2615         },
2616 };
2617
2618 /* DES (the 'P' (public) device) */
2619 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2620         .rev_offs       = 0x0030,
2621         .sysc_offs      = 0x0034,
2622         .syss_offs      = 0x0038,
2623         .sysc_flags     = SYSS_HAS_RESET_STATUS,
2624 };
2625
2626 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2627         .name   = "des",
2628         .sysc   = &dra7xx_des_sysc,
2629 };
2630
2631 /* DES */
2632 static struct omap_hwmod dra7xx_des_hwmod = {
2633         .name           = "des",
2634         .class          = &dra7xx_des_hwmod_class,
2635         .clkdm_name     = "l4sec_clkdm",
2636         .main_clk       = "l3_iclk_div",
2637         .prcm = {
2638                 .omap4 = {
2639                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2640                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2641                         .modulemode   = MODULEMODE_HWCTRL,
2642                 },
2643         },
2644 };
2645
2646 /* rng */
2647 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2648         .rev_offs       = 0x1fe0,
2649         .sysc_offs      = 0x1fe4,
2650         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2651         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
2652         .sysc_fields    = &omap_hwmod_sysc_type1,
2653 };
2654
2655 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2656         .name           = "rng",
2657         .sysc           = &dra7xx_rng_sysc,
2658 };
2659
2660 static struct omap_hwmod dra7xx_rng_hwmod = {
2661         .name           = "rng",
2662         .class          = &dra7xx_rng_hwmod_class,
2663         .flags          = HWMOD_SWSUP_SIDLE,
2664         .clkdm_name     = "l4sec_clkdm",
2665         .prcm = {
2666                 .omap4 = {
2667                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2668                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2669                         .modulemode   = MODULEMODE_HWCTRL,
2670                 },
2671         },
2672 };
2673
2674 /*
2675  * 'usb_otg_ss' class
2676  *
2677  */
2678
2679 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2680         .rev_offs       = 0x0000,
2681         .sysc_offs      = 0x0010,
2682         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2683                            SYSC_HAS_SIDLEMODE),
2684         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2685                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2686                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2687         .sysc_fields    = &omap_hwmod_sysc_type2,
2688 };
2689
2690 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2691         .name   = "usb_otg_ss",
2692         .sysc   = &dra7xx_usb_otg_ss_sysc,
2693 };
2694
2695 /* usb_otg_ss1 */
2696 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2697         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2698 };
2699
2700 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2701         .name           = "usb_otg_ss1",
2702         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2703         .clkdm_name     = "l3init_clkdm",
2704         .main_clk       = "dpll_core_h13x2_ck",
2705         .flags          = HWMOD_CLKDM_NOAUTO,
2706         .prcm = {
2707                 .omap4 = {
2708                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2709                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2710                         .modulemode   = MODULEMODE_HWCTRL,
2711                 },
2712         },
2713         .opt_clks       = usb_otg_ss1_opt_clks,
2714         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2715 };
2716
2717 /* usb_otg_ss2 */
2718 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2719         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2720 };
2721
2722 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2723         .name           = "usb_otg_ss2",
2724         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2725         .clkdm_name     = "l3init_clkdm",
2726         .main_clk       = "dpll_core_h13x2_ck",
2727         .flags          = HWMOD_CLKDM_NOAUTO,
2728         .prcm = {
2729                 .omap4 = {
2730                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2731                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2732                         .modulemode   = MODULEMODE_HWCTRL,
2733                 },
2734         },
2735         .opt_clks       = usb_otg_ss2_opt_clks,
2736         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2737 };
2738
2739 /* usb_otg_ss3 */
2740 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2741         .name           = "usb_otg_ss3",
2742         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2743         .clkdm_name     = "l3init_clkdm",
2744         .main_clk       = "dpll_core_h13x2_ck",
2745         .prcm = {
2746                 .omap4 = {
2747                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2748                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2749                         .modulemode   = MODULEMODE_HWCTRL,
2750                 },
2751         },
2752 };
2753
2754 /* usb_otg_ss4 */
2755 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2756         .name           = "usb_otg_ss4",
2757         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2758         .clkdm_name     = "l3init_clkdm",
2759         .main_clk       = "dpll_core_h13x2_ck",
2760         .prcm = {
2761                 .omap4 = {
2762                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2763                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2764                         .modulemode   = MODULEMODE_HWCTRL,
2765                 },
2766         },
2767 };
2768
2769 /*
2770  * 'vcp' class
2771  *
2772  */
2773
2774 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2775         .name   = "vcp",
2776 };
2777
2778 /* vcp1 */
2779 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2780         .name           = "vcp1",
2781         .class          = &dra7xx_vcp_hwmod_class,
2782         .clkdm_name     = "l3main1_clkdm",
2783         .main_clk       = "l3_iclk_div",
2784         .prcm = {
2785                 .omap4 = {
2786                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2787                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2788                 },
2789         },
2790 };
2791
2792 /* vcp2 */
2793 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2794         .name           = "vcp2",
2795         .class          = &dra7xx_vcp_hwmod_class,
2796         .clkdm_name     = "l3main1_clkdm",
2797         .main_clk       = "l3_iclk_div",
2798         .prcm = {
2799                 .omap4 = {
2800                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2801                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2802                 },
2803         },
2804 };
2805
2806 /*
2807  * 'wd_timer' class
2808  *
2809  */
2810
2811 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2812         .rev_offs       = 0x0000,
2813         .sysc_offs      = 0x0010,
2814         .syss_offs      = 0x0014,
2815         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2816                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2817         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2818                            SIDLE_SMART_WKUP),
2819         .sysc_fields    = &omap_hwmod_sysc_type1,
2820 };
2821
2822 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2823         .name           = "wd_timer",
2824         .sysc           = &dra7xx_wd_timer_sysc,
2825         .pre_shutdown   = &omap2_wd_timer_disable,
2826         .reset          = &omap2_wd_timer_reset,
2827 };
2828
2829 /* wd_timer2 */
2830 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2831         .name           = "wd_timer2",
2832         .class          = &dra7xx_wd_timer_hwmod_class,
2833         .clkdm_name     = "wkupaon_clkdm",
2834         .main_clk       = "sys_32k_ck",
2835         .prcm = {
2836                 .omap4 = {
2837                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2838                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2839                         .modulemode   = MODULEMODE_SWCTRL,
2840                 },
2841         },
2842 };
2843
2844
2845 /*
2846  * Interfaces
2847  */
2848
2849 /* l3_main_1 -> dmm */
2850 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2851         .master         = &dra7xx_l3_main_1_hwmod,
2852         .slave          = &dra7xx_dmm_hwmod,
2853         .clk            = "l3_iclk_div",
2854         .user           = OCP_USER_SDMA,
2855 };
2856
2857 /* l3_main_2 -> l3_instr */
2858 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2859         .master         = &dra7xx_l3_main_2_hwmod,
2860         .slave          = &dra7xx_l3_instr_hwmod,
2861         .clk            = "l3_iclk_div",
2862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2863 };
2864
2865 /* l4_cfg -> l3_main_1 */
2866 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2867         .master         = &dra7xx_l4_cfg_hwmod,
2868         .slave          = &dra7xx_l3_main_1_hwmod,
2869         .clk            = "l3_iclk_div",
2870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2871 };
2872
2873 /* mpu -> l3_main_1 */
2874 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2875         .master         = &dra7xx_mpu_hwmod,
2876         .slave          = &dra7xx_l3_main_1_hwmod,
2877         .clk            = "l3_iclk_div",
2878         .user           = OCP_USER_MPU,
2879 };
2880
2881 /* l3_main_1 -> l3_main_2 */
2882 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2883         .master         = &dra7xx_l3_main_1_hwmod,
2884         .slave          = &dra7xx_l3_main_2_hwmod,
2885         .clk            = "l3_iclk_div",
2886         .user           = OCP_USER_MPU,
2887 };
2888
2889 /* l4_cfg -> l3_main_2 */
2890 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2891         .master         = &dra7xx_l4_cfg_hwmod,
2892         .slave          = &dra7xx_l3_main_2_hwmod,
2893         .clk            = "l3_iclk_div",
2894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2895 };
2896
2897 /* l3_main_1 -> l4_cfg */
2898 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2899         .master         = &dra7xx_l3_main_1_hwmod,
2900         .slave          = &dra7xx_l4_cfg_hwmod,
2901         .clk            = "l3_iclk_div",
2902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2903 };
2904
2905 /* l3_main_1 -> l4_per1 */
2906 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2907         .master         = &dra7xx_l3_main_1_hwmod,
2908         .slave          = &dra7xx_l4_per1_hwmod,
2909         .clk            = "l3_iclk_div",
2910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2911 };
2912
2913 /* l3_main_1 -> l4_per2 */
2914 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2915         .master         = &dra7xx_l3_main_1_hwmod,
2916         .slave          = &dra7xx_l4_per2_hwmod,
2917         .clk            = "l3_iclk_div",
2918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2920
2921 /* l3_main_1 -> l4_per3 */
2922 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2923         .master         = &dra7xx_l3_main_1_hwmod,
2924         .slave          = &dra7xx_l4_per3_hwmod,
2925         .clk            = "l3_iclk_div",
2926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2927 };
2928
2929 /* l3_main_1 -> l4_wkup */
2930 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2931         .master         = &dra7xx_l3_main_1_hwmod,
2932         .slave          = &dra7xx_l4_wkup_hwmod,
2933         .clk            = "wkupaon_iclk_mux",
2934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2935 };
2936
2937 /* l4_per2 -> atl */
2938 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2939         .master         = &dra7xx_l4_per2_hwmod,
2940         .slave          = &dra7xx_atl_hwmod,
2941         .clk            = "l3_iclk_div",
2942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2943 };
2944
2945 /* l3_main_1 -> bb2d */
2946 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2947         .master         = &dra7xx_l3_main_1_hwmod,
2948         .slave          = &dra7xx_bb2d_hwmod,
2949         .clk            = "l3_iclk_div",
2950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2951 };
2952
2953 /* l4_wkup -> counter_32k */
2954 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2955         .master         = &dra7xx_l4_wkup_hwmod,
2956         .slave          = &dra7xx_counter_32k_hwmod,
2957         .clk            = "wkupaon_iclk_mux",
2958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2959 };
2960
2961 /* l4_wkup -> ctrl_module_wkup */
2962 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2963         .master         = &dra7xx_l4_wkup_hwmod,
2964         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2965         .clk            = "wkupaon_iclk_mux",
2966         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2967 };
2968
2969 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2970         .master         = &dra7xx_l4_per2_hwmod,
2971         .slave          = &dra7xx_gmac_hwmod,
2972         .clk            = "dpll_gmac_ck",
2973         .user           = OCP_USER_MPU,
2974 };
2975
2976 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2977         .master         = &dra7xx_gmac_hwmod,
2978         .slave          = &dra7xx_mdio_hwmod,
2979         .user           = OCP_USER_MPU,
2980 };
2981
2982 /* l4_wkup -> dcan1 */
2983 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2984         .master         = &dra7xx_l4_wkup_hwmod,
2985         .slave          = &dra7xx_dcan1_hwmod,
2986         .clk            = "wkupaon_iclk_mux",
2987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2988 };
2989
2990 /* l4_per2 -> dcan2 */
2991 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2992         .master         = &dra7xx_l4_per2_hwmod,
2993         .slave          = &dra7xx_dcan2_hwmod,
2994         .clk            = "l3_iclk_div",
2995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2996 };
2997
2998 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2999         {
3000                 .pa_start       = 0x4a056000,
3001                 .pa_end         = 0x4a056fff,
3002                 .flags          = ADDR_TYPE_RT
3003         },
3004         { }
3005 };
3006
3007 /* l4_cfg -> dma_system */
3008 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3009         .master         = &dra7xx_l4_cfg_hwmod,
3010         .slave          = &dra7xx_dma_system_hwmod,
3011         .clk            = "l3_iclk_div",
3012         .addr           = dra7xx_dma_system_addrs,
3013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3014 };
3015
3016 /* l3_main_1 -> tpcc */
3017 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
3018         .master         = &dra7xx_l3_main_1_hwmod,
3019         .slave          = &dra7xx_tpcc_hwmod,
3020         .clk            = "l3_iclk_div",
3021         .user           = OCP_USER_MPU,
3022 };
3023
3024 /* l3_main_1 -> tptc0 */
3025 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3026         .master         = &dra7xx_l3_main_1_hwmod,
3027         .slave          = &dra7xx_tptc0_hwmod,
3028         .clk            = "l3_iclk_div",
3029         .user           = OCP_USER_MPU,
3030 };
3031
3032 /* l3_main_1 -> tptc1 */
3033 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3034         .master         = &dra7xx_l3_main_1_hwmod,
3035         .slave          = &dra7xx_tptc1_hwmod,
3036         .clk            = "l3_iclk_div",
3037         .user           = OCP_USER_MPU,
3038 };
3039
3040 /* l3_main_1 -> dss */
3041 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3042         .master         = &dra7xx_l3_main_1_hwmod,
3043         .slave          = &dra7xx_dss_hwmod,
3044         .clk            = "l3_iclk_div",
3045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3046 };
3047
3048 /* l3_main_1 -> dispc */
3049 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3050         .master         = &dra7xx_l3_main_1_hwmod,
3051         .slave          = &dra7xx_dss_dispc_hwmod,
3052         .clk            = "l3_iclk_div",
3053         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3054 };
3055
3056 /* l3_main_1 -> dispc */
3057 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3058         .master         = &dra7xx_l3_main_1_hwmod,
3059         .slave          = &dra7xx_dss_hdmi_hwmod,
3060         .clk            = "l3_iclk_div",
3061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3062 };
3063
3064 /* l3_main_1 -> aes1 */
3065 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3066         .master         = &dra7xx_l3_main_1_hwmod,
3067         .slave          = &dra7xx_aes1_hwmod,
3068         .clk            = "l3_iclk_div",
3069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3070 };
3071
3072 /* l3_main_1 -> aes2 */
3073 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3074         .master         = &dra7xx_l3_main_1_hwmod,
3075         .slave          = &dra7xx_aes2_hwmod,
3076         .clk            = "l3_iclk_div",
3077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3078 };
3079
3080 /* l3_main_1 -> sha0 */
3081 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3082         .master         = &dra7xx_l3_main_1_hwmod,
3083         .slave          = &dra7xx_sha0_hwmod,
3084         .clk            = "l3_iclk_div",
3085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3086 };
3087
3088 /* l4_per2 -> mcasp1 */
3089 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3090         .master         = &dra7xx_l4_per2_hwmod,
3091         .slave          = &dra7xx_mcasp1_hwmod,
3092         .clk            = "l4_root_clk_div",
3093         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3094 };
3095
3096 /* l3_main_1 -> mcasp1 */
3097 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3098         .master         = &dra7xx_l3_main_1_hwmod,
3099         .slave          = &dra7xx_mcasp1_hwmod,
3100         .clk            = "l3_iclk_div",
3101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3102 };
3103
3104 /* l4_per2 -> mcasp2 */
3105 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3106         .master         = &dra7xx_l4_per2_hwmod,
3107         .slave          = &dra7xx_mcasp2_hwmod,
3108         .clk            = "l4_root_clk_div",
3109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3110 };
3111
3112 /* l3_main_1 -> mcasp2 */
3113 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3114         .master         = &dra7xx_l3_main_1_hwmod,
3115         .slave          = &dra7xx_mcasp2_hwmod,
3116         .clk            = "l3_iclk_div",
3117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3118 };
3119
3120 /* l4_per2 -> mcasp3 */
3121 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3122         .master         = &dra7xx_l4_per2_hwmod,
3123         .slave          = &dra7xx_mcasp3_hwmod,
3124         .clk            = "l4_root_clk_div",
3125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3126 };
3127
3128 /* l3_main_1 -> mcasp3 */
3129 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3130         .master         = &dra7xx_l3_main_1_hwmod,
3131         .slave          = &dra7xx_mcasp3_hwmod,
3132         .clk            = "l3_iclk_div",
3133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3134 };
3135
3136 /* l4_per2 -> mcasp4 */
3137 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3138         .master         = &dra7xx_l4_per2_hwmod,
3139         .slave          = &dra7xx_mcasp4_hwmod,
3140         .clk            = "l4_root_clk_div",
3141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3142 };
3143
3144 /* l4_per2 -> mcasp5 */
3145 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3146         .master         = &dra7xx_l4_per2_hwmod,
3147         .slave          = &dra7xx_mcasp5_hwmod,
3148         .clk            = "l4_root_clk_div",
3149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3150 };
3151
3152 /* l4_per2 -> mcasp6 */
3153 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3154         .master         = &dra7xx_l4_per2_hwmod,
3155         .slave          = &dra7xx_mcasp6_hwmod,
3156         .clk            = "l4_root_clk_div",
3157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3158 };
3159
3160 /* l4_per2 -> mcasp7 */
3161 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3162         .master         = &dra7xx_l4_per2_hwmod,
3163         .slave          = &dra7xx_mcasp7_hwmod,
3164         .clk            = "l4_root_clk_div",
3165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3166 };
3167
3168 /* l4_per2 -> mcasp8 */
3169 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3170         .master         = &dra7xx_l4_per2_hwmod,
3171         .slave          = &dra7xx_mcasp8_hwmod,
3172         .clk            = "l4_root_clk_div",
3173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3174 };
3175
3176 /* l4_per1 -> elm */
3177 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3178         .master         = &dra7xx_l4_per1_hwmod,
3179         .slave          = &dra7xx_elm_hwmod,
3180         .clk            = "l3_iclk_div",
3181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3182 };
3183
3184 /* l4_wkup -> gpio1 */
3185 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3186         .master         = &dra7xx_l4_wkup_hwmod,
3187         .slave          = &dra7xx_gpio1_hwmod,
3188         .clk            = "wkupaon_iclk_mux",
3189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3190 };
3191
3192 /* l4_per1 -> gpio2 */
3193 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3194         .master         = &dra7xx_l4_per1_hwmod,
3195         .slave          = &dra7xx_gpio2_hwmod,
3196         .clk            = "l3_iclk_div",
3197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3198 };
3199
3200 /* l4_per1 -> gpio3 */
3201 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3202         .master         = &dra7xx_l4_per1_hwmod,
3203         .slave          = &dra7xx_gpio3_hwmod,
3204         .clk            = "l3_iclk_div",
3205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3206 };
3207
3208 /* l4_per1 -> gpio4 */
3209 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3210         .master         = &dra7xx_l4_per1_hwmod,
3211         .slave          = &dra7xx_gpio4_hwmod,
3212         .clk            = "l3_iclk_div",
3213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3214 };
3215
3216 /* l4_per1 -> gpio5 */
3217 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3218         .master         = &dra7xx_l4_per1_hwmod,
3219         .slave          = &dra7xx_gpio5_hwmod,
3220         .clk            = "l3_iclk_div",
3221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3222 };
3223
3224 /* l4_per1 -> gpio6 */
3225 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3226         .master         = &dra7xx_l4_per1_hwmod,
3227         .slave          = &dra7xx_gpio6_hwmod,
3228         .clk            = "l3_iclk_div",
3229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3230 };
3231
3232 /* l4_per1 -> gpio7 */
3233 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3234         .master         = &dra7xx_l4_per1_hwmod,
3235         .slave          = &dra7xx_gpio7_hwmod,
3236         .clk            = "l3_iclk_div",
3237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3238 };
3239
3240 /* l4_per1 -> gpio8 */
3241 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3242         .master         = &dra7xx_l4_per1_hwmod,
3243         .slave          = &dra7xx_gpio8_hwmod,
3244         .clk            = "l3_iclk_div",
3245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3246 };
3247
3248 /* l3_main_1 -> gpmc */
3249 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3250         .master         = &dra7xx_l3_main_1_hwmod,
3251         .slave          = &dra7xx_gpmc_hwmod,
3252         .clk            = "l3_iclk_div",
3253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3254 };
3255
3256 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3257         {
3258                 .pa_start       = 0x480b2000,
3259                 .pa_end         = 0x480b201f,
3260                 .flags          = ADDR_TYPE_RT
3261         },
3262         { }
3263 };
3264
3265 /* l4_per1 -> hdq1w */
3266 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3267         .master         = &dra7xx_l4_per1_hwmod,
3268         .slave          = &dra7xx_hdq1w_hwmod,
3269         .clk            = "l3_iclk_div",
3270         .addr           = dra7xx_hdq1w_addrs,
3271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3273
3274 /* l4_per1 -> i2c1 */
3275 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3276         .master         = &dra7xx_l4_per1_hwmod,
3277         .slave          = &dra7xx_i2c1_hwmod,
3278         .clk            = "l3_iclk_div",
3279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3281
3282 /* l4_per1 -> i2c2 */
3283 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3284         .master         = &dra7xx_l4_per1_hwmod,
3285         .slave          = &dra7xx_i2c2_hwmod,
3286         .clk            = "l3_iclk_div",
3287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3289
3290 /* l4_per1 -> i2c3 */
3291 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3292         .master         = &dra7xx_l4_per1_hwmod,
3293         .slave          = &dra7xx_i2c3_hwmod,
3294         .clk            = "l3_iclk_div",
3295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3297
3298 /* l4_per1 -> i2c4 */
3299 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3300         .master         = &dra7xx_l4_per1_hwmod,
3301         .slave          = &dra7xx_i2c4_hwmod,
3302         .clk            = "l3_iclk_div",
3303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* l4_per1 -> i2c5 */
3307 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3308         .master         = &dra7xx_l4_per1_hwmod,
3309         .slave          = &dra7xx_i2c5_hwmod,
3310         .clk            = "l3_iclk_div",
3311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l4_cfg -> mailbox1 */
3315 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3316         .master         = &dra7xx_l4_cfg_hwmod,
3317         .slave          = &dra7xx_mailbox1_hwmod,
3318         .clk            = "l3_iclk_div",
3319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3321
3322 /* l4_per3 -> mailbox2 */
3323 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3324         .master         = &dra7xx_l4_per3_hwmod,
3325         .slave          = &dra7xx_mailbox2_hwmod,
3326         .clk            = "l3_iclk_div",
3327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3329
3330 /* l4_per3 -> mailbox3 */
3331 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3332         .master         = &dra7xx_l4_per3_hwmod,
3333         .slave          = &dra7xx_mailbox3_hwmod,
3334         .clk            = "l3_iclk_div",
3335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3337
3338 /* l4_per3 -> mailbox4 */
3339 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3340         .master         = &dra7xx_l4_per3_hwmod,
3341         .slave          = &dra7xx_mailbox4_hwmod,
3342         .clk            = "l3_iclk_div",
3343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3345
3346 /* l4_per3 -> mailbox5 */
3347 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3348         .master         = &dra7xx_l4_per3_hwmod,
3349         .slave          = &dra7xx_mailbox5_hwmod,
3350         .clk            = "l3_iclk_div",
3351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3352 };
3353
3354 /* l4_per3 -> mailbox6 */
3355 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3356         .master         = &dra7xx_l4_per3_hwmod,
3357         .slave          = &dra7xx_mailbox6_hwmod,
3358         .clk            = "l3_iclk_div",
3359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3360 };
3361
3362 /* l4_per3 -> mailbox7 */
3363 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3364         .master         = &dra7xx_l4_per3_hwmod,
3365         .slave          = &dra7xx_mailbox7_hwmod,
3366         .clk            = "l3_iclk_div",
3367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3369
3370 /* l4_per3 -> mailbox8 */
3371 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3372         .master         = &dra7xx_l4_per3_hwmod,
3373         .slave          = &dra7xx_mailbox8_hwmod,
3374         .clk            = "l3_iclk_div",
3375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3377
3378 /* l4_per3 -> mailbox9 */
3379 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3380         .master         = &dra7xx_l4_per3_hwmod,
3381         .slave          = &dra7xx_mailbox9_hwmod,
3382         .clk            = "l3_iclk_div",
3383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3385
3386 /* l4_per3 -> mailbox10 */
3387 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3388         .master         = &dra7xx_l4_per3_hwmod,
3389         .slave          = &dra7xx_mailbox10_hwmod,
3390         .clk            = "l3_iclk_div",
3391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3393
3394 /* l4_per3 -> mailbox11 */
3395 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3396         .master         = &dra7xx_l4_per3_hwmod,
3397         .slave          = &dra7xx_mailbox11_hwmod,
3398         .clk            = "l3_iclk_div",
3399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3401
3402 /* l4_per3 -> mailbox12 */
3403 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3404         .master         = &dra7xx_l4_per3_hwmod,
3405         .slave          = &dra7xx_mailbox12_hwmod,
3406         .clk            = "l3_iclk_div",
3407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3408 };
3409
3410 /* l4_per3 -> mailbox13 */
3411 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3412         .master         = &dra7xx_l4_per3_hwmod,
3413         .slave          = &dra7xx_mailbox13_hwmod,
3414         .clk            = "l3_iclk_div",
3415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 /* l4_per1 -> mcspi1 */
3419 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3420         .master         = &dra7xx_l4_per1_hwmod,
3421         .slave          = &dra7xx_mcspi1_hwmod,
3422         .clk            = "l3_iclk_div",
3423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3425
3426 /* l4_per1 -> mcspi2 */
3427 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3428         .master         = &dra7xx_l4_per1_hwmod,
3429         .slave          = &dra7xx_mcspi2_hwmod,
3430         .clk            = "l3_iclk_div",
3431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3432 };
3433
3434 /* l4_per1 -> mcspi3 */
3435 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3436         .master         = &dra7xx_l4_per1_hwmod,
3437         .slave          = &dra7xx_mcspi3_hwmod,
3438         .clk            = "l3_iclk_div",
3439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3440 };
3441
3442 /* l4_per1 -> mcspi4 */
3443 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3444         .master         = &dra7xx_l4_per1_hwmod,
3445         .slave          = &dra7xx_mcspi4_hwmod,
3446         .clk            = "l3_iclk_div",
3447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3448 };
3449
3450 /* l4_per1 -> mmc1 */
3451 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3452         .master         = &dra7xx_l4_per1_hwmod,
3453         .slave          = &dra7xx_mmc1_hwmod,
3454         .clk            = "l3_iclk_div",
3455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3456 };
3457
3458 /* l4_per1 -> mmc2 */
3459 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3460         .master         = &dra7xx_l4_per1_hwmod,
3461         .slave          = &dra7xx_mmc2_hwmod,
3462         .clk            = "l3_iclk_div",
3463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3464 };
3465
3466 /* l4_per1 -> mmc3 */
3467 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3468         .master         = &dra7xx_l4_per1_hwmod,
3469         .slave          = &dra7xx_mmc3_hwmod,
3470         .clk            = "l3_iclk_div",
3471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3472 };
3473
3474 /* l4_per1 -> mmc4 */
3475 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3476         .master         = &dra7xx_l4_per1_hwmod,
3477         .slave          = &dra7xx_mmc4_hwmod,
3478         .clk            = "l3_iclk_div",
3479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3480 };
3481
3482 /* l4_cfg -> mpu */
3483 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3484         .master         = &dra7xx_l4_cfg_hwmod,
3485         .slave          = &dra7xx_mpu_hwmod,
3486         .clk            = "l3_iclk_div",
3487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3488 };
3489
3490 /* l4_cfg -> ocp2scp1 */
3491 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3492         .master         = &dra7xx_l4_cfg_hwmod,
3493         .slave          = &dra7xx_ocp2scp1_hwmod,
3494         .clk            = "l4_root_clk_div",
3495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3496 };
3497
3498 /* l4_cfg -> ocp2scp3 */
3499 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3500         .master         = &dra7xx_l4_cfg_hwmod,
3501         .slave          = &dra7xx_ocp2scp3_hwmod,
3502         .clk            = "l4_root_clk_div",
3503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3504 };
3505
3506 /* l3_main_1 -> pciess1 */
3507 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3508         .master         = &dra7xx_l3_main_1_hwmod,
3509         .slave          = &dra7xx_pciess1_hwmod,
3510         .clk            = "l3_iclk_div",
3511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3512 };
3513
3514 /* l4_cfg -> pciess1 */
3515 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3516         .master         = &dra7xx_l4_cfg_hwmod,
3517         .slave          = &dra7xx_pciess1_hwmod,
3518         .clk            = "l4_root_clk_div",
3519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3520 };
3521
3522 /* l3_main_1 -> pciess2 */
3523 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3524         .master         = &dra7xx_l3_main_1_hwmod,
3525         .slave          = &dra7xx_pciess2_hwmod,
3526         .clk            = "l3_iclk_div",
3527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3528 };
3529
3530 /* l4_cfg -> pciess2 */
3531 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3532         .master         = &dra7xx_l4_cfg_hwmod,
3533         .slave          = &dra7xx_pciess2_hwmod,
3534         .clk            = "l4_root_clk_div",
3535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3536 };
3537
3538 /* l3_main_1 -> qspi */
3539 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3540         .master         = &dra7xx_l3_main_1_hwmod,
3541         .slave          = &dra7xx_qspi_hwmod,
3542         .clk            = "l3_iclk_div",
3543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3544 };
3545
3546 /* l4_per3 -> rtcss */
3547 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3548         .master         = &dra7xx_l4_per3_hwmod,
3549         .slave          = &dra7xx_rtcss_hwmod,
3550         .clk            = "l4_root_clk_div",
3551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3552 };
3553
3554 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3555         {
3556                 .name           = "sysc",
3557                 .pa_start       = 0x4a141100,
3558                 .pa_end         = 0x4a141107,
3559                 .flags          = ADDR_TYPE_RT
3560         },
3561         { }
3562 };
3563
3564 /* l4_cfg -> sata */
3565 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3566         .master         = &dra7xx_l4_cfg_hwmod,
3567         .slave          = &dra7xx_sata_hwmod,
3568         .clk            = "l3_iclk_div",
3569         .addr           = dra7xx_sata_addrs,
3570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3571 };
3572
3573 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3574         {
3575                 .pa_start       = 0x4a0dd000,
3576                 .pa_end         = 0x4a0dd07f,
3577                 .flags          = ADDR_TYPE_RT
3578         },
3579         { }
3580 };
3581
3582 /* l4_cfg -> smartreflex_core */
3583 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3584         .master         = &dra7xx_l4_cfg_hwmod,
3585         .slave          = &dra7xx_smartreflex_core_hwmod,
3586         .clk            = "l4_root_clk_div",
3587         .addr           = dra7xx_smartreflex_core_addrs,
3588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3589 };
3590
3591 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3592         {
3593                 .pa_start       = 0x4a0d9000,
3594                 .pa_end         = 0x4a0d907f,
3595                 .flags          = ADDR_TYPE_RT
3596         },
3597         { }
3598 };
3599
3600 /* l4_cfg -> smartreflex_mpu */
3601 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3602         .master         = &dra7xx_l4_cfg_hwmod,
3603         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3604         .clk            = "l4_root_clk_div",
3605         .addr           = dra7xx_smartreflex_mpu_addrs,
3606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3607 };
3608
3609 /* l4_cfg -> spinlock */
3610 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3611         .master         = &dra7xx_l4_cfg_hwmod,
3612         .slave          = &dra7xx_spinlock_hwmod,
3613         .clk            = "l3_iclk_div",
3614         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3615 };
3616
3617 /* l4_wkup -> timer1 */
3618 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3619         .master         = &dra7xx_l4_wkup_hwmod,
3620         .slave          = &dra7xx_timer1_hwmod,
3621         .clk            = "wkupaon_iclk_mux",
3622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3623 };
3624
3625 /* l4_per1 -> timer2 */
3626 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3627         .master         = &dra7xx_l4_per1_hwmod,
3628         .slave          = &dra7xx_timer2_hwmod,
3629         .clk            = "l3_iclk_div",
3630         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3631 };
3632
3633 /* l4_per1 -> timer3 */
3634 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3635         .master         = &dra7xx_l4_per1_hwmod,
3636         .slave          = &dra7xx_timer3_hwmod,
3637         .clk            = "l3_iclk_div",
3638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3640
3641 /* l4_per1 -> timer4 */
3642 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3643         .master         = &dra7xx_l4_per1_hwmod,
3644         .slave          = &dra7xx_timer4_hwmod,
3645         .clk            = "l3_iclk_div",
3646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3648
3649 /* l4_per3 -> timer5 */
3650 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3651         .master         = &dra7xx_l4_per3_hwmod,
3652         .slave          = &dra7xx_timer5_hwmod,
3653         .clk            = "l3_iclk_div",
3654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3655 };
3656
3657 /* l4_per3 -> timer6 */
3658 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3659         .master         = &dra7xx_l4_per3_hwmod,
3660         .slave          = &dra7xx_timer6_hwmod,
3661         .clk            = "l3_iclk_div",
3662         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3663 };
3664
3665 /* l4_per3 -> timer7 */
3666 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3667         .master         = &dra7xx_l4_per3_hwmod,
3668         .slave          = &dra7xx_timer7_hwmod,
3669         .clk            = "l3_iclk_div",
3670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3671 };
3672
3673 /* l4_per3 -> timer8 */
3674 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3675         .master         = &dra7xx_l4_per3_hwmod,
3676         .slave          = &dra7xx_timer8_hwmod,
3677         .clk            = "l3_iclk_div",
3678         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3679 };
3680
3681 /* l4_per1 -> timer9 */
3682 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3683         .master         = &dra7xx_l4_per1_hwmod,
3684         .slave          = &dra7xx_timer9_hwmod,
3685         .clk            = "l3_iclk_div",
3686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3687 };
3688
3689 /* l4_per1 -> timer10 */
3690 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3691         .master         = &dra7xx_l4_per1_hwmod,
3692         .slave          = &dra7xx_timer10_hwmod,
3693         .clk            = "l3_iclk_div",
3694         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3695 };
3696
3697 /* l4_per1 -> timer11 */
3698 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3699         .master         = &dra7xx_l4_per1_hwmod,
3700         .slave          = &dra7xx_timer11_hwmod,
3701         .clk            = "l3_iclk_div",
3702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3703 };
3704
3705 /* l4_wkup -> timer12 */
3706 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3707         .master         = &dra7xx_l4_wkup_hwmod,
3708         .slave          = &dra7xx_timer12_hwmod,
3709         .clk            = "wkupaon_iclk_mux",
3710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3711 };
3712
3713 /* l4_per3 -> timer13 */
3714 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3715         .master         = &dra7xx_l4_per3_hwmod,
3716         .slave          = &dra7xx_timer13_hwmod,
3717         .clk            = "l3_iclk_div",
3718         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3719 };
3720
3721 /* l4_per3 -> timer14 */
3722 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3723         .master         = &dra7xx_l4_per3_hwmod,
3724         .slave          = &dra7xx_timer14_hwmod,
3725         .clk            = "l3_iclk_div",
3726         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3727 };
3728
3729 /* l4_per3 -> timer15 */
3730 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3731         .master         = &dra7xx_l4_per3_hwmod,
3732         .slave          = &dra7xx_timer15_hwmod,
3733         .clk            = "l3_iclk_div",
3734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3735 };
3736
3737 /* l4_per3 -> timer16 */
3738 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3739         .master         = &dra7xx_l4_per3_hwmod,
3740         .slave          = &dra7xx_timer16_hwmod,
3741         .clk            = "l3_iclk_div",
3742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3743 };
3744
3745 /* l4_per1 -> uart1 */
3746 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3747         .master         = &dra7xx_l4_per1_hwmod,
3748         .slave          = &dra7xx_uart1_hwmod,
3749         .clk            = "l3_iclk_div",
3750         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3751 };
3752
3753 /* l4_per1 -> uart2 */
3754 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3755         .master         = &dra7xx_l4_per1_hwmod,
3756         .slave          = &dra7xx_uart2_hwmod,
3757         .clk            = "l3_iclk_div",
3758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3759 };
3760
3761 /* l4_per1 -> uart3 */
3762 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3763         .master         = &dra7xx_l4_per1_hwmod,
3764         .slave          = &dra7xx_uart3_hwmod,
3765         .clk            = "l3_iclk_div",
3766         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3767 };
3768
3769 /* l4_per1 -> uart4 */
3770 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3771         .master         = &dra7xx_l4_per1_hwmod,
3772         .slave          = &dra7xx_uart4_hwmod,
3773         .clk            = "l3_iclk_div",
3774         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3775 };
3776
3777 /* l4_per1 -> uart5 */
3778 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3779         .master         = &dra7xx_l4_per1_hwmod,
3780         .slave          = &dra7xx_uart5_hwmod,
3781         .clk            = "l3_iclk_div",
3782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3783 };
3784
3785 /* l4_per1 -> uart6 */
3786 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3787         .master         = &dra7xx_l4_per1_hwmod,
3788         .slave          = &dra7xx_uart6_hwmod,
3789         .clk            = "l3_iclk_div",
3790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3791 };
3792
3793 /* l4_per2 -> uart7 */
3794 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3795         .master         = &dra7xx_l4_per2_hwmod,
3796         .slave          = &dra7xx_uart7_hwmod,
3797         .clk            = "l3_iclk_div",
3798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3799 };
3800
3801 /* l4_per1 -> des */
3802 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3803         .master         = &dra7xx_l4_per1_hwmod,
3804         .slave          = &dra7xx_des_hwmod,
3805         .clk            = "l3_iclk_div",
3806         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3807 };
3808
3809 /* l4_per2 -> uart8 */
3810 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3811         .master         = &dra7xx_l4_per2_hwmod,
3812         .slave          = &dra7xx_uart8_hwmod,
3813         .clk            = "l3_iclk_div",
3814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3815 };
3816
3817 /* l4_per2 -> uart9 */
3818 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3819         .master         = &dra7xx_l4_per2_hwmod,
3820         .slave          = &dra7xx_uart9_hwmod,
3821         .clk            = "l3_iclk_div",
3822         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3823 };
3824
3825 /* l4_wkup -> uart10 */
3826 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3827         .master         = &dra7xx_l4_wkup_hwmod,
3828         .slave          = &dra7xx_uart10_hwmod,
3829         .clk            = "wkupaon_iclk_mux",
3830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3831 };
3832
3833 /* l4_per1 -> rng */
3834 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3835         .master         = &dra7xx_l4_per1_hwmod,
3836         .slave          = &dra7xx_rng_hwmod,
3837         .user           = OCP_USER_MPU,
3838 };
3839
3840 /* l4_per3 -> usb_otg_ss1 */
3841 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3842         .master         = &dra7xx_l4_per3_hwmod,
3843         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3844         .clk            = "dpll_core_h13x2_ck",
3845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3846 };
3847
3848 /* l4_per3 -> usb_otg_ss2 */
3849 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3850         .master         = &dra7xx_l4_per3_hwmod,
3851         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3852         .clk            = "dpll_core_h13x2_ck",
3853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3854 };
3855
3856 /* l4_per3 -> usb_otg_ss3 */
3857 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3858         .master         = &dra7xx_l4_per3_hwmod,
3859         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3860         .clk            = "dpll_core_h13x2_ck",
3861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3862 };
3863
3864 /* l4_per3 -> usb_otg_ss4 */
3865 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3866         .master         = &dra7xx_l4_per3_hwmod,
3867         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3868         .clk            = "dpll_core_h13x2_ck",
3869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3870 };
3871
3872 /* l3_main_1 -> vcp1 */
3873 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3874         .master         = &dra7xx_l3_main_1_hwmod,
3875         .slave          = &dra7xx_vcp1_hwmod,
3876         .clk            = "l3_iclk_div",
3877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3878 };
3879
3880 /* l4_per2 -> vcp1 */
3881 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3882         .master         = &dra7xx_l4_per2_hwmod,
3883         .slave          = &dra7xx_vcp1_hwmod,
3884         .clk            = "l3_iclk_div",
3885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3886 };
3887
3888 /* l3_main_1 -> vcp2 */
3889 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3890         .master         = &dra7xx_l3_main_1_hwmod,
3891         .slave          = &dra7xx_vcp2_hwmod,
3892         .clk            = "l3_iclk_div",
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 /* l4_per2 -> vcp2 */
3897 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3898         .master         = &dra7xx_l4_per2_hwmod,
3899         .slave          = &dra7xx_vcp2_hwmod,
3900         .clk            = "l3_iclk_div",
3901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3902 };
3903
3904 /* l4_wkup -> wd_timer2 */
3905 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3906         .master         = &dra7xx_l4_wkup_hwmod,
3907         .slave          = &dra7xx_wd_timer2_hwmod,
3908         .clk            = "wkupaon_iclk_mux",
3909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3910 };
3911
3912 /* l4_per2 -> epwmss0 */
3913 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3914         .master         = &dra7xx_l4_per2_hwmod,
3915         .slave          = &dra7xx_epwmss0_hwmod,
3916         .clk            = "l4_root_clk_div",
3917         .user           = OCP_USER_MPU,
3918 };
3919
3920 /* l4_per2 -> epwmss1 */
3921 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3922         .master         = &dra7xx_l4_per2_hwmod,
3923         .slave          = &dra7xx_epwmss1_hwmod,
3924         .clk            = "l4_root_clk_div",
3925         .user           = OCP_USER_MPU,
3926 };
3927
3928 /* l4_per2 -> epwmss2 */
3929 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3930         .master         = &dra7xx_l4_per2_hwmod,
3931         .slave          = &dra7xx_epwmss2_hwmod,
3932         .clk            = "l4_root_clk_div",
3933         .user           = OCP_USER_MPU,
3934 };
3935
3936 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3937         &dra7xx_l3_main_1__dmm,
3938         &dra7xx_l3_main_2__l3_instr,
3939         &dra7xx_l4_cfg__l3_main_1,
3940         &dra7xx_mpu__l3_main_1,
3941         &dra7xx_l3_main_1__l3_main_2,
3942         &dra7xx_l4_cfg__l3_main_2,
3943         &dra7xx_l3_main_1__l4_cfg,
3944         &dra7xx_l3_main_1__l4_per1,
3945         &dra7xx_l3_main_1__l4_per2,
3946         &dra7xx_l3_main_1__l4_per3,
3947         &dra7xx_l3_main_1__l4_wkup,
3948         &dra7xx_l4_per2__atl,
3949         &dra7xx_l3_main_1__bb2d,
3950         &dra7xx_l4_wkup__counter_32k,
3951         &dra7xx_l4_wkup__ctrl_module_wkup,
3952         &dra7xx_l4_wkup__dcan1,
3953         &dra7xx_l4_per2__dcan2,
3954         &dra7xx_l4_per2__cpgmac0,
3955         &dra7xx_l4_per2__mcasp1,
3956         &dra7xx_l3_main_1__mcasp1,
3957         &dra7xx_l4_per2__mcasp2,
3958         &dra7xx_l3_main_1__mcasp2,
3959         &dra7xx_l4_per2__mcasp3,
3960         &dra7xx_l3_main_1__mcasp3,
3961         &dra7xx_l4_per2__mcasp4,
3962         &dra7xx_l4_per2__mcasp5,
3963         &dra7xx_l4_per2__mcasp6,
3964         &dra7xx_l4_per2__mcasp7,
3965         &dra7xx_l4_per2__mcasp8,
3966         &dra7xx_gmac__mdio,
3967         &dra7xx_l4_cfg__dma_system,
3968         &dra7xx_l3_main_1__tpcc,
3969         &dra7xx_l3_main_1__tptc0,
3970         &dra7xx_l3_main_1__tptc1,
3971         &dra7xx_l3_main_1__dss,
3972         &dra7xx_l3_main_1__dispc,
3973         &dra7xx_l3_main_1__hdmi,
3974         &dra7xx_l3_main_1__aes1,
3975         &dra7xx_l3_main_1__aes2,
3976         &dra7xx_l3_main_1__sha0,
3977         &dra7xx_l4_per1__elm,
3978         &dra7xx_l4_wkup__gpio1,
3979         &dra7xx_l4_per1__gpio2,
3980         &dra7xx_l4_per1__gpio3,
3981         &dra7xx_l4_per1__gpio4,
3982         &dra7xx_l4_per1__gpio5,
3983         &dra7xx_l4_per1__gpio6,
3984         &dra7xx_l4_per1__gpio7,
3985         &dra7xx_l4_per1__gpio8,
3986         &dra7xx_l3_main_1__gpmc,
3987         &dra7xx_l4_per1__hdq1w,
3988         &dra7xx_l4_per1__i2c1,
3989         &dra7xx_l4_per1__i2c2,
3990         &dra7xx_l4_per1__i2c3,
3991         &dra7xx_l4_per1__i2c4,
3992         &dra7xx_l4_per1__i2c5,
3993         &dra7xx_l4_cfg__mailbox1,
3994         &dra7xx_l4_per3__mailbox2,
3995         &dra7xx_l4_per3__mailbox3,
3996         &dra7xx_l4_per3__mailbox4,
3997         &dra7xx_l4_per3__mailbox5,
3998         &dra7xx_l4_per3__mailbox6,
3999         &dra7xx_l4_per3__mailbox7,
4000         &dra7xx_l4_per3__mailbox8,
4001         &dra7xx_l4_per3__mailbox9,
4002         &dra7xx_l4_per3__mailbox10,
4003         &dra7xx_l4_per3__mailbox11,
4004         &dra7xx_l4_per3__mailbox12,
4005         &dra7xx_l4_per3__mailbox13,
4006         &dra7xx_l4_per1__mcspi1,
4007         &dra7xx_l4_per1__mcspi2,
4008         &dra7xx_l4_per1__mcspi3,
4009         &dra7xx_l4_per1__mcspi4,
4010         &dra7xx_l4_per1__mmc1,
4011         &dra7xx_l4_per1__mmc2,
4012         &dra7xx_l4_per1__mmc3,
4013         &dra7xx_l4_per1__mmc4,
4014         &dra7xx_l4_cfg__mpu,
4015         &dra7xx_l4_cfg__ocp2scp1,
4016         &dra7xx_l4_cfg__ocp2scp3,
4017         &dra7xx_l3_main_1__pciess1,
4018         &dra7xx_l4_cfg__pciess1,
4019         &dra7xx_l3_main_1__pciess2,
4020         &dra7xx_l4_cfg__pciess2,
4021         &dra7xx_l3_main_1__qspi,
4022         &dra7xx_l4_cfg__sata,
4023         &dra7xx_l4_cfg__smartreflex_core,
4024         &dra7xx_l4_cfg__smartreflex_mpu,
4025         &dra7xx_l4_cfg__spinlock,
4026         &dra7xx_l4_wkup__timer1,
4027         &dra7xx_l4_per1__timer2,
4028         &dra7xx_l4_per1__timer3,
4029         &dra7xx_l4_per1__timer4,
4030         &dra7xx_l4_per3__timer5,
4031         &dra7xx_l4_per3__timer6,
4032         &dra7xx_l4_per3__timer7,
4033         &dra7xx_l4_per3__timer8,
4034         &dra7xx_l4_per1__timer9,
4035         &dra7xx_l4_per1__timer10,
4036         &dra7xx_l4_per1__timer11,
4037         &dra7xx_l4_per3__timer13,
4038         &dra7xx_l4_per3__timer14,
4039         &dra7xx_l4_per3__timer15,
4040         &dra7xx_l4_per3__timer16,
4041         &dra7xx_l4_per1__uart1,
4042         &dra7xx_l4_per1__uart2,
4043         &dra7xx_l4_per1__uart3,
4044         &dra7xx_l4_per1__uart4,
4045         &dra7xx_l4_per1__uart5,
4046         &dra7xx_l4_per1__uart6,
4047         &dra7xx_l4_per2__uart7,
4048         &dra7xx_l4_per2__uart8,
4049         &dra7xx_l4_per2__uart9,
4050         &dra7xx_l4_wkup__uart10,
4051         &dra7xx_l4_per1__des,
4052         &dra7xx_l4_per3__usb_otg_ss1,
4053         &dra7xx_l4_per3__usb_otg_ss2,
4054         &dra7xx_l4_per3__usb_otg_ss3,
4055         &dra7xx_l3_main_1__vcp1,
4056         &dra7xx_l4_per2__vcp1,
4057         &dra7xx_l3_main_1__vcp2,
4058         &dra7xx_l4_per2__vcp2,
4059         &dra7xx_l4_wkup__wd_timer2,
4060         &dra7xx_l4_per2__epwmss0,
4061         &dra7xx_l4_per2__epwmss1,
4062         &dra7xx_l4_per2__epwmss2,
4063         NULL,
4064 };
4065
4066 /* GP-only hwmod links */
4067 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4068         &dra7xx_l4_wkup__timer12,
4069         &dra7xx_l4_per1__rng,
4070         NULL,
4071 };
4072
4073 /* SoC variant specific hwmod links */
4074 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
4075         &dra7xx_l4_per3__usb_otg_ss4,
4076         NULL,
4077 };
4078
4079 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4080         &dra7xx_l4_per3__usb_otg_ss4,
4081         NULL,
4082 };
4083
4084 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4085         NULL,
4086 };
4087
4088 static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4089         &dra7xx_l4_per3__rtcss,
4090         NULL,
4091 };
4092
4093 int __init dra7xx_hwmod_init(void)
4094 {
4095         int ret;
4096
4097         omap_hwmod_init();
4098         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4099
4100         if (!ret && soc_is_dra74x())
4101                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4102         else if (!ret && soc_is_dra72x())
4103                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4104         else if (!ret && soc_is_dra76x())
4105                 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4106
4107         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4108                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4109
4110         /* now for the IPs available only in dra74 and dra72 */
4111         if (!ret && !of_machine_is_compatible("ti,dra718") && !soc_is_dra76x())
4112                 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
4113
4114         return ret;
4115 }