arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "omap_hwmod_common_data.h"
  32 #include "cm1_7xx.h"
  33 #include "cm2_7xx.h"
  34 #include "prm7xx.h"
  35 #include "i2c.h"
  36 #include "mmc.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'l3' class
  53  * instance(s): l3_instr, l3_main_1, l3_main_2
  54  */
  55 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  56         .name   = "l3",
  57 };
  58
  59 /* l3_instr */
  60 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  61         .name           = "l3_instr",
  62         .class          = &dra7xx_l3_hwmod_class,
  63         .clkdm_name     = "l3instr_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  68                         .modulemode   = MODULEMODE_HWCTRL,
  69                 },
  70         },
  71 };
  72
  73 /* l3_main_1 */
  74 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  75         .name           = "l3_main_1",
  76         .class          = &dra7xx_l3_hwmod_class,
  77         .clkdm_name     = "l3main1_clkdm",
  78         .prcm = {
  79                 .omap4 = {
  80                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  81                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  82                 },
  83         },
  84 };
  85
  86 /* l3_main_2 */
  87 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  88         .name           = "l3_main_2",
  89         .class          = &dra7xx_l3_hwmod_class,
  90         .clkdm_name     = "l3instr_clkdm",
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
  94                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
  95                         .modulemode   = MODULEMODE_HWCTRL,
  96                 },
  97         },
  98 };
  99
 100 /*
 101  * 'l4' class
 102  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 103  */
 104 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 105         .name   = "l4",
 106 };
 107
 108 /* l4_cfg */
 109 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 110         .name           = "l4_cfg",
 111         .class          = &dra7xx_l4_hwmod_class,
 112         .clkdm_name     = "l4cfg_clkdm",
 113         .prcm = {
 114                 .omap4 = {
 115                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 116                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 117                 },
 118         },
 119 };
 120
 121 /* l4_per1 */
 122 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 123         .name           = "l4_per1",
 124         .class          = &dra7xx_l4_hwmod_class,
 125         .clkdm_name     = "l4per_clkdm",
 126         .prcm = {
 127                 .omap4 = {
 128                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 129                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 130                 },
 131         },
 132 };
 133
 134 /* l4_per2 */
 135 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 136         .name           = "l4_per2",
 137         .class          = &dra7xx_l4_hwmod_class,
 138         .clkdm_name     = "l4per2_clkdm",
 139         .prcm = {
 140                 .omap4 = {
 141                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 142                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 143                 },
 144         },
 145 };
 146
 147 /* l4_per3 */
 148 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 149         .name           = "l4_per3",
 150         .class          = &dra7xx_l4_hwmod_class,
 151         .clkdm_name     = "l4per3_clkdm",
 152         .prcm = {
 153                 .omap4 = {
 154                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 155                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 156                 },
 157         },
 158 };
 159
 160 /* l4_wkup */
 161 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 162         .name           = "l4_wkup",
 163         .class          = &dra7xx_l4_hwmod_class,
 164         .clkdm_name     = "wkupaon_clkdm",
 165         .prcm = {
 166                 .omap4 = {
 167                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 168                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 169                 },
 170         },
 171 };
 172
 173 /*
 174  * 'atl' class
 175  *
 176  */
 177
 178 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 179         .name   = "atl",
 180 };
 181
 182 /* atl */
 183 static struct omap_hwmod dra7xx_atl_hwmod = {
 184         .name           = "atl",
 185         .class          = &dra7xx_atl_hwmod_class,
 186         .clkdm_name     = "atl_clkdm",
 187         .main_clk       = "atl_gfclk_mux",
 188         .prcm = {
 189                 .omap4 = {
 190                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 191                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 192                         .modulemode   = MODULEMODE_SWCTRL,
 193                 },
 194         },
 195 };
 196
 197 /*
 198  * 'bb2d' class
 199  *
 200  */
 201
 202 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 203         .name   = "bb2d",
 204 };
 205
 206 /* bb2d */
 207 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 208         .name           = "bb2d",
 209         .class          = &dra7xx_bb2d_hwmod_class,
 210         .clkdm_name     = "dss_clkdm",
 211         .main_clk       = "dpll_core_h24x2_ck",
 212         .prcm = {
 213                 .omap4 = {
 214                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 215                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 216                         .modulemode   = MODULEMODE_SWCTRL,
 217                 },
 218         },
 219 };
 220
 221 /*
 222  * 'counter' class
 223  *
 224  */
 225
 226 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 227         .rev_offs       = 0x0000,
 228         .sysc_offs      = 0x0010,
 229         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 230         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 231                            SIDLE_SMART_WKUP),
 232         .sysc_fields    = &omap_hwmod_sysc_type1,
 233 };
 234
 235 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 236         .name   = "counter",
 237         .sysc   = &dra7xx_counter_sysc,
 238 };
 239
 240 /* counter_32k */
 241 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 242         .name           = "counter_32k",
 243         .class          = &dra7xx_counter_hwmod_class,
 244         .clkdm_name     = "wkupaon_clkdm",
 245         .flags          = HWMOD_SWSUP_SIDLE,
 246         .main_clk       = "wkupaon_iclk_mux",
 247         .prcm = {
 248                 .omap4 = {
 249                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 250                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 251                 },
 252         },
 253 };
 254
 255 /*
 256  * 'ctrl_module' class
 257  *
 258  */
 259
 260 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 261         .name   = "ctrl_module",
 262 };
 263
 264 /* ctrl_module_wkup */
 265 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 266         .name           = "ctrl_module_wkup",
 267         .class          = &dra7xx_ctrl_module_hwmod_class,
 268         .clkdm_name     = "wkupaon_clkdm",
 269         .prcm = {
 270                 .omap4 = {
 271                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'gmac' class
 278  * cpsw/gmac sub system
 279  */
 280 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 281         .rev_offs       = 0x0,
 282         .sysc_offs      = 0x8,
 283         .syss_offs      = 0x4,
 284         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 285                            SYSS_HAS_RESET_STATUS),
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 287                            MSTANDBY_NO),
 288         .sysc_fields    = &omap_hwmod_sysc_type3,
 289 };
 290
 291 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 292         .name           = "gmac",
 293         .sysc           = &dra7xx_gmac_sysc,
 294 };
 295
 296 static struct omap_hwmod dra7xx_gmac_hwmod = {
 297         .name           = "gmac",
 298         .class          = &dra7xx_gmac_hwmod_class,
 299         .clkdm_name     = "gmac_clkdm",
 300         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 301         .main_clk       = "dpll_gmac_ck",
 302         .mpu_rt_idx     = 1,
 303         .prcm           = {
 304                 .omap4  = {
 305                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 306                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 307                         .modulemode     = MODULEMODE_SWCTRL,
 308                 },
 309         },
 310 };
 311
 312 /*
 313  * 'mdio' class
 314  */
 315 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 316         .name           = "davinci_mdio",
 317 };
 318
 319 static struct omap_hwmod dra7xx_mdio_hwmod = {
 320         .name           = "davinci_mdio",
 321         .class          = &dra7xx_mdio_hwmod_class,
 322         .clkdm_name     = "gmac_clkdm",
 323         .main_clk       = "dpll_gmac_ck",
 324 };
 325
 326 /*
 327  * 'dcan' class
 328  *
 329  */
 330
 331 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 332         .name   = "dcan",
 333 };
 334
 335 /* dcan1 */
 336 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 337         .name           = "dcan1",
 338         .class          = &dra7xx_dcan_hwmod_class,
 339         .clkdm_name     = "wkupaon_clkdm",
 340         .main_clk       = "dcan1_sys_clk_mux",
 341         .prcm = {
 342                 .omap4 = {
 343                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 344                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 345                         .modulemode   = MODULEMODE_SWCTRL,
 346                 },
 347         },
 348 };
 349
 350 /* dcan2 */
 351 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 352         .name           = "dcan2",
 353         .class          = &dra7xx_dcan_hwmod_class,
 354         .clkdm_name     = "l4per2_clkdm",
 355         .main_clk       = "sys_clkin1",
 356         .prcm = {
 357                 .omap4 = {
 358                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 359                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 360                         .modulemode   = MODULEMODE_SWCTRL,
 361                 },
 362         },
 363 };
 364
 365 /*
 366  * 'dma' class
 367  *
 368  */
 369
 370 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 371         .rev_offs       = 0x0000,
 372         .sysc_offs      = 0x002c,
 373         .syss_offs      = 0x0028,
 374         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 375                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 376                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 377                            SYSS_HAS_RESET_STATUS),
 378         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 379                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 380                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 381         .sysc_fields    = &omap_hwmod_sysc_type1,
 382 };
 383
 384 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 385         .name   = "dma",
 386         .sysc   = &dra7xx_dma_sysc,
 387 };
 388
 389 /* dma dev_attr */
 390 static struct omap_dma_dev_attr dma_dev_attr = {
 391         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 392                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 393         .lch_count      = 32,
 394 };
 395
 396 /* dma_system */
 397 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 398         .name           = "dma_system",
 399         .class          = &dra7xx_dma_hwmod_class,
 400         .clkdm_name     = "dma_clkdm",
 401         .main_clk       = "l3_iclk_div",
 402         .prcm = {
 403                 .omap4 = {
 404                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 405                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 406                 },
 407         },
 408         .dev_attr       = &dma_dev_attr,
 409 };
 410
 411 /*
 412  * 'dss' class
 413  *
 414  */
 415
 416 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 417         .rev_offs       = 0x0000,
 418         .syss_offs      = 0x0014,
 419         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 420 };
 421
 422 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 423         .name   = "dss",
 424         .sysc   = &dra7xx_dss_sysc,
 425         .reset  = omap_dss_reset,
 426 };
 427
 428 /* dss */
 429 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 430         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 431         { .dma_req = -1 }
 432 };
 433
 434 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 435         { .role = "dss_clk", .clk = "dss_dss_clk" },
 436         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 437         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 438         { .role = "video2_clk", .clk = "dss_video2_clk" },
 439         { .role = "video1_clk", .clk = "dss_video1_clk" },
 440         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 441 };
 442
 443 static struct omap_hwmod dra7xx_dss_hwmod = {
 444         .name           = "dss_core",
 445         .class          = &dra7xx_dss_hwmod_class,
 446         .clkdm_name     = "dss_clkdm",
 447         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 448         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 449         .main_clk       = "dss_dss_clk",
 450         .prcm = {
 451                 .omap4 = {
 452                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 453                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 454                         .modulemode   = MODULEMODE_SWCTRL,
 455                 },
 456         },
 457         .opt_clks       = dss_opt_clks,
 458         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 459 };
 460
 461 /*
 462  * 'dispc' class
 463  * display controller
 464  */
 465
 466 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 467         .rev_offs       = 0x0000,
 468         .sysc_offs      = 0x0010,
 469         .syss_offs      = 0x0014,
 470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 471                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 472                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 473                            SYSS_HAS_RESET_STATUS),
 474         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 475                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 476         .sysc_fields    = &omap_hwmod_sysc_type1,
 477 };
 478
 479 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 480         .name   = "dispc",
 481         .sysc   = &dra7xx_dispc_sysc,
 482 };
 483
 484 /* dss_dispc */
 485 /* dss_dispc dev_attr */
 486 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 487         .has_framedonetv_irq    = 1,
 488         .manager_count          = 4,
 489 };
 490
 491 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 492         .name           = "dss_dispc",
 493         .class          = &dra7xx_dispc_hwmod_class,
 494         .clkdm_name     = "dss_clkdm",
 495         .main_clk       = "dss_dss_clk",
 496         .prcm = {
 497                 .omap4 = {
 498                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 500                 },
 501         },
 502         .dev_attr       = &dss_dispc_dev_attr,
 503 };
 504
 505 /*
 506  * 'hdmi' class
 507  * hdmi controller
 508  */
 509
 510 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 511         .rev_offs       = 0x0000,
 512         .sysc_offs      = 0x0010,
 513         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 514                            SYSC_HAS_SOFTRESET),
 515         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 516                            SIDLE_SMART_WKUP),
 517         .sysc_fields    = &omap_hwmod_sysc_type2,
 518 };
 519
 520 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 521         .name   = "hdmi",
 522         .sysc   = &dra7xx_hdmi_sysc,
 523 };
 524
 525 /* dss_hdmi */
 526
 527 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 528         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 529 };
 530
 531 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 532         .name           = "dss_hdmi",
 533         .class          = &dra7xx_hdmi_hwmod_class,
 534         .clkdm_name     = "dss_clkdm",
 535         .main_clk       = "dss_48mhz_clk",
 536         .prcm = {
 537                 .omap4 = {
 538                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 539                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 540                 },
 541         },
 542         .opt_clks       = dss_hdmi_opt_clks,
 543         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 544 };
 545
 546 /*
 547  * 'elm' class
 548  *
 549  */
 550
 551 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 556                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 557                            SYSS_HAS_RESET_STATUS),
 558         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 559                            SIDLE_SMART_WKUP),
 560         .sysc_fields    = &omap_hwmod_sysc_type1,
 561 };
 562
 563 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 564         .name   = "elm",
 565         .sysc   = &dra7xx_elm_sysc,
 566 };
 567
 568 /* elm */
 569
 570 static struct omap_hwmod dra7xx_elm_hwmod = {
 571         .name           = "elm",
 572         .class          = &dra7xx_elm_hwmod_class,
 573         .clkdm_name     = "l4per_clkdm",
 574         .main_clk       = "l3_iclk_div",
 575         .prcm = {
 576                 .omap4 = {
 577                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 578                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 579                 },
 580         },
 581 };
 582
 583 /*
 584  * 'gpio' class
 585  *
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .syss_offs      = 0x0114,
 592         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 593                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 594                            SYSS_HAS_RESET_STATUS),
 595         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 596                            SIDLE_SMART_WKUP),
 597         .sysc_fields    = &omap_hwmod_sysc_type1,
 598 };
 599
 600 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 601         .name   = "gpio",
 602         .sysc   = &dra7xx_gpio_sysc,
 603         .rev    = 2,
 604 };
 605
 606 /* gpio dev_attr */
 607 static struct omap_gpio_dev_attr gpio_dev_attr = {
 608         .bank_width     = 32,
 609         .dbck_flag      = true,
 610 };
 611
 612 /* gpio1 */
 613 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 614         { .role = "dbclk", .clk = "gpio1_dbclk" },
 615 };
 616
 617 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 618         .name           = "gpio1",
 619         .class          = &dra7xx_gpio_hwmod_class,
 620         .clkdm_name     = "wkupaon_clkdm",
 621         .main_clk       = "wkupaon_iclk_mux",
 622         .prcm = {
 623                 .omap4 = {
 624                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 625                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 626                         .modulemode   = MODULEMODE_HWCTRL,
 627                 },
 628         },
 629         .opt_clks       = gpio1_opt_clks,
 630         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 631         .dev_attr       = &gpio_dev_attr,
 632 };
 633
 634 /* gpio2 */
 635 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 636         { .role = "dbclk", .clk = "gpio2_dbclk" },
 637 };
 638
 639 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 640         .name           = "gpio2",
 641         .class          = &dra7xx_gpio_hwmod_class,
 642         .clkdm_name     = "l4per_clkdm",
 643         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 644         .main_clk       = "l3_iclk_div",
 645         .prcm = {
 646                 .omap4 = {
 647                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 648                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 649                         .modulemode   = MODULEMODE_HWCTRL,
 650                 },
 651         },
 652         .opt_clks       = gpio2_opt_clks,
 653         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 654         .dev_attr       = &gpio_dev_attr,
 655 };
 656
 657 /* gpio3 */
 658 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 659         { .role = "dbclk", .clk = "gpio3_dbclk" },
 660 };
 661
 662 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 663         .name           = "gpio3",
 664         .class          = &dra7xx_gpio_hwmod_class,
 665         .clkdm_name     = "l4per_clkdm",
 666         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 667         .main_clk       = "l3_iclk_div",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 671                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 672                         .modulemode   = MODULEMODE_HWCTRL,
 673                 },
 674         },
 675         .opt_clks       = gpio3_opt_clks,
 676         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 677         .dev_attr       = &gpio_dev_attr,
 678 };
 679
 680 /* gpio4 */
 681 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 682         { .role = "dbclk", .clk = "gpio4_dbclk" },
 683 };
 684
 685 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 686         .name           = "gpio4",
 687         .class          = &dra7xx_gpio_hwmod_class,
 688         .clkdm_name     = "l4per_clkdm",
 689         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 690         .main_clk       = "l3_iclk_div",
 691         .prcm = {
 692                 .omap4 = {
 693                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 694                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 695                         .modulemode   = MODULEMODE_HWCTRL,
 696                 },
 697         },
 698         .opt_clks       = gpio4_opt_clks,
 699         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 700         .dev_attr       = &gpio_dev_attr,
 701 };
 702
 703 /* gpio5 */
 704 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 705         { .role = "dbclk", .clk = "gpio5_dbclk" },
 706 };
 707
 708 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 709         .name           = "gpio5",
 710         .class          = &dra7xx_gpio_hwmod_class,
 711         .clkdm_name     = "l4per_clkdm",
 712         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 713         .main_clk       = "l3_iclk_div",
 714         .prcm = {
 715                 .omap4 = {
 716                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 717                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 718                         .modulemode   = MODULEMODE_HWCTRL,
 719                 },
 720         },
 721         .opt_clks       = gpio5_opt_clks,
 722         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 723         .dev_attr       = &gpio_dev_attr,
 724 };
 725
 726 /* gpio6 */
 727 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 728         { .role = "dbclk", .clk = "gpio6_dbclk" },
 729 };
 730
 731 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 732         .name           = "gpio6",
 733         .class          = &dra7xx_gpio_hwmod_class,
 734         .clkdm_name     = "l4per_clkdm",
 735         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 736         .main_clk       = "l3_iclk_div",
 737         .prcm = {
 738                 .omap4 = {
 739                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 740                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 741                         .modulemode   = MODULEMODE_HWCTRL,
 742                 },
 743         },
 744         .opt_clks       = gpio6_opt_clks,
 745         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 746         .dev_attr       = &gpio_dev_attr,
 747 };
 748
 749 /* gpio7 */
 750 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 751         { .role = "dbclk", .clk = "gpio7_dbclk" },
 752 };
 753
 754 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 755         .name           = "gpio7",
 756         .class          = &dra7xx_gpio_hwmod_class,
 757         .clkdm_name     = "l4per_clkdm",
 758         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 759         .main_clk       = "l3_iclk_div",
 760         .prcm = {
 761                 .omap4 = {
 762                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 763                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 764                         .modulemode   = MODULEMODE_HWCTRL,
 765                 },
 766         },
 767         .opt_clks       = gpio7_opt_clks,
 768         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 769         .dev_attr       = &gpio_dev_attr,
 770 };
 771
 772 /* gpio8 */
 773 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 774         { .role = "dbclk", .clk = "gpio8_dbclk" },
 775 };
 776
 777 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 778         .name           = "gpio8",
 779         .class          = &dra7xx_gpio_hwmod_class,
 780         .clkdm_name     = "l4per_clkdm",
 781         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 782         .main_clk       = "l3_iclk_div",
 783         .prcm = {
 784                 .omap4 = {
 785                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 786                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 787                         .modulemode   = MODULEMODE_HWCTRL,
 788                 },
 789         },
 790         .opt_clks       = gpio8_opt_clks,
 791         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 792         .dev_attr       = &gpio_dev_attr,
 793 };
 794
 795 /*
 796  * 'gpmc' class
 797  *
 798  */
 799
 800 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 801         .rev_offs       = 0x0000,
 802         .sysc_offs      = 0x0010,
 803         .syss_offs      = 0x0014,
 804         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 805                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 807                            SIDLE_SMART_WKUP),
 808         .sysc_fields    = &omap_hwmod_sysc_type1,
 809 };
 810
 811 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 812         .name   = "gpmc",
 813         .sysc   = &dra7xx_gpmc_sysc,
 814 };
 815
 816 /* gpmc */
 817
 818 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 819         .name           = "gpmc",
 820         .class          = &dra7xx_gpmc_hwmod_class,
 821         .clkdm_name     = "l3main1_clkdm",
 822         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 823         .main_clk       = "l3_iclk_div",
 824         .prcm = {
 825                 .omap4 = {
 826                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 827                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 828                         .modulemode   = MODULEMODE_HWCTRL,
 829                 },
 830         },
 831 };
 832
 833 /*
 834  * 'hdq1w' class
 835  *
 836  */
 837
 838 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 839         .rev_offs       = 0x0000,
 840         .sysc_offs      = 0x0014,
 841         .syss_offs      = 0x0018,
 842         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 843                            SYSS_HAS_RESET_STATUS),
 844         .sysc_fields    = &omap_hwmod_sysc_type1,
 845 };
 846
 847 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 848         .name   = "hdq1w",
 849         .sysc   = &dra7xx_hdq1w_sysc,
 850 };
 851
 852 /* hdq1w */
 853
 854 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 855         .name           = "hdq1w",
 856         .class          = &dra7xx_hdq1w_hwmod_class,
 857         .clkdm_name     = "l4per_clkdm",
 858         .flags          = HWMOD_INIT_NO_RESET,
 859         .main_clk       = "func_12m_fclk",
 860         .prcm = {
 861                 .omap4 = {
 862                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
 863                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
 864                         .modulemode   = MODULEMODE_SWCTRL,
 865                 },
 866         },
 867 };
 868
 869 /*
 870  * 'i2c' class
 871  *
 872  */
 873
 874 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
 875         .sysc_offs      = 0x0010,
 876         .syss_offs      = 0x0090,
 877         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 878                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 879                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 880         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 881                            SIDLE_SMART_WKUP),
 882         .clockact       = CLOCKACT_TEST_ICLK,
 883         .sysc_fields    = &omap_hwmod_sysc_type1,
 884 };
 885
 886 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
 887         .name   = "i2c",
 888         .sysc   = &dra7xx_i2c_sysc,
 889         .reset  = &omap_i2c_reset,
 890         .rev    = OMAP_I2C_IP_VERSION_2,
 891 };
 892
 893 /* i2c dev_attr */
 894 static struct omap_i2c_dev_attr i2c_dev_attr = {
 895         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 896 };
 897
 898 /* i2c1 */
 899 static struct omap_hwmod dra7xx_i2c1_hwmod = {
 900         .name           = "i2c1",
 901         .class          = &dra7xx_i2c_hwmod_class,
 902         .clkdm_name     = "l4per_clkdm",
 903         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 904         .main_clk       = "func_96m_fclk",
 905         .prcm = {
 906                 .omap4 = {
 907                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 908                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 909                         .modulemode   = MODULEMODE_SWCTRL,
 910                 },
 911         },
 912         .dev_attr       = &i2c_dev_attr,
 913 };
 914
 915 /* i2c2 */
 916 static struct omap_hwmod dra7xx_i2c2_hwmod = {
 917         .name           = "i2c2",
 918         .class          = &dra7xx_i2c_hwmod_class,
 919         .clkdm_name     = "l4per_clkdm",
 920         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 921         .main_clk       = "func_96m_fclk",
 922         .prcm = {
 923                 .omap4 = {
 924                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 925                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 926                         .modulemode   = MODULEMODE_SWCTRL,
 927                 },
 928         },
 929         .dev_attr       = &i2c_dev_attr,
 930 };
 931
 932 /* i2c3 */
 933 static struct omap_hwmod dra7xx_i2c3_hwmod = {
 934         .name           = "i2c3",
 935         .class          = &dra7xx_i2c_hwmod_class,
 936         .clkdm_name     = "l4per_clkdm",
 937         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 938         .main_clk       = "func_96m_fclk",
 939         .prcm = {
 940                 .omap4 = {
 941                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 942                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 943                         .modulemode   = MODULEMODE_SWCTRL,
 944                 },
 945         },
 946         .dev_attr       = &i2c_dev_attr,
 947 };
 948
 949 /* i2c4 */
 950 static struct omap_hwmod dra7xx_i2c4_hwmod = {
 951         .name           = "i2c4",
 952         .class          = &dra7xx_i2c_hwmod_class,
 953         .clkdm_name     = "l4per_clkdm",
 954         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 955         .main_clk       = "func_96m_fclk",
 956         .prcm = {
 957                 .omap4 = {
 958                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 959                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 960                         .modulemode   = MODULEMODE_SWCTRL,
 961                 },
 962         },
 963         .dev_attr       = &i2c_dev_attr,
 964 };
 965
 966 /* i2c5 */
 967 static struct omap_hwmod dra7xx_i2c5_hwmod = {
 968         .name           = "i2c5",
 969         .class          = &dra7xx_i2c_hwmod_class,
 970         .clkdm_name     = "ipu_clkdm",
 971         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 972         .main_clk       = "func_96m_fclk",
 973         .prcm = {
 974                 .omap4 = {
 975                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
 976                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
 977                         .modulemode   = MODULEMODE_SWCTRL,
 978                 },
 979         },
 980         .dev_attr       = &i2c_dev_attr,
 981 };
 982
 983 /*
 984  * 'mailbox' class
 985  *
 986  */
 987
 988 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
 989         .rev_offs       = 0x0000,
 990         .sysc_offs      = 0x0010,
 991         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 992                            SYSC_HAS_SOFTRESET),
 993         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 994         .sysc_fields    = &omap_hwmod_sysc_type2,
 995 };
 996
 997 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
 998         .name   = "mailbox",
 999         .sysc   = &dra7xx_mailbox_sysc,
1000 };
1001
1002 /* mailbox1 */
1003 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1004         .name           = "mailbox1",
1005         .class          = &dra7xx_mailbox_hwmod_class,
1006         .clkdm_name     = "l4cfg_clkdm",
1007         .prcm = {
1008                 .omap4 = {
1009                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1010                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1011                 },
1012         },
1013 };
1014
1015 /* mailbox2 */
1016 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1017         .name           = "mailbox2",
1018         .class          = &dra7xx_mailbox_hwmod_class,
1019         .clkdm_name     = "l4cfg_clkdm",
1020         .prcm = {
1021                 .omap4 = {
1022                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1023                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1024                 },
1025         },
1026 };
1027
1028 /* mailbox3 */
1029 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1030         .name           = "mailbox3",
1031         .class          = &dra7xx_mailbox_hwmod_class,
1032         .clkdm_name     = "l4cfg_clkdm",
1033         .prcm = {
1034                 .omap4 = {
1035                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1036                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1037                 },
1038         },
1039 };
1040
1041 /* mailbox4 */
1042 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1043         .name           = "mailbox4",
1044         .class          = &dra7xx_mailbox_hwmod_class,
1045         .clkdm_name     = "l4cfg_clkdm",
1046         .prcm = {
1047                 .omap4 = {
1048                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1049                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1050                 },
1051         },
1052 };
1053
1054 /* mailbox5 */
1055 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1056         .name           = "mailbox5",
1057         .class          = &dra7xx_mailbox_hwmod_class,
1058         .clkdm_name     = "l4cfg_clkdm",
1059         .prcm = {
1060                 .omap4 = {
1061                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1062                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1063                 },
1064         },
1065 };
1066
1067 /* mailbox6 */
1068 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1069         .name           = "mailbox6",
1070         .class          = &dra7xx_mailbox_hwmod_class,
1071         .clkdm_name     = "l4cfg_clkdm",
1072         .prcm = {
1073                 .omap4 = {
1074                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1075                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1076                 },
1077         },
1078 };
1079
1080 /* mailbox7 */
1081 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1082         .name           = "mailbox7",
1083         .class          = &dra7xx_mailbox_hwmod_class,
1084         .clkdm_name     = "l4cfg_clkdm",
1085         .prcm = {
1086                 .omap4 = {
1087                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1088                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1089                 },
1090         },
1091 };
1092
1093 /* mailbox8 */
1094 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1095         .name           = "mailbox8",
1096         .class          = &dra7xx_mailbox_hwmod_class,
1097         .clkdm_name     = "l4cfg_clkdm",
1098         .prcm = {
1099                 .omap4 = {
1100                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1101                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1102                 },
1103         },
1104 };
1105
1106 /* mailbox9 */
1107 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1108         .name           = "mailbox9",
1109         .class          = &dra7xx_mailbox_hwmod_class,
1110         .clkdm_name     = "l4cfg_clkdm",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1114                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1115                 },
1116         },
1117 };
1118
1119 /* mailbox10 */
1120 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1121         .name           = "mailbox10",
1122         .class          = &dra7xx_mailbox_hwmod_class,
1123         .clkdm_name     = "l4cfg_clkdm",
1124         .prcm = {
1125                 .omap4 = {
1126                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1127                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1128                 },
1129         },
1130 };
1131
1132 /* mailbox11 */
1133 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1134         .name           = "mailbox11",
1135         .class          = &dra7xx_mailbox_hwmod_class,
1136         .clkdm_name     = "l4cfg_clkdm",
1137         .prcm = {
1138                 .omap4 = {
1139                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1140                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1141                 },
1142         },
1143 };
1144
1145 /* mailbox12 */
1146 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1147         .name           = "mailbox12",
1148         .class          = &dra7xx_mailbox_hwmod_class,
1149         .clkdm_name     = "l4cfg_clkdm",
1150         .prcm = {
1151                 .omap4 = {
1152                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1153                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1154                 },
1155         },
1156 };
1157
1158 /* mailbox13 */
1159 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1160         .name           = "mailbox13",
1161         .class          = &dra7xx_mailbox_hwmod_class,
1162         .clkdm_name     = "l4cfg_clkdm",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1166                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1167                 },
1168         },
1169 };
1170
1171 /*
1172  * 'mcspi' class
1173  *
1174  */
1175
1176 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1177         .rev_offs       = 0x0000,
1178         .sysc_offs      = 0x0010,
1179         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1180                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1181         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1182                            SIDLE_SMART_WKUP),
1183         .sysc_fields    = &omap_hwmod_sysc_type2,
1184 };
1185
1186 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1187         .name   = "mcspi",
1188         .sysc   = &dra7xx_mcspi_sysc,
1189         .rev    = OMAP4_MCSPI_REV,
1190 };
1191
1192 /* mcspi1 */
1193 /* mcspi1 dev_attr */
1194 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1195         .num_chipselect = 4,
1196 };
1197
1198 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1199         .name           = "mcspi1",
1200         .class          = &dra7xx_mcspi_hwmod_class,
1201         .clkdm_name     = "l4per_clkdm",
1202         .main_clk       = "func_48m_fclk",
1203         .prcm = {
1204                 .omap4 = {
1205                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1206                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1207                         .modulemode   = MODULEMODE_SWCTRL,
1208                 },
1209         },
1210         .dev_attr       = &mcspi1_dev_attr,
1211 };
1212
1213 /* mcspi2 */
1214 /* mcspi2 dev_attr */
1215 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1216         .num_chipselect = 2,
1217 };
1218
1219 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1220         .name           = "mcspi2",
1221         .class          = &dra7xx_mcspi_hwmod_class,
1222         .clkdm_name     = "l4per_clkdm",
1223         .main_clk       = "func_48m_fclk",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1227                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_SWCTRL,
1229                 },
1230         },
1231         .dev_attr       = &mcspi2_dev_attr,
1232 };
1233
1234 /* mcspi3 */
1235 /* mcspi3 dev_attr */
1236 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1237         .num_chipselect = 2,
1238 };
1239
1240 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1241         .name           = "mcspi3",
1242         .class          = &dra7xx_mcspi_hwmod_class,
1243         .clkdm_name     = "l4per_clkdm",
1244         .main_clk       = "func_48m_fclk",
1245         .prcm = {
1246                 .omap4 = {
1247                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1248                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1249                         .modulemode   = MODULEMODE_SWCTRL,
1250                 },
1251         },
1252         .dev_attr       = &mcspi3_dev_attr,
1253 };
1254
1255 /* mcspi4 */
1256 /* mcspi4 dev_attr */
1257 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1258         .num_chipselect = 1,
1259 };
1260
1261 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1262         .name           = "mcspi4",
1263         .class          = &dra7xx_mcspi_hwmod_class,
1264         .clkdm_name     = "l4per_clkdm",
1265         .main_clk       = "func_48m_fclk",
1266         .prcm = {
1267                 .omap4 = {
1268                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1269                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1270                         .modulemode   = MODULEMODE_SWCTRL,
1271                 },
1272         },
1273         .dev_attr       = &mcspi4_dev_attr,
1274 };
1275
1276 /*
1277  * 'mmc' class
1278  *
1279  */
1280
1281 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1282         .rev_offs       = 0x0000,
1283         .sysc_offs      = 0x0010,
1284         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1285                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1286                            SYSC_HAS_SOFTRESET),
1287         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1288                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1289                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1290         .sysc_fields    = &omap_hwmod_sysc_type2,
1291 };
1292
1293 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1294         .name   = "mmc",
1295         .sysc   = &dra7xx_mmc_sysc,
1296 };
1297
1298 /* mmc1 */
1299 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1300         { .role = "clk32k", .clk = "mmc1_clk32k" },
1301 };
1302
1303 /* mmc1 dev_attr */
1304 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1305         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1306 };
1307
1308 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1309         .name           = "mmc1",
1310         .class          = &dra7xx_mmc_hwmod_class,
1311         .clkdm_name     = "l3init_clkdm",
1312         .main_clk       = "mmc1_fclk_div",
1313         .prcm = {
1314                 .omap4 = {
1315                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1316                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1317                         .modulemode   = MODULEMODE_SWCTRL,
1318                 },
1319         },
1320         .opt_clks       = mmc1_opt_clks,
1321         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1322         .dev_attr       = &mmc1_dev_attr,
1323 };
1324
1325 /* mmc2 */
1326 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1327         { .role = "clk32k", .clk = "mmc2_clk32k" },
1328 };
1329
1330 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1331         .name           = "mmc2",
1332         .class          = &dra7xx_mmc_hwmod_class,
1333         .clkdm_name     = "l3init_clkdm",
1334         .main_clk       = "mmc2_fclk_div",
1335         .prcm = {
1336                 .omap4 = {
1337                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1338                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1339                         .modulemode   = MODULEMODE_SWCTRL,
1340                 },
1341         },
1342         .opt_clks       = mmc2_opt_clks,
1343         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1344 };
1345
1346 /* mmc3 */
1347 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1348         { .role = "clk32k", .clk = "mmc3_clk32k" },
1349 };
1350
1351 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1352         .name           = "mmc3",
1353         .class          = &dra7xx_mmc_hwmod_class,
1354         .clkdm_name     = "l4per_clkdm",
1355         .main_clk       = "mmc3_gfclk_div",
1356         .prcm = {
1357                 .omap4 = {
1358                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1359                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1360                         .modulemode   = MODULEMODE_SWCTRL,
1361                 },
1362         },
1363         .opt_clks       = mmc3_opt_clks,
1364         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1365 };
1366
1367 /* mmc4 */
1368 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1369         { .role = "clk32k", .clk = "mmc4_clk32k" },
1370 };
1371
1372 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1373         .name           = "mmc4",
1374         .class          = &dra7xx_mmc_hwmod_class,
1375         .clkdm_name     = "l4per_clkdm",
1376         .main_clk       = "mmc4_gfclk_div",
1377         .prcm = {
1378                 .omap4 = {
1379                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1380                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1381                         .modulemode   = MODULEMODE_SWCTRL,
1382                 },
1383         },
1384         .opt_clks       = mmc4_opt_clks,
1385         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1386 };
1387
1388 /*
1389  * 'mpu' class
1390  *
1391  */
1392
1393 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1394         .name   = "mpu",
1395 };
1396
1397 /* mpu */
1398 static struct omap_hwmod dra7xx_mpu_hwmod = {
1399         .name           = "mpu",
1400         .class          = &dra7xx_mpu_hwmod_class,
1401         .clkdm_name     = "mpu_clkdm",
1402         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1403         .main_clk       = "dpll_mpu_m2_ck",
1404         .prcm = {
1405                 .omap4 = {
1406                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1407                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1408                 },
1409         },
1410 };
1411
1412 /*
1413  * 'ocp2scp' class
1414  *
1415  */
1416
1417 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1418         .rev_offs       = 0x0000,
1419         .sysc_offs      = 0x0010,
1420         .syss_offs      = 0x0014,
1421         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1422                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1423         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1424                            SIDLE_SMART_WKUP),
1425         .sysc_fields    = &omap_hwmod_sysc_type1,
1426 };
1427
1428 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1429         .name   = "ocp2scp",
1430         .sysc   = &dra7xx_ocp2scp_sysc,
1431 };
1432
1433 /* ocp2scp1 */
1434 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1435         .name           = "ocp2scp1",
1436         .class          = &dra7xx_ocp2scp_hwmod_class,
1437         .clkdm_name     = "l3init_clkdm",
1438         .main_clk       = "l4_root_clk_div",
1439         .prcm = {
1440                 .omap4 = {
1441                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1442                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1443                         .modulemode   = MODULEMODE_HWCTRL,
1444                 },
1445         },
1446 };
1447
1448 /* ocp2scp3 */
1449 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1450         .name           = "ocp2scp3",
1451         .class          = &dra7xx_ocp2scp_hwmod_class,
1452         .clkdm_name     = "l3init_clkdm",
1453         .main_clk       = "l4_root_clk_div",
1454         .prcm = {
1455                 .omap4 = {
1456                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1457                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1458                         .modulemode   = MODULEMODE_HWCTRL,
1459                 },
1460         },
1461 };
1462
1463 /*
1464  * 'PCIE' class
1465  *
1466  */
1467
1468 static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1469         .name   = "pcie",
1470 };
1471
1472 /* pcie1 */
1473 static struct omap_hwmod dra7xx_pcie1_hwmod = {
1474         .name           = "pcie1",
1475         .class          = &dra7xx_pcie_hwmod_class,
1476         .clkdm_name     = "pcie_clkdm",
1477         .main_clk       = "l4_root_clk_div",
1478         .prcm = {
1479                 .omap4 = {
1480                         .clkctrl_offs   = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1481                         .modulemode     = MODULEMODE_SWCTRL,
1482                 },
1483         },
1484 };
1485
1486 /* pcie2 */
1487 static struct omap_hwmod dra7xx_pcie2_hwmod = {
1488         .name           = "pcie2",
1489         .class          = &dra7xx_pcie_hwmod_class,
1490         .clkdm_name     = "pcie_clkdm",
1491         .main_clk       = "l4_root_clk_div",
1492         .prcm = {
1493                 .omap4 = {
1494                         .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1495                         .modulemode   = MODULEMODE_SWCTRL,
1496                 },
1497         },
1498 };
1499
1500 /*
1501  * 'PCIE PHY' class
1502  *
1503  */
1504
1505 static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1506         .name   = "pcie-phy",
1507 };
1508
1509 /* pcie1 phy */
1510 static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1511         .name           = "pcie1-phy",
1512         .class          = &dra7xx_pcie_phy_hwmod_class,
1513         .clkdm_name     = "l3init_clkdm",
1514         .main_clk       = "l4_root_clk_div",
1515         .prcm = {
1516                 .omap4 = {
1517                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1518                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1519                         .modulemode   = MODULEMODE_SWCTRL,
1520                 },
1521         },
1522 };
1523
1524 /* pcie2 phy */
1525 static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1526         .name           = "pcie2-phy",
1527         .class          = &dra7xx_pcie_phy_hwmod_class,
1528         .clkdm_name     = "l3init_clkdm",
1529         .main_clk       = "l4_root_clk_div",
1530         .prcm = {
1531                 .omap4 = {
1532                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1533                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1534                         .modulemode   = MODULEMODE_SWCTRL,
1535                 },
1536         },
1537 };
1538
1539 /*
1540  * 'qspi' class
1541  *
1542  */
1543
1544 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1545         .sysc_offs      = 0x0010,
1546         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1548                            SIDLE_SMART_WKUP),
1549         .sysc_fields    = &omap_hwmod_sysc_type2,
1550 };
1551
1552 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1553         .name   = "qspi",
1554         .sysc   = &dra7xx_qspi_sysc,
1555 };
1556
1557 /* qspi */
1558 static struct omap_hwmod dra7xx_qspi_hwmod = {
1559         .name           = "qspi",
1560         .class          = &dra7xx_qspi_hwmod_class,
1561         .clkdm_name     = "l4per2_clkdm",
1562         .main_clk       = "qspi_gfclk_div",
1563         .prcm = {
1564                 .omap4 = {
1565                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1566                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1567                         .modulemode   = MODULEMODE_SWCTRL,
1568                 },
1569         },
1570 };
1571
1572 /*
1573  * 'rtcss' class
1574  *
1575  */
1576 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1577         .sysc_offs      = 0x0078,
1578         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1579         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1580                            SIDLE_SMART_WKUP),
1581         .sysc_fields    = &omap_hwmod_sysc_type3,
1582 };
1583
1584 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1585         .name   = "rtcss",
1586         .sysc   = &dra7xx_rtcss_sysc,
1587 };
1588
1589 /* rtcss */
1590 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1591         .name           = "rtcss",
1592         .class          = &dra7xx_rtcss_hwmod_class,
1593         .clkdm_name     = "rtc_clkdm",
1594         .main_clk       = "sys_32k_ck",
1595         .prcm = {
1596                 .omap4 = {
1597                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1598                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1599                         .modulemode   = MODULEMODE_SWCTRL,
1600                 },
1601         },
1602 };
1603
1604 /*
1605  * 'sata' class
1606  *
1607  */
1608
1609 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1610         .sysc_offs      = 0x0000,
1611         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1613                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1614                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1615         .sysc_fields    = &omap_hwmod_sysc_type2,
1616 };
1617
1618 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1619         .name   = "sata",
1620         .sysc   = &dra7xx_sata_sysc,
1621 };
1622
1623 /* sata */
1624
1625 static struct omap_hwmod dra7xx_sata_hwmod = {
1626         .name           = "sata",
1627         .class          = &dra7xx_sata_hwmod_class,
1628         .clkdm_name     = "l3init_clkdm",
1629         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1630         .main_clk       = "func_48m_fclk",
1631         .mpu_rt_idx     = 1,
1632         .prcm = {
1633                 .omap4 = {
1634                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1635                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1636                         .modulemode   = MODULEMODE_SWCTRL,
1637                 },
1638         },
1639 };
1640
1641 /*
1642  * 'smartreflex' class
1643  *
1644  */
1645
1646 /* The IP is not compliant to type1 / type2 scheme */
1647 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1648         .sidle_shift    = 24,
1649         .enwkup_shift   = 26,
1650 };
1651
1652 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1653         .sysc_offs      = 0x0038,
1654         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1655         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1656                            SIDLE_SMART_WKUP),
1657         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1658 };
1659
1660 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1661         .name   = "smartreflex",
1662         .sysc   = &dra7xx_smartreflex_sysc,
1663         .rev    = 2,
1664 };
1665
1666 /* smartreflex_core */
1667 /* smartreflex_core dev_attr */
1668 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1669         .sensor_voltdm_name     = "core",
1670 };
1671
1672 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1673         .name           = "smartreflex_core",
1674         .class          = &dra7xx_smartreflex_hwmod_class,
1675         .clkdm_name     = "coreaon_clkdm",
1676         .main_clk       = "wkupaon_iclk_mux",
1677         .prcm = {
1678                 .omap4 = {
1679                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1680                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1681                         .modulemode   = MODULEMODE_SWCTRL,
1682                 },
1683         },
1684         .dev_attr       = &smartreflex_core_dev_attr,
1685 };
1686
1687 /* smartreflex_mpu */
1688 /* smartreflex_mpu dev_attr */
1689 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1690         .sensor_voltdm_name     = "mpu",
1691 };
1692
1693 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1694         .name           = "smartreflex_mpu",
1695         .class          = &dra7xx_smartreflex_hwmod_class,
1696         .clkdm_name     = "coreaon_clkdm",
1697         .main_clk       = "wkupaon_iclk_mux",
1698         .prcm = {
1699                 .omap4 = {
1700                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1701                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1702                         .modulemode   = MODULEMODE_SWCTRL,
1703                 },
1704         },
1705         .dev_attr       = &smartreflex_mpu_dev_attr,
1706 };
1707
1708 /*
1709  * 'spinlock' class
1710  *
1711  */
1712
1713 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1714         .rev_offs       = 0x0000,
1715         .sysc_offs      = 0x0010,
1716         .syss_offs      = 0x0014,
1717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1719                            SYSS_HAS_RESET_STATUS),
1720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1721         .sysc_fields    = &omap_hwmod_sysc_type1,
1722 };
1723
1724 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1725         .name   = "spinlock",
1726         .sysc   = &dra7xx_spinlock_sysc,
1727 };
1728
1729 /* spinlock */
1730 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1731         .name           = "spinlock",
1732         .class          = &dra7xx_spinlock_hwmod_class,
1733         .clkdm_name     = "l4cfg_clkdm",
1734         .main_clk       = "l3_iclk_div",
1735         .prcm = {
1736                 .omap4 = {
1737                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1738                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1739                 },
1740         },
1741 };
1742
1743 /*
1744  * 'timer' class
1745  *
1746  * This class contains several variants: ['timer_1ms', 'timer_secure',
1747  * 'timer']
1748  */
1749
1750 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1751         .rev_offs       = 0x0000,
1752         .sysc_offs      = 0x0010,
1753         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1754                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1755         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1756                            SIDLE_SMART_WKUP),
1757         .sysc_fields    = &omap_hwmod_sysc_type2,
1758 };
1759
1760 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1761         .name   = "timer",
1762         .sysc   = &dra7xx_timer_1ms_sysc,
1763 };
1764
1765 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1766         .rev_offs       = 0x0000,
1767         .sysc_offs      = 0x0010,
1768         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1769                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1770         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1771                            SIDLE_SMART_WKUP),
1772         .sysc_fields    = &omap_hwmod_sysc_type2,
1773 };
1774
1775 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1776         .name   = "timer",
1777         .sysc   = &dra7xx_timer_secure_sysc,
1778 };
1779
1780 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1781         .rev_offs       = 0x0000,
1782         .sysc_offs      = 0x0010,
1783         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1784                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1785         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1786                            SIDLE_SMART_WKUP),
1787         .sysc_fields    = &omap_hwmod_sysc_type2,
1788 };
1789
1790 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1791         .name   = "timer",
1792         .sysc   = &dra7xx_timer_sysc,
1793 };
1794
1795 /* timer1 */
1796 static struct omap_hwmod dra7xx_timer1_hwmod = {
1797         .name           = "timer1",
1798         .class          = &dra7xx_timer_1ms_hwmod_class,
1799         .clkdm_name     = "wkupaon_clkdm",
1800         .main_clk       = "timer1_gfclk_mux",
1801         .prcm = {
1802                 .omap4 = {
1803                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1804                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1805                         .modulemode   = MODULEMODE_SWCTRL,
1806                 },
1807         },
1808 };
1809
1810 /* timer2 */
1811 static struct omap_hwmod dra7xx_timer2_hwmod = {
1812         .name           = "timer2",
1813         .class          = &dra7xx_timer_1ms_hwmod_class,
1814         .clkdm_name     = "l4per_clkdm",
1815         .main_clk       = "timer2_gfclk_mux",
1816         .prcm = {
1817                 .omap4 = {
1818                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1819                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1820                         .modulemode   = MODULEMODE_SWCTRL,
1821                 },
1822         },
1823 };
1824
1825 /* timer3 */
1826 static struct omap_hwmod dra7xx_timer3_hwmod = {
1827         .name           = "timer3",
1828         .class          = &dra7xx_timer_hwmod_class,
1829         .clkdm_name     = "l4per_clkdm",
1830         .main_clk       = "timer3_gfclk_mux",
1831         .prcm = {
1832                 .omap4 = {
1833                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1834                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1835                         .modulemode   = MODULEMODE_SWCTRL,
1836                 },
1837         },
1838 };
1839
1840 /* timer4 */
1841 static struct omap_hwmod dra7xx_timer4_hwmod = {
1842         .name           = "timer4",
1843         .class          = &dra7xx_timer_secure_hwmod_class,
1844         .clkdm_name     = "l4per_clkdm",
1845         .main_clk       = "timer4_gfclk_mux",
1846         .prcm = {
1847                 .omap4 = {
1848                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1849                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1850                         .modulemode   = MODULEMODE_SWCTRL,
1851                 },
1852         },
1853 };
1854
1855 /* timer5 */
1856 static struct omap_hwmod dra7xx_timer5_hwmod = {
1857         .name           = "timer5",
1858         .class          = &dra7xx_timer_hwmod_class,
1859         .clkdm_name     = "ipu_clkdm",
1860         .main_clk       = "timer5_gfclk_mux",
1861         .prcm = {
1862                 .omap4 = {
1863                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1864                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1865                         .modulemode   = MODULEMODE_SWCTRL,
1866                 },
1867         },
1868 };
1869
1870 /* timer6 */
1871 static struct omap_hwmod dra7xx_timer6_hwmod = {
1872         .name           = "timer6",
1873         .class          = &dra7xx_timer_hwmod_class,
1874         .clkdm_name     = "ipu_clkdm",
1875         .main_clk       = "timer6_gfclk_mux",
1876         .prcm = {
1877                 .omap4 = {
1878                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1879                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1880                         .modulemode   = MODULEMODE_SWCTRL,
1881                 },
1882         },
1883 };
1884
1885 /* timer7 */
1886 static struct omap_hwmod dra7xx_timer7_hwmod = {
1887         .name           = "timer7",
1888         .class          = &dra7xx_timer_hwmod_class,
1889         .clkdm_name     = "ipu_clkdm",
1890         .main_clk       = "timer7_gfclk_mux",
1891         .prcm = {
1892                 .omap4 = {
1893                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1894                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1895                         .modulemode   = MODULEMODE_SWCTRL,
1896                 },
1897         },
1898 };
1899
1900 /* timer8 */
1901 static struct omap_hwmod dra7xx_timer8_hwmod = {
1902         .name           = "timer8",
1903         .class          = &dra7xx_timer_hwmod_class,
1904         .clkdm_name     = "ipu_clkdm",
1905         .main_clk       = "timer8_gfclk_mux",
1906         .prcm = {
1907                 .omap4 = {
1908                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1909                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1910                         .modulemode   = MODULEMODE_SWCTRL,
1911                 },
1912         },
1913 };
1914
1915 /* timer9 */
1916 static struct omap_hwmod dra7xx_timer9_hwmod = {
1917         .name           = "timer9",
1918         .class          = &dra7xx_timer_hwmod_class,
1919         .clkdm_name     = "l4per_clkdm",
1920         .main_clk       = "timer9_gfclk_mux",
1921         .prcm = {
1922                 .omap4 = {
1923                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1924                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1925                         .modulemode   = MODULEMODE_SWCTRL,
1926                 },
1927         },
1928 };
1929
1930 /* timer10 */
1931 static struct omap_hwmod dra7xx_timer10_hwmod = {
1932         .name           = "timer10",
1933         .class          = &dra7xx_timer_1ms_hwmod_class,
1934         .clkdm_name     = "l4per_clkdm",
1935         .main_clk       = "timer10_gfclk_mux",
1936         .prcm = {
1937                 .omap4 = {
1938                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1939                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1940                         .modulemode   = MODULEMODE_SWCTRL,
1941                 },
1942         },
1943 };
1944
1945 /* timer11 */
1946 static struct omap_hwmod dra7xx_timer11_hwmod = {
1947         .name           = "timer11",
1948         .class          = &dra7xx_timer_hwmod_class,
1949         .clkdm_name     = "l4per_clkdm",
1950         .main_clk       = "timer11_gfclk_mux",
1951         .prcm = {
1952                 .omap4 = {
1953                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1954                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1955                         .modulemode   = MODULEMODE_SWCTRL,
1956                 },
1957         },
1958 };
1959
1960 /*
1961  * 'uart' class
1962  *
1963  */
1964
1965 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1966         .rev_offs       = 0x0050,
1967         .sysc_offs      = 0x0054,
1968         .syss_offs      = 0x0058,
1969         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1970                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1971                            SYSS_HAS_RESET_STATUS),
1972         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1973                            SIDLE_SMART_WKUP),
1974         .sysc_fields    = &omap_hwmod_sysc_type1,
1975 };
1976
1977 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1978         .name   = "uart",
1979         .sysc   = &dra7xx_uart_sysc,
1980 };
1981
1982 /* uart1 */
1983 static struct omap_hwmod dra7xx_uart1_hwmod = {
1984         .name           = "uart1",
1985         .class          = &dra7xx_uart_hwmod_class,
1986         .clkdm_name     = "l4per_clkdm",
1987         .main_clk       = "uart1_gfclk_mux",
1988         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1989         .prcm = {
1990                 .omap4 = {
1991                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1992                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1993                         .modulemode   = MODULEMODE_SWCTRL,
1994                 },
1995         },
1996 };
1997
1998 /* uart2 */
1999 static struct omap_hwmod dra7xx_uart2_hwmod = {
2000         .name           = "uart2",
2001         .class          = &dra7xx_uart_hwmod_class,
2002         .clkdm_name     = "l4per_clkdm",
2003         .main_clk       = "uart2_gfclk_mux",
2004         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2005         .prcm = {
2006                 .omap4 = {
2007                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2008                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2009                         .modulemode   = MODULEMODE_SWCTRL,
2010                 },
2011         },
2012 };
2013
2014 /* uart3 */
2015 static struct omap_hwmod dra7xx_uart3_hwmod = {
2016         .name           = "uart3",
2017         .class          = &dra7xx_uart_hwmod_class,
2018         .clkdm_name     = "l4per_clkdm",
2019         .main_clk       = "uart3_gfclk_mux",
2020         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2024                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2025                         .modulemode   = MODULEMODE_SWCTRL,
2026                 },
2027         },
2028 };
2029
2030 /* uart4 */
2031 static struct omap_hwmod dra7xx_uart4_hwmod = {
2032         .name           = "uart4",
2033         .class          = &dra7xx_uart_hwmod_class,
2034         .clkdm_name     = "l4per_clkdm",
2035         .main_clk       = "uart4_gfclk_mux",
2036         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2037         .prcm = {
2038                 .omap4 = {
2039                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2040                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2041                         .modulemode   = MODULEMODE_SWCTRL,
2042                 },
2043         },
2044 };
2045
2046 /* uart5 */
2047 static struct omap_hwmod dra7xx_uart5_hwmod = {
2048         .name           = "uart5",
2049         .class          = &dra7xx_uart_hwmod_class,
2050         .clkdm_name     = "l4per_clkdm",
2051         .main_clk       = "uart5_gfclk_mux",
2052         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2053         .prcm = {
2054                 .omap4 = {
2055                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2056                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2057                         .modulemode   = MODULEMODE_SWCTRL,
2058                 },
2059         },
2060 };
2061
2062 /* uart6 */
2063 static struct omap_hwmod dra7xx_uart6_hwmod = {
2064         .name           = "uart6",
2065         .class          = &dra7xx_uart_hwmod_class,
2066         .clkdm_name     = "ipu_clkdm",
2067         .main_clk       = "uart6_gfclk_mux",
2068         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2069         .prcm = {
2070                 .omap4 = {
2071                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2072                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2073                         .modulemode   = MODULEMODE_SWCTRL,
2074                 },
2075         },
2076 };
2077
2078 /*
2079  * 'usb_otg_ss' class
2080  *
2081  */
2082
2083 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2084         .rev_offs       = 0x0000,
2085         .sysc_offs      = 0x0010,
2086         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2087                            SYSC_HAS_SIDLEMODE),
2088         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2089                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2090                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2091         .sysc_fields    = &omap_hwmod_sysc_type2,
2092 };
2093
2094 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2095         .name   = "usb_otg_ss",
2096         .sysc   = &dra7xx_usb_otg_ss_sysc,
2097 };
2098
2099 /* usb_otg_ss1 */
2100 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2101         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2102 };
2103
2104 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2105         .name           = "usb_otg_ss1",
2106         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2107         .clkdm_name     = "l3init_clkdm",
2108         .main_clk       = "dpll_core_h13x2_ck",
2109         .prcm = {
2110                 .omap4 = {
2111                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2112                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2113                         .modulemode   = MODULEMODE_HWCTRL,
2114                 },
2115         },
2116         .opt_clks       = usb_otg_ss1_opt_clks,
2117         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2118 };
2119
2120 /* usb_otg_ss2 */
2121 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2122         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2123 };
2124
2125 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2126         .name           = "usb_otg_ss2",
2127         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2128         .clkdm_name     = "l3init_clkdm",
2129         .main_clk       = "dpll_core_h13x2_ck",
2130         .prcm = {
2131                 .omap4 = {
2132                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2133                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2134                         .modulemode   = MODULEMODE_HWCTRL,
2135                 },
2136         },
2137         .opt_clks       = usb_otg_ss2_opt_clks,
2138         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2139 };
2140
2141 /* usb_otg_ss3 */
2142 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2143         .name           = "usb_otg_ss3",
2144         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2145         .clkdm_name     = "l3init_clkdm",
2146         .main_clk       = "dpll_core_h13x2_ck",
2147         .prcm = {
2148                 .omap4 = {
2149                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2150                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2151                         .modulemode   = MODULEMODE_HWCTRL,
2152                 },
2153         },
2154 };
2155
2156 /* usb_otg_ss4 */
2157 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2158         .name           = "usb_otg_ss4",
2159         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2160         .clkdm_name     = "l3init_clkdm",
2161         .main_clk       = "dpll_core_h13x2_ck",
2162         .prcm = {
2163                 .omap4 = {
2164                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2165                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2166                         .modulemode   = MODULEMODE_HWCTRL,
2167                 },
2168         },
2169 };
2170
2171 /*
2172  * 'vcp' class
2173  *
2174  */
2175
2176 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2177         .name   = "vcp",
2178 };
2179
2180 /* vcp1 */
2181 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2182         .name           = "vcp1",
2183         .class          = &dra7xx_vcp_hwmod_class,
2184         .clkdm_name     = "l3main1_clkdm",
2185         .main_clk       = "l3_iclk_div",
2186         .prcm = {
2187                 .omap4 = {
2188                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2189                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2190                 },
2191         },
2192 };
2193
2194 /* vcp2 */
2195 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2196         .name           = "vcp2",
2197         .class          = &dra7xx_vcp_hwmod_class,
2198         .clkdm_name     = "l3main1_clkdm",
2199         .main_clk       = "l3_iclk_div",
2200         .prcm = {
2201                 .omap4 = {
2202                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2203                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2204                 },
2205         },
2206 };
2207
2208 /*
2209  * 'wd_timer' class
2210  *
2211  */
2212
2213 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2214         .rev_offs       = 0x0000,
2215         .sysc_offs      = 0x0010,
2216         .syss_offs      = 0x0014,
2217         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2218                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2219         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2220                            SIDLE_SMART_WKUP),
2221         .sysc_fields    = &omap_hwmod_sysc_type1,
2222 };
2223
2224 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2225         .name           = "wd_timer",
2226         .sysc           = &dra7xx_wd_timer_sysc,
2227         .pre_shutdown   = &omap2_wd_timer_disable,
2228         .reset          = &omap2_wd_timer_reset,
2229 };
2230
2231 /* wd_timer2 */
2232 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2233         .name           = "wd_timer2",
2234         .class          = &dra7xx_wd_timer_hwmod_class,
2235         .clkdm_name     = "wkupaon_clkdm",
2236         .main_clk       = "sys_32k_ck",
2237         .prcm = {
2238                 .omap4 = {
2239                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2240                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2241                         .modulemode   = MODULEMODE_SWCTRL,
2242                 },
2243         },
2244 };
2245
2246
2247 /*
2248  * Interfaces
2249  */
2250
2251 /* l3_main_2 -> l3_instr */
2252 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2253         .master         = &dra7xx_l3_main_2_hwmod,
2254         .slave          = &dra7xx_l3_instr_hwmod,
2255         .clk            = "l3_iclk_div",
2256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2257 };
2258
2259 /* l4_cfg -> l3_main_1 */
2260 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2261         .master         = &dra7xx_l4_cfg_hwmod,
2262         .slave          = &dra7xx_l3_main_1_hwmod,
2263         .clk            = "l3_iclk_div",
2264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2265 };
2266
2267 /* mpu -> l3_main_1 */
2268 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2269         .master         = &dra7xx_mpu_hwmod,
2270         .slave          = &dra7xx_l3_main_1_hwmod,
2271         .clk            = "l3_iclk_div",
2272         .user           = OCP_USER_MPU,
2273 };
2274
2275 /* l3_main_1 -> l3_main_2 */
2276 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2277         .master         = &dra7xx_l3_main_1_hwmod,
2278         .slave          = &dra7xx_l3_main_2_hwmod,
2279         .clk            = "l3_iclk_div",
2280         .user           = OCP_USER_MPU,
2281 };
2282
2283 /* l4_cfg -> l3_main_2 */
2284 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2285         .master         = &dra7xx_l4_cfg_hwmod,
2286         .slave          = &dra7xx_l3_main_2_hwmod,
2287         .clk            = "l3_iclk_div",
2288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2289 };
2290
2291 /* l3_main_1 -> l4_cfg */
2292 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2293         .master         = &dra7xx_l3_main_1_hwmod,
2294         .slave          = &dra7xx_l4_cfg_hwmod,
2295         .clk            = "l3_iclk_div",
2296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2298
2299 /* l3_main_1 -> l4_per1 */
2300 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2301         .master         = &dra7xx_l3_main_1_hwmod,
2302         .slave          = &dra7xx_l4_per1_hwmod,
2303         .clk            = "l3_iclk_div",
2304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2305 };
2306
2307 /* l3_main_1 -> l4_per2 */
2308 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2309         .master         = &dra7xx_l3_main_1_hwmod,
2310         .slave          = &dra7xx_l4_per2_hwmod,
2311         .clk            = "l3_iclk_div",
2312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2313 };
2314
2315 /* l3_main_1 -> l4_per3 */
2316 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2317         .master         = &dra7xx_l3_main_1_hwmod,
2318         .slave          = &dra7xx_l4_per3_hwmod,
2319         .clk            = "l3_iclk_div",
2320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2321 };
2322
2323 /* l3_main_1 -> l4_wkup */
2324 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2325         .master         = &dra7xx_l3_main_1_hwmod,
2326         .slave          = &dra7xx_l4_wkup_hwmod,
2327         .clk            = "wkupaon_iclk_mux",
2328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2329 };
2330
2331 /* l4_per2 -> atl */
2332 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2333         .master         = &dra7xx_l4_per2_hwmod,
2334         .slave          = &dra7xx_atl_hwmod,
2335         .clk            = "l3_iclk_div",
2336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2337 };
2338
2339 /* l3_main_1 -> bb2d */
2340 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2341         .master         = &dra7xx_l3_main_1_hwmod,
2342         .slave          = &dra7xx_bb2d_hwmod,
2343         .clk            = "l3_iclk_div",
2344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2345 };
2346
2347 /* l4_wkup -> counter_32k */
2348 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2349         .master         = &dra7xx_l4_wkup_hwmod,
2350         .slave          = &dra7xx_counter_32k_hwmod,
2351         .clk            = "wkupaon_iclk_mux",
2352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* l4_wkup -> ctrl_module_wkup */
2356 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2357         .master         = &dra7xx_l4_wkup_hwmod,
2358         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2359         .clk            = "wkupaon_iclk_mux",
2360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2361 };
2362
2363 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2364         .master         = &dra7xx_l4_per2_hwmod,
2365         .slave          = &dra7xx_gmac_hwmod,
2366         .clk            = "dpll_gmac_ck",
2367         .user           = OCP_USER_MPU,
2368 };
2369
2370 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2371         .master         = &dra7xx_gmac_hwmod,
2372         .slave          = &dra7xx_mdio_hwmod,
2373         .user           = OCP_USER_MPU,
2374 };
2375
2376 /* l4_wkup -> dcan1 */
2377 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2378         .master         = &dra7xx_l4_wkup_hwmod,
2379         .slave          = &dra7xx_dcan1_hwmod,
2380         .clk            = "wkupaon_iclk_mux",
2381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* l4_per2 -> dcan2 */
2385 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2386         .master         = &dra7xx_l4_per2_hwmod,
2387         .slave          = &dra7xx_dcan2_hwmod,
2388         .clk            = "l3_iclk_div",
2389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2390 };
2391
2392 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2393         {
2394                 .pa_start       = 0x4a056000,
2395                 .pa_end         = 0x4a056fff,
2396                 .flags          = ADDR_TYPE_RT
2397         },
2398         { }
2399 };
2400
2401 /* l4_cfg -> dma_system */
2402 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2403         .master         = &dra7xx_l4_cfg_hwmod,
2404         .slave          = &dra7xx_dma_system_hwmod,
2405         .clk            = "l3_iclk_div",
2406         .addr           = dra7xx_dma_system_addrs,
2407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2408 };
2409
2410 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2411         {
2412                 .name           = "family",
2413                 .pa_start       = 0x58000000,
2414                 .pa_end         = 0x5800007f,
2415                 .flags          = ADDR_TYPE_RT
2416         },
2417 };
2418
2419 /* l3_main_1 -> dss */
2420 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2421         .master         = &dra7xx_l3_main_1_hwmod,
2422         .slave          = &dra7xx_dss_hwmod,
2423         .clk            = "l3_iclk_div",
2424         .addr           = dra7xx_dss_addrs,
2425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2429         {
2430                 .name           = "dispc",
2431                 .pa_start       = 0x58001000,
2432                 .pa_end         = 0x58001fff,
2433                 .flags          = ADDR_TYPE_RT
2434         },
2435 };
2436
2437 /* l3_main_1 -> dispc */
2438 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2439         .master         = &dra7xx_l3_main_1_hwmod,
2440         .slave          = &dra7xx_dss_dispc_hwmod,
2441         .clk            = "l3_iclk_div",
2442         .addr           = dra7xx_dss_dispc_addrs,
2443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2447         {
2448                 .name           = "hdmi_wp",
2449                 .pa_start       = 0x58040000,
2450                 .pa_end         = 0x580400ff,
2451                 .flags          = ADDR_TYPE_RT
2452         },
2453         { }
2454 };
2455
2456 /* l3_main_1 -> dispc */
2457 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2458         .master         = &dra7xx_l3_main_1_hwmod,
2459         .slave          = &dra7xx_dss_hdmi_hwmod,
2460         .clk            = "l3_iclk_div",
2461         .addr           = dra7xx_dss_hdmi_addrs,
2462         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2463 };
2464
2465 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2466         {
2467                 .pa_start       = 0x48078000,
2468                 .pa_end         = 0x48078fff,
2469                 .flags          = ADDR_TYPE_RT
2470         },
2471         { }
2472 };
2473
2474 /* l4_per1 -> elm */
2475 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2476         .master         = &dra7xx_l4_per1_hwmod,
2477         .slave          = &dra7xx_elm_hwmod,
2478         .clk            = "l3_iclk_div",
2479         .addr           = dra7xx_elm_addrs,
2480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2481 };
2482
2483 /* l4_wkup -> gpio1 */
2484 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2485         .master         = &dra7xx_l4_wkup_hwmod,
2486         .slave          = &dra7xx_gpio1_hwmod,
2487         .clk            = "wkupaon_iclk_mux",
2488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2489 };
2490
2491 /* l4_per1 -> gpio2 */
2492 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2493         .master         = &dra7xx_l4_per1_hwmod,
2494         .slave          = &dra7xx_gpio2_hwmod,
2495         .clk            = "l3_iclk_div",
2496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2497 };
2498
2499 /* l4_per1 -> gpio3 */
2500 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2501         .master         = &dra7xx_l4_per1_hwmod,
2502         .slave          = &dra7xx_gpio3_hwmod,
2503         .clk            = "l3_iclk_div",
2504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2505 };
2506
2507 /* l4_per1 -> gpio4 */
2508 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2509         .master         = &dra7xx_l4_per1_hwmod,
2510         .slave          = &dra7xx_gpio4_hwmod,
2511         .clk            = "l3_iclk_div",
2512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2513 };
2514
2515 /* l4_per1 -> gpio5 */
2516 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2517         .master         = &dra7xx_l4_per1_hwmod,
2518         .slave          = &dra7xx_gpio5_hwmod,
2519         .clk            = "l3_iclk_div",
2520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2521 };
2522
2523 /* l4_per1 -> gpio6 */
2524 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2525         .master         = &dra7xx_l4_per1_hwmod,
2526         .slave          = &dra7xx_gpio6_hwmod,
2527         .clk            = "l3_iclk_div",
2528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2529 };
2530
2531 /* l4_per1 -> gpio7 */
2532 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2533         .master         = &dra7xx_l4_per1_hwmod,
2534         .slave          = &dra7xx_gpio7_hwmod,
2535         .clk            = "l3_iclk_div",
2536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2537 };
2538
2539 /* l4_per1 -> gpio8 */
2540 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2541         .master         = &dra7xx_l4_per1_hwmod,
2542         .slave          = &dra7xx_gpio8_hwmod,
2543         .clk            = "l3_iclk_div",
2544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2548         {
2549                 .pa_start       = 0x50000000,
2550                 .pa_end         = 0x500003ff,
2551                 .flags          = ADDR_TYPE_RT
2552         },
2553         { }
2554 };
2555
2556 /* l3_main_1 -> gpmc */
2557 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2558         .master         = &dra7xx_l3_main_1_hwmod,
2559         .slave          = &dra7xx_gpmc_hwmod,
2560         .clk            = "l3_iclk_div",
2561         .addr           = dra7xx_gpmc_addrs,
2562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2563 };
2564
2565 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2566         {
2567                 .pa_start       = 0x480b2000,
2568                 .pa_end         = 0x480b201f,
2569                 .flags          = ADDR_TYPE_RT
2570         },
2571         { }
2572 };
2573
2574 /* l4_per1 -> hdq1w */
2575 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2576         .master         = &dra7xx_l4_per1_hwmod,
2577         .slave          = &dra7xx_hdq1w_hwmod,
2578         .clk            = "l3_iclk_div",
2579         .addr           = dra7xx_hdq1w_addrs,
2580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 /* l4_per1 -> i2c1 */
2584 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2585         .master         = &dra7xx_l4_per1_hwmod,
2586         .slave          = &dra7xx_i2c1_hwmod,
2587         .clk            = "l3_iclk_div",
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* l4_per1 -> i2c2 */
2592 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2593         .master         = &dra7xx_l4_per1_hwmod,
2594         .slave          = &dra7xx_i2c2_hwmod,
2595         .clk            = "l3_iclk_div",
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* l4_per1 -> i2c3 */
2600 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2601         .master         = &dra7xx_l4_per1_hwmod,
2602         .slave          = &dra7xx_i2c3_hwmod,
2603         .clk            = "l3_iclk_div",
2604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 /* l4_per1 -> i2c4 */
2608 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2609         .master         = &dra7xx_l4_per1_hwmod,
2610         .slave          = &dra7xx_i2c4_hwmod,
2611         .clk            = "l3_iclk_div",
2612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l4_per1 -> i2c5 */
2616 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2617         .master         = &dra7xx_l4_per1_hwmod,
2618         .slave          = &dra7xx_i2c5_hwmod,
2619         .clk            = "l3_iclk_div",
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* l4_cfg -> mailbox1 */
2624 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2625         .master         = &dra7xx_l4_cfg_hwmod,
2626         .slave          = &dra7xx_mailbox1_hwmod,
2627         .clk            = "l3_iclk_div",
2628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* l4_per3 -> mailbox2 */
2632 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2633         .master         = &dra7xx_l4_per3_hwmod,
2634         .slave          = &dra7xx_mailbox2_hwmod,
2635         .clk            = "l3_iclk_div",
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 /* l4_per3 -> mailbox3 */
2640 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2641         .master         = &dra7xx_l4_per3_hwmod,
2642         .slave          = &dra7xx_mailbox3_hwmod,
2643         .clk            = "l3_iclk_div",
2644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2645 };
2646
2647 /* l4_per3 -> mailbox4 */
2648 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2649         .master         = &dra7xx_l4_per3_hwmod,
2650         .slave          = &dra7xx_mailbox4_hwmod,
2651         .clk            = "l3_iclk_div",
2652         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 /* l4_per3 -> mailbox5 */
2656 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2657         .master         = &dra7xx_l4_per3_hwmod,
2658         .slave          = &dra7xx_mailbox5_hwmod,
2659         .clk            = "l3_iclk_div",
2660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2662
2663 /* l4_per3 -> mailbox6 */
2664 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2665         .master         = &dra7xx_l4_per3_hwmod,
2666         .slave          = &dra7xx_mailbox6_hwmod,
2667         .clk            = "l3_iclk_div",
2668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 /* l4_per3 -> mailbox7 */
2672 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2673         .master         = &dra7xx_l4_per3_hwmod,
2674         .slave          = &dra7xx_mailbox7_hwmod,
2675         .clk            = "l3_iclk_div",
2676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* l4_per3 -> mailbox8 */
2680 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2681         .master         = &dra7xx_l4_per3_hwmod,
2682         .slave          = &dra7xx_mailbox8_hwmod,
2683         .clk            = "l3_iclk_div",
2684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2685 };
2686
2687 /* l4_per3 -> mailbox9 */
2688 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2689         .master         = &dra7xx_l4_per3_hwmod,
2690         .slave          = &dra7xx_mailbox9_hwmod,
2691         .clk            = "l3_iclk_div",
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 /* l4_per3 -> mailbox10 */
2696 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2697         .master         = &dra7xx_l4_per3_hwmod,
2698         .slave          = &dra7xx_mailbox10_hwmod,
2699         .clk            = "l3_iclk_div",
2700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 /* l4_per3 -> mailbox11 */
2704 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2705         .master         = &dra7xx_l4_per3_hwmod,
2706         .slave          = &dra7xx_mailbox11_hwmod,
2707         .clk            = "l3_iclk_div",
2708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2709 };
2710
2711 /* l4_per3 -> mailbox12 */
2712 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2713         .master         = &dra7xx_l4_per3_hwmod,
2714         .slave          = &dra7xx_mailbox12_hwmod,
2715         .clk            = "l3_iclk_div",
2716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2717 };
2718
2719 /* l4_per3 -> mailbox13 */
2720 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2721         .master         = &dra7xx_l4_per3_hwmod,
2722         .slave          = &dra7xx_mailbox13_hwmod,
2723         .clk            = "l3_iclk_div",
2724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* l4_per1 -> mcspi1 */
2728 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2729         .master         = &dra7xx_l4_per1_hwmod,
2730         .slave          = &dra7xx_mcspi1_hwmod,
2731         .clk            = "l3_iclk_div",
2732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2733 };
2734
2735 /* l4_per1 -> mcspi2 */
2736 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2737         .master         = &dra7xx_l4_per1_hwmod,
2738         .slave          = &dra7xx_mcspi2_hwmod,
2739         .clk            = "l3_iclk_div",
2740         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2741 };
2742
2743 /* l4_per1 -> mcspi3 */
2744 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2745         .master         = &dra7xx_l4_per1_hwmod,
2746         .slave          = &dra7xx_mcspi3_hwmod,
2747         .clk            = "l3_iclk_div",
2748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2749 };
2750
2751 /* l4_per1 -> mcspi4 */
2752 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2753         .master         = &dra7xx_l4_per1_hwmod,
2754         .slave          = &dra7xx_mcspi4_hwmod,
2755         .clk            = "l3_iclk_div",
2756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /* l4_per1 -> mmc1 */
2760 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2761         .master         = &dra7xx_l4_per1_hwmod,
2762         .slave          = &dra7xx_mmc1_hwmod,
2763         .clk            = "l3_iclk_div",
2764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_per1 -> mmc2 */
2768 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2769         .master         = &dra7xx_l4_per1_hwmod,
2770         .slave          = &dra7xx_mmc2_hwmod,
2771         .clk            = "l3_iclk_div",
2772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2774
2775 /* l4_per1 -> mmc3 */
2776 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2777         .master         = &dra7xx_l4_per1_hwmod,
2778         .slave          = &dra7xx_mmc3_hwmod,
2779         .clk            = "l3_iclk_div",
2780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2781 };
2782
2783 /* l4_per1 -> mmc4 */
2784 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2785         .master         = &dra7xx_l4_per1_hwmod,
2786         .slave          = &dra7xx_mmc4_hwmod,
2787         .clk            = "l3_iclk_div",
2788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2789 };
2790
2791 /* l4_cfg -> mpu */
2792 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2793         .master         = &dra7xx_l4_cfg_hwmod,
2794         .slave          = &dra7xx_mpu_hwmod,
2795         .clk            = "l3_iclk_div",
2796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2797 };
2798
2799 /* l4_cfg -> ocp2scp1 */
2800 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2801         .master         = &dra7xx_l4_cfg_hwmod,
2802         .slave          = &dra7xx_ocp2scp1_hwmod,
2803         .clk            = "l4_root_clk_div",
2804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /* l4_cfg -> ocp2scp3 */
2808 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2809         .master         = &dra7xx_l4_cfg_hwmod,
2810         .slave          = &dra7xx_ocp2scp3_hwmod,
2811         .clk            = "l4_root_clk_div",
2812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2813 };
2814
2815 /* l3_main_1 -> pcie1 */
2816 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2817         .master         = &dra7xx_l3_main_1_hwmod,
2818         .slave          = &dra7xx_pcie1_hwmod,
2819         .clk            = "l3_iclk_div",
2820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2821 };
2822
2823 /* l4_cfg -> pcie1 */
2824 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2825         .master         = &dra7xx_l4_cfg_hwmod,
2826         .slave          = &dra7xx_pcie1_hwmod,
2827         .clk            = "l4_root_clk_div",
2828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* l3_main_1 -> pcie2 */
2832 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2833         .master         = &dra7xx_l3_main_1_hwmod,
2834         .slave          = &dra7xx_pcie2_hwmod,
2835         .clk            = "l3_iclk_div",
2836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 /* l4_cfg -> pcie2 */
2840 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2841         .master         = &dra7xx_l4_cfg_hwmod,
2842         .slave          = &dra7xx_pcie2_hwmod,
2843         .clk            = "l4_root_clk_div",
2844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 /* l4_cfg -> pcie1 phy */
2848 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2849         .master         = &dra7xx_l4_cfg_hwmod,
2850         .slave          = &dra7xx_pcie1_phy_hwmod,
2851         .clk            = "l4_root_clk_div",
2852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 /* l4_cfg -> pcie2 phy */
2856 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2857         .master         = &dra7xx_l4_cfg_hwmod,
2858         .slave          = &dra7xx_pcie2_phy_hwmod,
2859         .clk            = "l4_root_clk_div",
2860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2861 };
2862
2863 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2864         {
2865                 .pa_start       = 0x4b300000,
2866                 .pa_end         = 0x4b30007f,
2867                 .flags          = ADDR_TYPE_RT
2868         },
2869         { }
2870 };
2871
2872 /* l3_main_1 -> qspi */
2873 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2874         .master         = &dra7xx_l3_main_1_hwmod,
2875         .slave          = &dra7xx_qspi_hwmod,
2876         .clk            = "l3_iclk_div",
2877         .addr           = dra7xx_qspi_addrs,
2878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2879 };
2880
2881 /* l4_per3 -> rtcss */
2882 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2883         .master         = &dra7xx_l4_per3_hwmod,
2884         .slave          = &dra7xx_rtcss_hwmod,
2885         .clk            = "l4_root_clk_div",
2886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2887 };
2888
2889 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2890         {
2891                 .name           = "sysc",
2892                 .pa_start       = 0x4a141100,
2893                 .pa_end         = 0x4a141107,
2894                 .flags          = ADDR_TYPE_RT
2895         },
2896         { }
2897 };
2898
2899 /* l4_cfg -> sata */
2900 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2901         .master         = &dra7xx_l4_cfg_hwmod,
2902         .slave          = &dra7xx_sata_hwmod,
2903         .clk            = "l3_iclk_div",
2904         .addr           = dra7xx_sata_addrs,
2905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2906 };
2907
2908 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2909         {
2910                 .pa_start       = 0x4a0dd000,
2911                 .pa_end         = 0x4a0dd07f,
2912                 .flags          = ADDR_TYPE_RT
2913         },
2914         { }
2915 };
2916
2917 /* l4_cfg -> smartreflex_core */
2918 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2919         .master         = &dra7xx_l4_cfg_hwmod,
2920         .slave          = &dra7xx_smartreflex_core_hwmod,
2921         .clk            = "l4_root_clk_div",
2922         .addr           = dra7xx_smartreflex_core_addrs,
2923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2924 };
2925
2926 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2927         {
2928                 .pa_start       = 0x4a0d9000,
2929                 .pa_end         = 0x4a0d907f,
2930                 .flags          = ADDR_TYPE_RT
2931         },
2932         { }
2933 };
2934
2935 /* l4_cfg -> smartreflex_mpu */
2936 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2937         .master         = &dra7xx_l4_cfg_hwmod,
2938         .slave          = &dra7xx_smartreflex_mpu_hwmod,
2939         .clk            = "l4_root_clk_div",
2940         .addr           = dra7xx_smartreflex_mpu_addrs,
2941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2942 };
2943
2944 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2945         {
2946                 .pa_start       = 0x4a0f6000,
2947                 .pa_end         = 0x4a0f6fff,
2948                 .flags          = ADDR_TYPE_RT
2949         },
2950         { }
2951 };
2952
2953 /* l4_cfg -> spinlock */
2954 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2955         .master         = &dra7xx_l4_cfg_hwmod,
2956         .slave          = &dra7xx_spinlock_hwmod,
2957         .clk            = "l3_iclk_div",
2958         .addr           = dra7xx_spinlock_addrs,
2959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2960 };
2961
2962 /* l4_wkup -> timer1 */
2963 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2964         .master         = &dra7xx_l4_wkup_hwmod,
2965         .slave          = &dra7xx_timer1_hwmod,
2966         .clk            = "wkupaon_iclk_mux",
2967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2968 };
2969
2970 /* l4_per1 -> timer2 */
2971 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2972         .master         = &dra7xx_l4_per1_hwmod,
2973         .slave          = &dra7xx_timer2_hwmod,
2974         .clk            = "l3_iclk_div",
2975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2976 };
2977
2978 /* l4_per1 -> timer3 */
2979 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2980         .master         = &dra7xx_l4_per1_hwmod,
2981         .slave          = &dra7xx_timer3_hwmod,
2982         .clk            = "l3_iclk_div",
2983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2984 };
2985
2986 /* l4_per1 -> timer4 */
2987 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2988         .master         = &dra7xx_l4_per1_hwmod,
2989         .slave          = &dra7xx_timer4_hwmod,
2990         .clk            = "l3_iclk_div",
2991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2992 };
2993
2994 /* l4_per3 -> timer5 */
2995 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2996         .master         = &dra7xx_l4_per3_hwmod,
2997         .slave          = &dra7xx_timer5_hwmod,
2998         .clk            = "l3_iclk_div",
2999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3000 };
3001
3002 /* l4_per3 -> timer6 */
3003 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3004         .master         = &dra7xx_l4_per3_hwmod,
3005         .slave          = &dra7xx_timer6_hwmod,
3006         .clk            = "l3_iclk_div",
3007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3008 };
3009
3010 /* l4_per3 -> timer7 */
3011 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3012         .master         = &dra7xx_l4_per3_hwmod,
3013         .slave          = &dra7xx_timer7_hwmod,
3014         .clk            = "l3_iclk_div",
3015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3016 };
3017
3018 /* l4_per3 -> timer8 */
3019 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3020         .master         = &dra7xx_l4_per3_hwmod,
3021         .slave          = &dra7xx_timer8_hwmod,
3022         .clk            = "l3_iclk_div",
3023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3024 };
3025
3026 /* l4_per1 -> timer9 */
3027 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3028         .master         = &dra7xx_l4_per1_hwmod,
3029         .slave          = &dra7xx_timer9_hwmod,
3030         .clk            = "l3_iclk_div",
3031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3032 };
3033
3034 /* l4_per1 -> timer10 */
3035 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3036         .master         = &dra7xx_l4_per1_hwmod,
3037         .slave          = &dra7xx_timer10_hwmod,
3038         .clk            = "l3_iclk_div",
3039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3040 };
3041
3042 /* l4_per1 -> timer11 */
3043 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3044         .master         = &dra7xx_l4_per1_hwmod,
3045         .slave          = &dra7xx_timer11_hwmod,
3046         .clk            = "l3_iclk_div",
3047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3048 };
3049
3050 /* l4_per1 -> uart1 */
3051 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3052         .master         = &dra7xx_l4_per1_hwmod,
3053         .slave          = &dra7xx_uart1_hwmod,
3054         .clk            = "l3_iclk_div",
3055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3056 };
3057
3058 /* l4_per1 -> uart2 */
3059 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3060         .master         = &dra7xx_l4_per1_hwmod,
3061         .slave          = &dra7xx_uart2_hwmod,
3062         .clk            = "l3_iclk_div",
3063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3064 };
3065
3066 /* l4_per1 -> uart3 */
3067 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3068         .master         = &dra7xx_l4_per1_hwmod,
3069         .slave          = &dra7xx_uart3_hwmod,
3070         .clk            = "l3_iclk_div",
3071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3072 };
3073
3074 /* l4_per1 -> uart4 */
3075 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3076         .master         = &dra7xx_l4_per1_hwmod,
3077         .slave          = &dra7xx_uart4_hwmod,
3078         .clk            = "l3_iclk_div",
3079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3080 };
3081
3082 /* l4_per1 -> uart5 */
3083 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3084         .master         = &dra7xx_l4_per1_hwmod,
3085         .slave          = &dra7xx_uart5_hwmod,
3086         .clk            = "l3_iclk_div",
3087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3088 };
3089
3090 /* l4_per1 -> uart6 */
3091 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3092         .master         = &dra7xx_l4_per1_hwmod,
3093         .slave          = &dra7xx_uart6_hwmod,
3094         .clk            = "l3_iclk_div",
3095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3096 };
3097
3098 /* l4_per3 -> usb_otg_ss1 */
3099 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3100         .master         = &dra7xx_l4_per3_hwmod,
3101         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3102         .clk            = "dpll_core_h13x2_ck",
3103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3104 };
3105
3106 /* l4_per3 -> usb_otg_ss2 */
3107 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3108         .master         = &dra7xx_l4_per3_hwmod,
3109         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3110         .clk            = "dpll_core_h13x2_ck",
3111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3112 };
3113
3114 /* l4_per3 -> usb_otg_ss3 */
3115 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3116         .master         = &dra7xx_l4_per3_hwmod,
3117         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3118         .clk            = "dpll_core_h13x2_ck",
3119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3120 };
3121
3122 /* l4_per3 -> usb_otg_ss4 */
3123 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3124         .master         = &dra7xx_l4_per3_hwmod,
3125         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3126         .clk            = "dpll_core_h13x2_ck",
3127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3128 };
3129
3130 /* l3_main_1 -> vcp1 */
3131 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3132         .master         = &dra7xx_l3_main_1_hwmod,
3133         .slave          = &dra7xx_vcp1_hwmod,
3134         .clk            = "l3_iclk_div",
3135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /* l4_per2 -> vcp1 */
3139 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3140         .master         = &dra7xx_l4_per2_hwmod,
3141         .slave          = &dra7xx_vcp1_hwmod,
3142         .clk            = "l3_iclk_div",
3143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3144 };
3145
3146 /* l3_main_1 -> vcp2 */
3147 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3148         .master         = &dra7xx_l3_main_1_hwmod,
3149         .slave          = &dra7xx_vcp2_hwmod,
3150         .clk            = "l3_iclk_div",
3151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3152 };
3153
3154 /* l4_per2 -> vcp2 */
3155 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3156         .master         = &dra7xx_l4_per2_hwmod,
3157         .slave          = &dra7xx_vcp2_hwmod,
3158         .clk            = "l3_iclk_div",
3159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3160 };
3161
3162 /* l4_wkup -> wd_timer2 */
3163 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3164         .master         = &dra7xx_l4_wkup_hwmod,
3165         .slave          = &dra7xx_wd_timer2_hwmod,
3166         .clk            = "wkupaon_iclk_mux",
3167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3168 };
3169
3170 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3171         &dra7xx_l3_main_2__l3_instr,
3172         &dra7xx_l4_cfg__l3_main_1,
3173         &dra7xx_mpu__l3_main_1,
3174         &dra7xx_l3_main_1__l3_main_2,
3175         &dra7xx_l4_cfg__l3_main_2,
3176         &dra7xx_l3_main_1__l4_cfg,
3177         &dra7xx_l3_main_1__l4_per1,
3178         &dra7xx_l3_main_1__l4_per2,
3179         &dra7xx_l3_main_1__l4_per3,
3180         &dra7xx_l3_main_1__l4_wkup,
3181         &dra7xx_l4_per2__atl,
3182         &dra7xx_l3_main_1__bb2d,
3183         &dra7xx_l4_wkup__counter_32k,
3184         &dra7xx_l4_wkup__ctrl_module_wkup,
3185         &dra7xx_l4_wkup__dcan1,
3186         &dra7xx_l4_per2__dcan2,
3187         &dra7xx_l4_per2__cpgmac0,
3188         &dra7xx_gmac__mdio,
3189         &dra7xx_l4_cfg__dma_system,
3190         &dra7xx_l3_main_1__dss,
3191         &dra7xx_l3_main_1__dispc,
3192         &dra7xx_l3_main_1__hdmi,
3193         &dra7xx_l4_per1__elm,
3194         &dra7xx_l4_wkup__gpio1,
3195         &dra7xx_l4_per1__gpio2,
3196         &dra7xx_l4_per1__gpio3,
3197         &dra7xx_l4_per1__gpio4,
3198         &dra7xx_l4_per1__gpio5,
3199         &dra7xx_l4_per1__gpio6,
3200         &dra7xx_l4_per1__gpio7,
3201         &dra7xx_l4_per1__gpio8,
3202         &dra7xx_l3_main_1__gpmc,
3203         &dra7xx_l4_per1__hdq1w,
3204         &dra7xx_l4_per1__i2c1,
3205         &dra7xx_l4_per1__i2c2,
3206         &dra7xx_l4_per1__i2c3,
3207         &dra7xx_l4_per1__i2c4,
3208         &dra7xx_l4_per1__i2c5,
3209         &dra7xx_l4_cfg__mailbox1,
3210         &dra7xx_l4_per3__mailbox2,
3211         &dra7xx_l4_per3__mailbox3,
3212         &dra7xx_l4_per3__mailbox4,
3213         &dra7xx_l4_per3__mailbox5,
3214         &dra7xx_l4_per3__mailbox6,
3215         &dra7xx_l4_per3__mailbox7,
3216         &dra7xx_l4_per3__mailbox8,
3217         &dra7xx_l4_per3__mailbox9,
3218         &dra7xx_l4_per3__mailbox10,
3219         &dra7xx_l4_per3__mailbox11,
3220         &dra7xx_l4_per3__mailbox12,
3221         &dra7xx_l4_per3__mailbox13,
3222         &dra7xx_l4_per1__mcspi1,
3223         &dra7xx_l4_per1__mcspi2,
3224         &dra7xx_l4_per1__mcspi3,
3225         &dra7xx_l4_per1__mcspi4,
3226         &dra7xx_l4_per1__mmc1,
3227         &dra7xx_l4_per1__mmc2,
3228         &dra7xx_l4_per1__mmc3,
3229         &dra7xx_l4_per1__mmc4,
3230         &dra7xx_l4_cfg__mpu,
3231         &dra7xx_l4_cfg__ocp2scp1,
3232         &dra7xx_l4_cfg__ocp2scp3,
3233         &dra7xx_l3_main_1__pcie1,
3234         &dra7xx_l4_cfg__pcie1,
3235         &dra7xx_l3_main_1__pcie2,
3236         &dra7xx_l4_cfg__pcie2,
3237         &dra7xx_l4_cfg__pcie1_phy,
3238         &dra7xx_l4_cfg__pcie2_phy,
3239         &dra7xx_l3_main_1__qspi,
3240         &dra7xx_l4_per3__rtcss,
3241         &dra7xx_l4_cfg__sata,
3242         &dra7xx_l4_cfg__smartreflex_core,
3243         &dra7xx_l4_cfg__smartreflex_mpu,
3244         &dra7xx_l4_cfg__spinlock,
3245         &dra7xx_l4_wkup__timer1,
3246         &dra7xx_l4_per1__timer2,
3247         &dra7xx_l4_per1__timer3,
3248         &dra7xx_l4_per1__timer4,
3249         &dra7xx_l4_per3__timer5,
3250         &dra7xx_l4_per3__timer6,
3251         &dra7xx_l4_per3__timer7,
3252         &dra7xx_l4_per3__timer8,
3253         &dra7xx_l4_per1__timer9,
3254         &dra7xx_l4_per1__timer10,
3255         &dra7xx_l4_per1__timer11,
3256         &dra7xx_l4_per1__uart1,
3257         &dra7xx_l4_per1__uart2,
3258         &dra7xx_l4_per1__uart3,
3259         &dra7xx_l4_per1__uart4,
3260         &dra7xx_l4_per1__uart5,
3261         &dra7xx_l4_per1__uart6,
3262         &dra7xx_l4_per3__usb_otg_ss1,
3263         &dra7xx_l4_per3__usb_otg_ss2,
3264         &dra7xx_l4_per3__usb_otg_ss3,
3265         &dra7xx_l3_main_1__vcp1,
3266         &dra7xx_l4_per2__vcp1,
3267         &dra7xx_l3_main_1__vcp2,
3268         &dra7xx_l4_per2__vcp2,
3269         &dra7xx_l4_wkup__wd_timer2,
3270         NULL,
3271 };
3272
3273 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3274         &dra7xx_l4_per3__usb_otg_ss4,
3275         NULL,
3276 };
3277
3278 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3279         NULL,
3280 };
3281
3282 int __init dra7xx_hwmod_init(void)
3283 {
3284         int ret;
3285
3286         omap_hwmod_init();
3287         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3288
3289         if (!ret && soc_is_dra74x())
3290                 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3291         else if (!ret && soc_is_dra72x())
3292                 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3293
3294         return ret;
3295 }