arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/platform_data/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26
  27 #include "omap_hwmod.h"
  28 #include "omap_hwmod_common_data.h"
  29 #include "cm1_54xx.h"
  30 #include "cm2_54xx.h"
  31 #include "prm54xx.h"
  32 #include "i2c.h"
  33 #include "wd_timer.h"
  34
  35 /* Base offset for all OMAP5 interrupts external to MPUSS */
  36 #define OMAP54XX_IRQ_GIC_START  32
  37
  38 /* Base offset for all OMAP5 dma requests */
  39 #define OMAP54XX_DMA_REQ_START  1
  40
  41
  42 /*
  43  * IP blocks
  44  */
  45
  46 /*
  47  * 'dmm' class
  48  * instance(s): dmm
  49  */
  50 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  51         .name   = "dmm",
  52 };
  53
  54 /* dmm */
  55 static struct omap_hwmod omap54xx_dmm_hwmod = {
  56         .name           = "dmm",
  57         .class          = &omap54xx_dmm_hwmod_class,
  58         .clkdm_name     = "emif_clkdm",
  59         .prcm = {
  60                 .omap4 = {
  61                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  62                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  63                 },
  64         },
  65 };
  66
  67 /*
  68  * 'l3' class
  69  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  70  */
  71 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  72         .name   = "l3",
  73 };
  74
  75 /* l3_instr */
  76 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  77         .name           = "l3_instr",
  78         .class          = &omap54xx_l3_hwmod_class,
  79         .clkdm_name     = "l3instr_clkdm",
  80         .prcm = {
  81                 .omap4 = {
  82                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  83                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  84                         .modulemode   = MODULEMODE_HWCTRL,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_1 */
  90 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  91         .name           = "l3_main_1",
  92         .class          = &omap54xx_l3_hwmod_class,
  93         .clkdm_name     = "l3main1_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /* l3_main_2 */
 103 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 104         .name           = "l3_main_2",
 105         .class          = &omap54xx_l3_hwmod_class,
 106         .clkdm_name     = "l3main2_clkdm",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 110                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 111                 },
 112         },
 113 };
 114
 115 /* l3_main_3 */
 116 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 117         .name           = "l3_main_3",
 118         .class          = &omap54xx_l3_hwmod_class,
 119         .clkdm_name     = "l3instr_clkdm",
 120         .prcm = {
 121                 .omap4 = {
 122                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 123                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 124                         .modulemode   = MODULEMODE_HWCTRL,
 125                 },
 126         },
 127 };
 128
 129 /*
 130  * 'l4' class
 131  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 132  */
 133 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 134         .name   = "l4",
 135 };
 136
 137 /* l4_abe */
 138 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 139         .name           = "l4_abe",
 140         .class          = &omap54xx_l4_hwmod_class,
 141         .clkdm_name     = "abe_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 145                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 146                 },
 147         },
 148 };
 149
 150 /* l4_cfg */
 151 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 152         .name           = "l4_cfg",
 153         .class          = &omap54xx_l4_hwmod_class,
 154         .clkdm_name     = "l4cfg_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /* l4_per */
 164 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 165         .name           = "l4_per",
 166         .class          = &omap54xx_l4_hwmod_class,
 167         .clkdm_name     = "l4per_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 171                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /* l4_wkup */
 177 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 178         .name           = "l4_wkup",
 179         .class          = &omap54xx_l4_hwmod_class,
 180         .clkdm_name     = "wkupaon_clkdm",
 181         .prcm = {
 182                 .omap4 = {
 183                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 184                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 185                 },
 186         },
 187 };
 188
 189 /*
 190  * 'mpu_bus' class
 191  * instance(s): mpu_private
 192  */
 193 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 194         .name   = "mpu_bus",
 195 };
 196
 197 /* mpu_private */
 198 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 199         .name           = "mpu_private",
 200         .class          = &omap54xx_mpu_bus_hwmod_class,
 201         .clkdm_name     = "mpu_clkdm",
 202         .prcm = {
 203                 .omap4 = {
 204                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 205                 },
 206         },
 207 };
 208
 209 /*
 210  * 'counter' class
 211  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 212  */
 213
 214 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 215         .rev_offs       = 0x0000,
 216         .sysc_offs      = 0x0010,
 217         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 218         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 219         .sysc_fields    = &omap_hwmod_sysc_type1,
 220 };
 221
 222 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 223         .name   = "counter",
 224         .sysc   = &omap54xx_counter_sysc,
 225 };
 226
 227 /* counter_32k */
 228 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 229         .name           = "counter_32k",
 230         .class          = &omap54xx_counter_hwmod_class,
 231         .clkdm_name     = "wkupaon_clkdm",
 232         .flags          = HWMOD_SWSUP_SIDLE,
 233         .main_clk       = "wkupaon_iclk_mux",
 234         .prcm = {
 235                 .omap4 = {
 236                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 237                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'dma' class
 244  * dma controller for data exchange between memory to memory (i.e. internal or
 245  * external memory) and gp peripherals to memory or memory to gp peripherals
 246  */
 247
 248 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 249         .rev_offs       = 0x0000,
 250         .sysc_offs      = 0x002c,
 251         .syss_offs      = 0x0028,
 252         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 253                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 254                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 255                            SYSS_HAS_RESET_STATUS),
 256         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 257                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 258         .sysc_fields    = &omap_hwmod_sysc_type1,
 259 };
 260
 261 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 262         .name   = "dma",
 263         .sysc   = &omap54xx_dma_sysc,
 264 };
 265
 266 /* dma dev_attr */
 267 static struct omap_dma_dev_attr dma_dev_attr = {
 268         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 269                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 270         .lch_count      = 32,
 271 };
 272
 273 /* dma_system */
 274 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 275         .name           = "dma_system",
 276         .class          = &omap54xx_dma_hwmod_class,
 277         .clkdm_name     = "dma_clkdm",
 278         .main_clk       = "l3_iclk_div",
 279         .prcm = {
 280                 .omap4 = {
 281                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 282                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 283                 },
 284         },
 285         .dev_attr       = &dma_dev_attr,
 286 };
 287
 288 /*
 289  * 'dmic' class
 290  * digital microphone controller
 291  */
 292
 293 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 294         .rev_offs       = 0x0000,
 295         .sysc_offs      = 0x0010,
 296         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 297                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 298         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 299                            SIDLE_SMART_WKUP),
 300         .sysc_fields    = &omap_hwmod_sysc_type2,
 301 };
 302
 303 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 304         .name   = "dmic",
 305         .sysc   = &omap54xx_dmic_sysc,
 306 };
 307
 308 /* dmic */
 309 static struct omap_hwmod omap54xx_dmic_hwmod = {
 310         .name           = "dmic",
 311         .class          = &omap54xx_dmic_hwmod_class,
 312         .clkdm_name     = "abe_clkdm",
 313         .main_clk       = "dmic_gfclk",
 314         .prcm = {
 315                 .omap4 = {
 316                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 317                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 318                         .modulemode   = MODULEMODE_SWCTRL,
 319                 },
 320         },
 321 };
 322
 323 /*
 324  * 'dss' class
 325  * display sub-system
 326  */
 327 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 328         .rev_offs       = 0x0000,
 329         .syss_offs      = 0x0014,
 330         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 331 };
 332
 333 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 334         .name   = "dss",
 335         .sysc   = &omap54xx_dss_sysc,
 336         .reset  = omap_dss_reset,
 337 };
 338
 339 /* dss */
 340 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 341         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 342         { .role = "sys_clk", .clk = "dss_sys_clk" },
 343         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 344 };
 345
 346 static struct omap_hwmod omap54xx_dss_hwmod = {
 347         .name           = "dss_core",
 348         .class          = &omap54xx_dss_hwmod_class,
 349         .clkdm_name     = "dss_clkdm",
 350         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 351         .main_clk       = "dss_dss_clk",
 352         .prcm = {
 353                 .omap4 = {
 354                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 355                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 356                         .modulemode   = MODULEMODE_SWCTRL,
 357                 },
 358         },
 359         .opt_clks       = dss_opt_clks,
 360         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 361 };
 362
 363 /*
 364  * 'dispc' class
 365  * display controller
 366  */
 367
 368 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 369         .rev_offs       = 0x0000,
 370         .sysc_offs      = 0x0010,
 371         .syss_offs      = 0x0014,
 372         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 373                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 374                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 375                            SYSS_HAS_RESET_STATUS),
 376         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 377                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 378         .sysc_fields    = &omap_hwmod_sysc_type1,
 379 };
 380
 381 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 382         .name   = "dispc",
 383         .sysc   = &omap54xx_dispc_sysc,
 384 };
 385
 386 /* dss_dispc */
 387 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 388         { .role = "sys_clk", .clk = "dss_sys_clk" },
 389 };
 390
 391 /* dss_dispc dev_attr */
 392 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 393         .has_framedonetv_irq    = 1,
 394         .manager_count          = 4,
 395 };
 396
 397 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 398         .name           = "dss_dispc",
 399         .class          = &omap54xx_dispc_hwmod_class,
 400         .clkdm_name     = "dss_clkdm",
 401         .main_clk       = "dss_dss_clk",
 402         .prcm = {
 403                 .omap4 = {
 404                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 405                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 406                 },
 407         },
 408         .opt_clks       = dss_dispc_opt_clks,
 409         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 410         .dev_attr       = &dss_dispc_dev_attr,
 411         .parent_hwmod   = &omap54xx_dss_hwmod,
 412 };
 413
 414 /*
 415  * 'dsi1' class
 416  * display serial interface controller
 417  */
 418
 419 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 420         .rev_offs       = 0x0000,
 421         .sysc_offs      = 0x0010,
 422         .syss_offs      = 0x0014,
 423         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 424                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 425                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 426         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 427         .sysc_fields    = &omap_hwmod_sysc_type1,
 428 };
 429
 430 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 431         .name   = "dsi1",
 432         .sysc   = &omap54xx_dsi1_sysc,
 433 };
 434
 435 /* dss_dsi1_a */
 436 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 437         { .role = "sys_clk", .clk = "dss_sys_clk" },
 438 };
 439
 440 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 441         .name           = "dss_dsi1",
 442         .class          = &omap54xx_dsi1_hwmod_class,
 443         .clkdm_name     = "dss_clkdm",
 444         .main_clk       = "dss_dss_clk",
 445         .prcm = {
 446                 .omap4 = {
 447                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 448                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 449                 },
 450         },
 451         .opt_clks       = dss_dsi1_a_opt_clks,
 452         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 453         .parent_hwmod   = &omap54xx_dss_hwmod,
 454 };
 455
 456 /* dss_dsi1_c */
 457 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 458         { .role = "sys_clk", .clk = "dss_sys_clk" },
 459 };
 460
 461 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 462         .name           = "dss_dsi2",
 463         .class          = &omap54xx_dsi1_hwmod_class,
 464         .clkdm_name     = "dss_clkdm",
 465         .main_clk       = "dss_dss_clk",
 466         .prcm = {
 467                 .omap4 = {
 468                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 469                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 470                 },
 471         },
 472         .opt_clks       = dss_dsi1_c_opt_clks,
 473         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 474         .parent_hwmod   = &omap54xx_dss_hwmod,
 475 };
 476
 477 /*
 478  * 'hdmi' class
 479  * hdmi controller
 480  */
 481
 482 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 483         .rev_offs       = 0x0000,
 484         .sysc_offs      = 0x0010,
 485         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 486                            SYSC_HAS_SOFTRESET),
 487         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 488                            SIDLE_SMART_WKUP),
 489         .sysc_fields    = &omap_hwmod_sysc_type2,
 490 };
 491
 492 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 493         .name   = "hdmi",
 494         .sysc   = &omap54xx_hdmi_sysc,
 495 };
 496
 497 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 498         { .role = "sys_clk", .clk = "dss_sys_clk" },
 499 };
 500
 501 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 502         .name           = "dss_hdmi",
 503         .class          = &omap54xx_hdmi_hwmod_class,
 504         .clkdm_name     = "dss_clkdm",
 505         .main_clk       = "dss_48mhz_clk",
 506         .prcm = {
 507                 .omap4 = {
 508                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 509                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 510                 },
 511         },
 512         .opt_clks       = dss_hdmi_opt_clks,
 513         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 514         .parent_hwmod   = &omap54xx_dss_hwmod,
 515 };
 516
 517 /*
 518  * 'rfbi' class
 519  * remote frame buffer interface
 520  */
 521
 522 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 523         .rev_offs       = 0x0000,
 524         .sysc_offs      = 0x0010,
 525         .syss_offs      = 0x0014,
 526         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 527                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 528         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 529         .sysc_fields    = &omap_hwmod_sysc_type1,
 530 };
 531
 532 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 533         .name   = "rfbi",
 534         .sysc   = &omap54xx_rfbi_sysc,
 535 };
 536
 537 /* dss_rfbi */
 538 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 539         { .role = "ick", .clk = "l3_iclk_div" },
 540 };
 541
 542 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 543         .name           = "dss_rfbi",
 544         .class          = &omap54xx_rfbi_hwmod_class,
 545         .clkdm_name     = "dss_clkdm",
 546         .prcm = {
 547                 .omap4 = {
 548                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 549                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 550                 },
 551         },
 552         .opt_clks       = dss_rfbi_opt_clks,
 553         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 554         .parent_hwmod   = &omap54xx_dss_hwmod,
 555 };
 556
 557 /*
 558  * 'emif' class
 559  * external memory interface no1 (wrapper)
 560  */
 561
 562 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 563         .rev_offs       = 0x0000,
 564 };
 565
 566 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 567         .name   = "emif",
 568         .sysc   = &omap54xx_emif_sysc,
 569 };
 570
 571 /* emif1 */
 572 static struct omap_hwmod omap54xx_emif1_hwmod = {
 573         .name           = "emif1",
 574         .class          = &omap54xx_emif_hwmod_class,
 575         .clkdm_name     = "emif_clkdm",
 576         .flags          = HWMOD_INIT_NO_IDLE,
 577         .main_clk       = "dpll_core_h11x2_ck",
 578         .prcm = {
 579                 .omap4 = {
 580                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 581                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 582                         .modulemode   = MODULEMODE_HWCTRL,
 583                 },
 584         },
 585 };
 586
 587 /* emif2 */
 588 static struct omap_hwmod omap54xx_emif2_hwmod = {
 589         .name           = "emif2",
 590         .class          = &omap54xx_emif_hwmod_class,
 591         .clkdm_name     = "emif_clkdm",
 592         .flags          = HWMOD_INIT_NO_IDLE,
 593         .main_clk       = "dpll_core_h11x2_ck",
 594         .prcm = {
 595                 .omap4 = {
 596                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 597                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 598                         .modulemode   = MODULEMODE_HWCTRL,
 599                 },
 600         },
 601 };
 602
 603 /*
 604  * 'gpio' class
 605  * general purpose io module
 606  */
 607
 608 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 609         .rev_offs       = 0x0000,
 610         .sysc_offs      = 0x0010,
 611         .syss_offs      = 0x0114,
 612         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 613                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 614                            SYSS_HAS_RESET_STATUS),
 615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 616                            SIDLE_SMART_WKUP),
 617         .sysc_fields    = &omap_hwmod_sysc_type1,
 618 };
 619
 620 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 621         .name   = "gpio",
 622         .sysc   = &omap54xx_gpio_sysc,
 623         .rev    = 2,
 624 };
 625
 626 /* gpio1 */
 627 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 628         { .role = "dbclk", .clk = "gpio1_dbclk" },
 629 };
 630
 631 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 632         .name           = "gpio1",
 633         .class          = &omap54xx_gpio_hwmod_class,
 634         .clkdm_name     = "wkupaon_clkdm",
 635         .main_clk       = "wkupaon_iclk_mux",
 636         .prcm = {
 637                 .omap4 = {
 638                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 639                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 640                         .modulemode   = MODULEMODE_HWCTRL,
 641                 },
 642         },
 643         .opt_clks       = gpio1_opt_clks,
 644         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 645 };
 646
 647 /* gpio2 */
 648 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 649         { .role = "dbclk", .clk = "gpio2_dbclk" },
 650 };
 651
 652 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 653         .name           = "gpio2",
 654         .class          = &omap54xx_gpio_hwmod_class,
 655         .clkdm_name     = "l4per_clkdm",
 656         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 657         .main_clk       = "l4_root_clk_div",
 658         .prcm = {
 659                 .omap4 = {
 660                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 661                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665         .opt_clks       = gpio2_opt_clks,
 666         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 667 };
 668
 669 /* gpio3 */
 670 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 671         { .role = "dbclk", .clk = "gpio3_dbclk" },
 672 };
 673
 674 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 675         .name           = "gpio3",
 676         .class          = &omap54xx_gpio_hwmod_class,
 677         .clkdm_name     = "l4per_clkdm",
 678         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 679         .main_clk       = "l4_root_clk_div",
 680         .prcm = {
 681                 .omap4 = {
 682                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 683                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 684                         .modulemode   = MODULEMODE_HWCTRL,
 685                 },
 686         },
 687         .opt_clks       = gpio3_opt_clks,
 688         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 689 };
 690
 691 /* gpio4 */
 692 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 693         { .role = "dbclk", .clk = "gpio4_dbclk" },
 694 };
 695
 696 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 697         .name           = "gpio4",
 698         .class          = &omap54xx_gpio_hwmod_class,
 699         .clkdm_name     = "l4per_clkdm",
 700         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 701         .main_clk       = "l4_root_clk_div",
 702         .prcm = {
 703                 .omap4 = {
 704                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 705                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 706                         .modulemode   = MODULEMODE_HWCTRL,
 707                 },
 708         },
 709         .opt_clks       = gpio4_opt_clks,
 710         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 711 };
 712
 713 /* gpio5 */
 714 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 715         { .role = "dbclk", .clk = "gpio5_dbclk" },
 716 };
 717
 718 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 719         .name           = "gpio5",
 720         .class          = &omap54xx_gpio_hwmod_class,
 721         .clkdm_name     = "l4per_clkdm",
 722         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 723         .main_clk       = "l4_root_clk_div",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 728                         .modulemode   = MODULEMODE_HWCTRL,
 729                 },
 730         },
 731         .opt_clks       = gpio5_opt_clks,
 732         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 733 };
 734
 735 /* gpio6 */
 736 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 737         { .role = "dbclk", .clk = "gpio6_dbclk" },
 738 };
 739
 740 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 741         .name           = "gpio6",
 742         .class          = &omap54xx_gpio_hwmod_class,
 743         .clkdm_name     = "l4per_clkdm",
 744         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 745         .main_clk       = "l4_root_clk_div",
 746         .prcm = {
 747                 .omap4 = {
 748                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 749                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 750                         .modulemode   = MODULEMODE_HWCTRL,
 751                 },
 752         },
 753         .opt_clks       = gpio6_opt_clks,
 754         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 755 };
 756
 757 /* gpio7 */
 758 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 759         { .role = "dbclk", .clk = "gpio7_dbclk" },
 760 };
 761
 762 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 763         .name           = "gpio7",
 764         .class          = &omap54xx_gpio_hwmod_class,
 765         .clkdm_name     = "l4per_clkdm",
 766         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 767         .main_clk       = "l4_root_clk_div",
 768         .prcm = {
 769                 .omap4 = {
 770                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 771                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 772                         .modulemode   = MODULEMODE_HWCTRL,
 773                 },
 774         },
 775         .opt_clks       = gpio7_opt_clks,
 776         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 777 };
 778
 779 /* gpio8 */
 780 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 781         { .role = "dbclk", .clk = "gpio8_dbclk" },
 782 };
 783
 784 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 785         .name           = "gpio8",
 786         .class          = &omap54xx_gpio_hwmod_class,
 787         .clkdm_name     = "l4per_clkdm",
 788         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 789         .main_clk       = "l4_root_clk_div",
 790         .prcm = {
 791                 .omap4 = {
 792                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 793                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 794                         .modulemode   = MODULEMODE_HWCTRL,
 795                 },
 796         },
 797         .opt_clks       = gpio8_opt_clks,
 798         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 799 };
 800
 801 /*
 802  * 'i2c' class
 803  * multimaster high-speed i2c controller
 804  */
 805
 806 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 807         .sysc_offs      = 0x0010,
 808         .syss_offs      = 0x0090,
 809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 810                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 811                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 813                            SIDLE_SMART_WKUP),
 814         .sysc_fields    = &omap_hwmod_sysc_type1,
 815 };
 816
 817 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 818         .name   = "i2c",
 819         .sysc   = &omap54xx_i2c_sysc,
 820         .reset  = &omap_i2c_reset,
 821         .rev    = OMAP_I2C_IP_VERSION_2,
 822 };
 823
 824 /* i2c1 */
 825 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 826         .name           = "i2c1",
 827         .class          = &omap54xx_i2c_hwmod_class,
 828         .clkdm_name     = "l4per_clkdm",
 829         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 830         .main_clk       = "func_96m_fclk",
 831         .prcm = {
 832                 .omap4 = {
 833                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 834                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 835                         .modulemode   = MODULEMODE_SWCTRL,
 836                 },
 837         },
 838 };
 839
 840 /* i2c2 */
 841 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 842         .name           = "i2c2",
 843         .class          = &omap54xx_i2c_hwmod_class,
 844         .clkdm_name     = "l4per_clkdm",
 845         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 846         .main_clk       = "func_96m_fclk",
 847         .prcm = {
 848                 .omap4 = {
 849                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 850                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 851                         .modulemode   = MODULEMODE_SWCTRL,
 852                 },
 853         },
 854 };
 855
 856 /* i2c3 */
 857 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 858         .name           = "i2c3",
 859         .class          = &omap54xx_i2c_hwmod_class,
 860         .clkdm_name     = "l4per_clkdm",
 861         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 862         .main_clk       = "func_96m_fclk",
 863         .prcm = {
 864                 .omap4 = {
 865                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 866                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 867                         .modulemode   = MODULEMODE_SWCTRL,
 868                 },
 869         },
 870 };
 871
 872 /* i2c4 */
 873 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 874         .name           = "i2c4",
 875         .class          = &omap54xx_i2c_hwmod_class,
 876         .clkdm_name     = "l4per_clkdm",
 877         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 878         .main_clk       = "func_96m_fclk",
 879         .prcm = {
 880                 .omap4 = {
 881                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 882                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 883                         .modulemode   = MODULEMODE_SWCTRL,
 884                 },
 885         },
 886 };
 887
 888 /* i2c5 */
 889 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 890         .name           = "i2c5",
 891         .class          = &omap54xx_i2c_hwmod_class,
 892         .clkdm_name     = "l4per_clkdm",
 893         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 894         .main_clk       = "func_96m_fclk",
 895         .prcm = {
 896                 .omap4 = {
 897                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 898                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 899                         .modulemode   = MODULEMODE_SWCTRL,
 900                 },
 901         },
 902 };
 903
 904 /*
 905  * 'kbd' class
 906  * keyboard controller
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 913                            SYSC_HAS_SOFTRESET),
 914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 915         .sysc_fields    = &omap_hwmod_sysc_type1,
 916 };
 917
 918 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 919         .name   = "kbd",
 920         .sysc   = &omap54xx_kbd_sysc,
 921 };
 922
 923 /* kbd */
 924 static struct omap_hwmod omap54xx_kbd_hwmod = {
 925         .name           = "kbd",
 926         .class          = &omap54xx_kbd_hwmod_class,
 927         .clkdm_name     = "wkupaon_clkdm",
 928         .main_clk       = "sys_32k_ck",
 929         .prcm = {
 930                 .omap4 = {
 931                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 932                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 933                         .modulemode   = MODULEMODE_SWCTRL,
 934                 },
 935         },
 936 };
 937
 938 /*
 939  * 'mailbox' class
 940  * mailbox module allowing communication between the on-chip processors using a
 941  * queued mailbox-interrupt mechanism.
 942  */
 943
 944 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 945         .rev_offs       = 0x0000,
 946         .sysc_offs      = 0x0010,
 947         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 948                            SYSC_HAS_SOFTRESET),
 949         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 950         .sysc_fields    = &omap_hwmod_sysc_type2,
 951 };
 952
 953 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 954         .name   = "mailbox",
 955         .sysc   = &omap54xx_mailbox_sysc,
 956 };
 957
 958 /* mailbox */
 959 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 960         .name           = "mailbox",
 961         .class          = &omap54xx_mailbox_hwmod_class,
 962         .clkdm_name     = "l4cfg_clkdm",
 963         .prcm = {
 964                 .omap4 = {
 965                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
 966                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
 967                 },
 968         },
 969 };
 970
 971 /*
 972  * 'mcbsp' class
 973  * multi channel buffered serial port controller
 974  */
 975
 976 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
 977         .sysc_offs      = 0x008c,
 978         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 979                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 980         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 981         .sysc_fields    = &omap_hwmod_sysc_type1,
 982 };
 983
 984 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
 985         .name   = "mcbsp",
 986         .sysc   = &omap54xx_mcbsp_sysc,
 987 };
 988
 989 /* mcbsp1 */
 990 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
 991         { .role = "pad_fck", .clk = "pad_clks_ck" },
 992         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
 993 };
 994
 995 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
 996         .name           = "mcbsp1",
 997         .class          = &omap54xx_mcbsp_hwmod_class,
 998         .clkdm_name     = "abe_clkdm",
 999         .main_clk       = "mcbsp1_gfclk",
1000         .prcm = {
1001                 .omap4 = {
1002                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1003                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1004                         .modulemode   = MODULEMODE_SWCTRL,
1005                 },
1006         },
1007         .opt_clks       = mcbsp1_opt_clks,
1008         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1009 };
1010
1011 /* mcbsp2 */
1012 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1013         { .role = "pad_fck", .clk = "pad_clks_ck" },
1014         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1015 };
1016
1017 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1018         .name           = "mcbsp2",
1019         .class          = &omap54xx_mcbsp_hwmod_class,
1020         .clkdm_name     = "abe_clkdm",
1021         .main_clk       = "mcbsp2_gfclk",
1022         .prcm = {
1023                 .omap4 = {
1024                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1025                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1026                         .modulemode   = MODULEMODE_SWCTRL,
1027                 },
1028         },
1029         .opt_clks       = mcbsp2_opt_clks,
1030         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1031 };
1032
1033 /* mcbsp3 */
1034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1035         { .role = "pad_fck", .clk = "pad_clks_ck" },
1036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1037 };
1038
1039 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1040         .name           = "mcbsp3",
1041         .class          = &omap54xx_mcbsp_hwmod_class,
1042         .clkdm_name     = "abe_clkdm",
1043         .main_clk       = "mcbsp3_gfclk",
1044         .prcm = {
1045                 .omap4 = {
1046                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1047                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1048                         .modulemode   = MODULEMODE_SWCTRL,
1049                 },
1050         },
1051         .opt_clks       = mcbsp3_opt_clks,
1052         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1053 };
1054
1055 /*
1056  * 'mcpdm' class
1057  * multi channel pdm controller (proprietary interface with phoenix power
1058  * ic)
1059  */
1060
1061 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1062         .rev_offs       = 0x0000,
1063         .sysc_offs      = 0x0010,
1064         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1065                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1067                            SIDLE_SMART_WKUP),
1068         .sysc_fields    = &omap_hwmod_sysc_type2,
1069 };
1070
1071 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1072         .name   = "mcpdm",
1073         .sysc   = &omap54xx_mcpdm_sysc,
1074 };
1075
1076 /* mcpdm */
1077 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1078         .name           = "mcpdm",
1079         .class          = &omap54xx_mcpdm_hwmod_class,
1080         .clkdm_name     = "abe_clkdm",
1081         /*
1082          * It's suspected that the McPDM requires an off-chip main
1083          * functional clock, controlled via I2C.  This IP block is
1084          * currently reset very early during boot, before I2C is
1085          * available, so it doesn't seem that we have any choice in
1086          * the kernel other than to avoid resetting it.  XXX This is
1087          * really a hardware issue workaround: every IP block should
1088          * be able to source its main functional clock from either
1089          * on-chip or off-chip sources.  McPDM seems to be the only
1090          * current exception.
1091          */
1092
1093         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1094         .main_clk       = "pad_clks_ck",
1095         .prcm = {
1096                 .omap4 = {
1097                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1098                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1099                         .modulemode   = MODULEMODE_SWCTRL,
1100                 },
1101         },
1102 };
1103
1104 /*
1105  * 'mcspi' class
1106  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1107  * bus
1108  */
1109
1110 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1111         .rev_offs       = 0x0000,
1112         .sysc_offs      = 0x0010,
1113         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1114                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1115         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1116                            SIDLE_SMART_WKUP),
1117         .sysc_fields    = &omap_hwmod_sysc_type2,
1118 };
1119
1120 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1121         .name   = "mcspi",
1122         .sysc   = &omap54xx_mcspi_sysc,
1123 };
1124
1125 /* mcspi1 */
1126 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1127         .name           = "mcspi1",
1128         .class          = &omap54xx_mcspi_hwmod_class,
1129         .clkdm_name     = "l4per_clkdm",
1130         .main_clk       = "func_48m_fclk",
1131         .prcm = {
1132                 .omap4 = {
1133                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1134                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1135                         .modulemode   = MODULEMODE_SWCTRL,
1136                 },
1137         },
1138 };
1139
1140 /* mcspi2 */
1141 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1142         .name           = "mcspi2",
1143         .class          = &omap54xx_mcspi_hwmod_class,
1144         .clkdm_name     = "l4per_clkdm",
1145         .main_clk       = "func_48m_fclk",
1146         .prcm = {
1147                 .omap4 = {
1148                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1149                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1150                         .modulemode   = MODULEMODE_SWCTRL,
1151                 },
1152         },
1153 };
1154
1155 /* mcspi3 */
1156 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1157         .name           = "mcspi3",
1158         .class          = &omap54xx_mcspi_hwmod_class,
1159         .clkdm_name     = "l4per_clkdm",
1160         .main_clk       = "func_48m_fclk",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1164                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_SWCTRL,
1166                 },
1167         },
1168 };
1169
1170 /* mcspi4 */
1171 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1172         .name           = "mcspi4",
1173         .class          = &omap54xx_mcspi_hwmod_class,
1174         .clkdm_name     = "l4per_clkdm",
1175         .main_clk       = "func_48m_fclk",
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1179                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1180                         .modulemode   = MODULEMODE_SWCTRL,
1181                 },
1182         },
1183 };
1184
1185 /*
1186  * 'mmc' class
1187  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1188  */
1189
1190 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1191         .rev_offs       = 0x0000,
1192         .sysc_offs      = 0x0010,
1193         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1194                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1195                            SYSC_HAS_SOFTRESET),
1196         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1197                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1198                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1199         .sysc_fields    = &omap_hwmod_sysc_type2,
1200 };
1201
1202 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1203         .name   = "mmc",
1204         .sysc   = &omap54xx_mmc_sysc,
1205 };
1206
1207 /* mmc1 */
1208 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1209         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1210 };
1211
1212 /* mmc1 dev_attr */
1213 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1214         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1215 };
1216
1217 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1218         .name           = "mmc1",
1219         .class          = &omap54xx_mmc_hwmod_class,
1220         .clkdm_name     = "l3init_clkdm",
1221         .main_clk       = "mmc1_fclk",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1225                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1226                         .modulemode   = MODULEMODE_SWCTRL,
1227                 },
1228         },
1229         .opt_clks       = mmc1_opt_clks,
1230         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1231         .dev_attr       = &mmc1_dev_attr,
1232 };
1233
1234 /* mmc2 */
1235 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1236         .name           = "mmc2",
1237         .class          = &omap54xx_mmc_hwmod_class,
1238         .clkdm_name     = "l3init_clkdm",
1239         .main_clk       = "mmc2_fclk",
1240         .prcm = {
1241                 .omap4 = {
1242                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1243                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1244                         .modulemode   = MODULEMODE_SWCTRL,
1245                 },
1246         },
1247 };
1248
1249 /* mmc3 */
1250 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1251         .name           = "mmc3",
1252         .class          = &omap54xx_mmc_hwmod_class,
1253         .clkdm_name     = "l4per_clkdm",
1254         .main_clk       = "func_48m_fclk",
1255         .prcm = {
1256                 .omap4 = {
1257                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1258                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1259                         .modulemode   = MODULEMODE_SWCTRL,
1260                 },
1261         },
1262 };
1263
1264 /* mmc4 */
1265 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1266         .name           = "mmc4",
1267         .class          = &omap54xx_mmc_hwmod_class,
1268         .clkdm_name     = "l4per_clkdm",
1269         .main_clk       = "func_48m_fclk",
1270         .prcm = {
1271                 .omap4 = {
1272                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1273                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1274                         .modulemode   = MODULEMODE_SWCTRL,
1275                 },
1276         },
1277 };
1278
1279 /* mmc5 */
1280 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1281         .name           = "mmc5",
1282         .class          = &omap54xx_mmc_hwmod_class,
1283         .clkdm_name     = "l4per_clkdm",
1284         .main_clk       = "func_96m_fclk",
1285         .prcm = {
1286                 .omap4 = {
1287                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1288                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1289                         .modulemode   = MODULEMODE_SWCTRL,
1290                 },
1291         },
1292 };
1293
1294 /*
1295  * 'mmu' class
1296  * The memory management unit performs virtual to physical address translation
1297  * for its requestors.
1298  */
1299
1300 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1301         .rev_offs       = 0x0000,
1302         .sysc_offs      = 0x0010,
1303         .syss_offs      = 0x0014,
1304         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1305                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1306                            SYSS_HAS_RESET_STATUS),
1307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1308         .sysc_fields    = &omap_hwmod_sysc_type1,
1309 };
1310
1311 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1312         .name = "mmu",
1313         .sysc = &omap54xx_mmu_sysc,
1314 };
1315
1316 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1317         { .name = "mmu_cache", .rst_shift = 1 },
1318 };
1319
1320 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1321         .name           = "mmu_dsp",
1322         .class          = &omap54xx_mmu_hwmod_class,
1323         .clkdm_name     = "dsp_clkdm",
1324         .rst_lines      = omap54xx_mmu_dsp_resets,
1325         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1326         .main_clk       = "dpll_iva_h11x2_ck",
1327         .prcm = {
1328                 .omap4 = {
1329                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1330                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1331                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1332                         .modulemode   = MODULEMODE_HWCTRL,
1333                 },
1334         },
1335 };
1336
1337 /* mmu ipu */
1338 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1339         { .name = "mmu_cache", .rst_shift = 2 },
1340 };
1341
1342 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1343         .name           = "mmu_ipu",
1344         .class          = &omap54xx_mmu_hwmod_class,
1345         .clkdm_name     = "ipu_clkdm",
1346         .rst_lines      = omap54xx_mmu_ipu_resets,
1347         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1348         .main_clk       = "dpll_core_h22x2_ck",
1349         .prcm = {
1350                 .omap4 = {
1351                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1352                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1353                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1354                         .modulemode   = MODULEMODE_HWCTRL,
1355                 },
1356         },
1357 };
1358
1359 /*
1360  * 'mpu' class
1361  * mpu sub-system
1362  */
1363
1364 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1365         .name   = "mpu",
1366 };
1367
1368 /* mpu */
1369 static struct omap_hwmod omap54xx_mpu_hwmod = {
1370         .name           = "mpu",
1371         .class          = &omap54xx_mpu_hwmod_class,
1372         .clkdm_name     = "mpu_clkdm",
1373         .flags          = HWMOD_INIT_NO_IDLE,
1374         .main_clk       = "dpll_mpu_m2_ck",
1375         .prcm = {
1376                 .omap4 = {
1377                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1378                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1379                 },
1380         },
1381 };
1382
1383 /*
1384  * 'spinlock' class
1385  * spinlock provides hardware assistance for synchronizing the processes
1386  * running on multiple processors
1387  */
1388
1389 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1390         .rev_offs       = 0x0000,
1391         .sysc_offs      = 0x0010,
1392         .syss_offs      = 0x0014,
1393         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1394                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1395                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1397         .sysc_fields    = &omap_hwmod_sysc_type1,
1398 };
1399
1400 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1401         .name   = "spinlock",
1402         .sysc   = &omap54xx_spinlock_sysc,
1403 };
1404
1405 /* spinlock */
1406 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1407         .name           = "spinlock",
1408         .class          = &omap54xx_spinlock_hwmod_class,
1409         .clkdm_name     = "l4cfg_clkdm",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'ocp2scp' class
1420  * bridge to transform ocp interface protocol to scp (serial control port)
1421  * protocol
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0010,
1427         .syss_offs      = 0x0014,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1429                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1430         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1431         .sysc_fields    = &omap_hwmod_sysc_type1,
1432 };
1433
1434 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1435         .name   = "ocp2scp",
1436         .sysc   = &omap54xx_ocp2scp_sysc,
1437 };
1438
1439 /* ocp2scp1 */
1440 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1441         .name           = "ocp2scp1",
1442         .class          = &omap54xx_ocp2scp_hwmod_class,
1443         .clkdm_name     = "l3init_clkdm",
1444         .main_clk       = "l4_root_clk_div",
1445         .prcm = {
1446                 .omap4 = {
1447                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1448                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1449                         .modulemode   = MODULEMODE_HWCTRL,
1450                 },
1451         },
1452 };
1453
1454 /*
1455  * 'timer' class
1456  * general purpose timer module with accurate 1ms tick
1457  * This class contains several variants: ['timer_1ms', 'timer']
1458  */
1459
1460 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1461         .rev_offs       = 0x0000,
1462         .sysc_offs      = 0x0010,
1463         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1464                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1465         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1466                            SIDLE_SMART_WKUP),
1467         .sysc_fields    = &omap_hwmod_sysc_type2,
1468 };
1469
1470 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1471         .name   = "timer",
1472         .sysc   = &omap54xx_timer_1ms_sysc,
1473 };
1474
1475 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1476         .rev_offs       = 0x0000,
1477         .sysc_offs      = 0x0010,
1478         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1479                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1481                            SIDLE_SMART_WKUP),
1482         .sysc_fields    = &omap_hwmod_sysc_type2,
1483 };
1484
1485 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1486         .name   = "timer",
1487         .sysc   = &omap54xx_timer_sysc,
1488 };
1489
1490 /* timer1 */
1491 static struct omap_hwmod omap54xx_timer1_hwmod = {
1492         .name           = "timer1",
1493         .class          = &omap54xx_timer_1ms_hwmod_class,
1494         .clkdm_name     = "wkupaon_clkdm",
1495         .main_clk       = "timer1_gfclk_mux",
1496         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1500                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_SWCTRL,
1502                 },
1503         },
1504 };
1505
1506 /* timer2 */
1507 static struct omap_hwmod omap54xx_timer2_hwmod = {
1508         .name           = "timer2",
1509         .class          = &omap54xx_timer_1ms_hwmod_class,
1510         .clkdm_name     = "l4per_clkdm",
1511         .main_clk       = "timer2_gfclk_mux",
1512         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1513         .prcm = {
1514                 .omap4 = {
1515                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1516                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1517                         .modulemode   = MODULEMODE_SWCTRL,
1518                 },
1519         },
1520 };
1521
1522 /* timer3 */
1523 static struct omap_hwmod omap54xx_timer3_hwmod = {
1524         .name           = "timer3",
1525         .class          = &omap54xx_timer_hwmod_class,
1526         .clkdm_name     = "l4per_clkdm",
1527         .main_clk       = "timer3_gfclk_mux",
1528         .prcm = {
1529                 .omap4 = {
1530                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1531                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1532                         .modulemode   = MODULEMODE_SWCTRL,
1533                 },
1534         },
1535 };
1536
1537 /* timer4 */
1538 static struct omap_hwmod omap54xx_timer4_hwmod = {
1539         .name           = "timer4",
1540         .class          = &omap54xx_timer_hwmod_class,
1541         .clkdm_name     = "l4per_clkdm",
1542         .main_clk       = "timer4_gfclk_mux",
1543         .prcm = {
1544                 .omap4 = {
1545                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1546                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1547                         .modulemode   = MODULEMODE_SWCTRL,
1548                 },
1549         },
1550 };
1551
1552 /* timer5 */
1553 static struct omap_hwmod omap54xx_timer5_hwmod = {
1554         .name           = "timer5",
1555         .class          = &omap54xx_timer_hwmod_class,
1556         .clkdm_name     = "abe_clkdm",
1557         .main_clk       = "timer5_gfclk_mux",
1558         .prcm = {
1559                 .omap4 = {
1560                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1561                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1562                         .modulemode   = MODULEMODE_SWCTRL,
1563                 },
1564         },
1565 };
1566
1567 /* timer6 */
1568 static struct omap_hwmod omap54xx_timer6_hwmod = {
1569         .name           = "timer6",
1570         .class          = &omap54xx_timer_hwmod_class,
1571         .clkdm_name     = "abe_clkdm",
1572         .main_clk       = "timer6_gfclk_mux",
1573         .prcm = {
1574                 .omap4 = {
1575                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1576                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1577                         .modulemode   = MODULEMODE_SWCTRL,
1578                 },
1579         },
1580 };
1581
1582 /* timer7 */
1583 static struct omap_hwmod omap54xx_timer7_hwmod = {
1584         .name           = "timer7",
1585         .class          = &omap54xx_timer_hwmod_class,
1586         .clkdm_name     = "abe_clkdm",
1587         .main_clk       = "timer7_gfclk_mux",
1588         .prcm = {
1589                 .omap4 = {
1590                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1591                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1592                         .modulemode   = MODULEMODE_SWCTRL,
1593                 },
1594         },
1595 };
1596
1597 /* timer8 */
1598 static struct omap_hwmod omap54xx_timer8_hwmod = {
1599         .name           = "timer8",
1600         .class          = &omap54xx_timer_hwmod_class,
1601         .clkdm_name     = "abe_clkdm",
1602         .main_clk       = "timer8_gfclk_mux",
1603         .prcm = {
1604                 .omap4 = {
1605                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1606                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1607                         .modulemode   = MODULEMODE_SWCTRL,
1608                 },
1609         },
1610 };
1611
1612 /* timer9 */
1613 static struct omap_hwmod omap54xx_timer9_hwmod = {
1614         .name           = "timer9",
1615         .class          = &omap54xx_timer_hwmod_class,
1616         .clkdm_name     = "l4per_clkdm",
1617         .main_clk       = "timer9_gfclk_mux",
1618         .prcm = {
1619                 .omap4 = {
1620                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1621                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1622                         .modulemode   = MODULEMODE_SWCTRL,
1623                 },
1624         },
1625 };
1626
1627 /* timer10 */
1628 static struct omap_hwmod omap54xx_timer10_hwmod = {
1629         .name           = "timer10",
1630         .class          = &omap54xx_timer_1ms_hwmod_class,
1631         .clkdm_name     = "l4per_clkdm",
1632         .main_clk       = "timer10_gfclk_mux",
1633         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1634         .prcm = {
1635                 .omap4 = {
1636                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1637                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1638                         .modulemode   = MODULEMODE_SWCTRL,
1639                 },
1640         },
1641 };
1642
1643 /* timer11 */
1644 static struct omap_hwmod omap54xx_timer11_hwmod = {
1645         .name           = "timer11",
1646         .class          = &omap54xx_timer_hwmod_class,
1647         .clkdm_name     = "l4per_clkdm",
1648         .main_clk       = "timer11_gfclk_mux",
1649         .prcm = {
1650                 .omap4 = {
1651                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1652                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1653                         .modulemode   = MODULEMODE_SWCTRL,
1654                 },
1655         },
1656 };
1657
1658 /*
1659  * 'uart' class
1660  * universal asynchronous receiver/transmitter (uart)
1661  */
1662
1663 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1664         .rev_offs       = 0x0050,
1665         .sysc_offs      = 0x0054,
1666         .syss_offs      = 0x0058,
1667         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1668                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1669                            SYSS_HAS_RESET_STATUS),
1670         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1671                            SIDLE_SMART_WKUP),
1672         .sysc_fields    = &omap_hwmod_sysc_type1,
1673 };
1674
1675 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1676         .name   = "uart",
1677         .sysc   = &omap54xx_uart_sysc,
1678 };
1679
1680 /* uart1 */
1681 static struct omap_hwmod omap54xx_uart1_hwmod = {
1682         .name           = "uart1",
1683         .class          = &omap54xx_uart_hwmod_class,
1684         .clkdm_name     = "l4per_clkdm",
1685         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1686         .main_clk       = "func_48m_fclk",
1687         .prcm = {
1688                 .omap4 = {
1689                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1690                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1691                         .modulemode   = MODULEMODE_SWCTRL,
1692                 },
1693         },
1694 };
1695
1696 /* uart2 */
1697 static struct omap_hwmod omap54xx_uart2_hwmod = {
1698         .name           = "uart2",
1699         .class          = &omap54xx_uart_hwmod_class,
1700         .clkdm_name     = "l4per_clkdm",
1701         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1702         .main_clk       = "func_48m_fclk",
1703         .prcm = {
1704                 .omap4 = {
1705                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1706                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1707                         .modulemode   = MODULEMODE_SWCTRL,
1708                 },
1709         },
1710 };
1711
1712 /* uart3 */
1713 static struct omap_hwmod omap54xx_uart3_hwmod = {
1714         .name           = "uart3",
1715         .class          = &omap54xx_uart_hwmod_class,
1716         .clkdm_name     = "l4per_clkdm",
1717         .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1718         .main_clk       = "func_48m_fclk",
1719         .prcm = {
1720                 .omap4 = {
1721                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1722                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1723                         .modulemode   = MODULEMODE_SWCTRL,
1724                 },
1725         },
1726 };
1727
1728 /* uart4 */
1729 static struct omap_hwmod omap54xx_uart4_hwmod = {
1730         .name           = "uart4",
1731         .class          = &omap54xx_uart_hwmod_class,
1732         .clkdm_name     = "l4per_clkdm",
1733         .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1734         .main_clk       = "func_48m_fclk",
1735         .prcm = {
1736                 .omap4 = {
1737                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1738                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1739                         .modulemode   = MODULEMODE_SWCTRL,
1740                 },
1741         },
1742 };
1743
1744 /* uart5 */
1745 static struct omap_hwmod omap54xx_uart5_hwmod = {
1746         .name           = "uart5",
1747         .class          = &omap54xx_uart_hwmod_class,
1748         .clkdm_name     = "l4per_clkdm",
1749         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1750         .main_clk       = "func_48m_fclk",
1751         .prcm = {
1752                 .omap4 = {
1753                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1754                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_SWCTRL,
1756                 },
1757         },
1758 };
1759
1760 /* uart6 */
1761 static struct omap_hwmod omap54xx_uart6_hwmod = {
1762         .name           = "uart6",
1763         .class          = &omap54xx_uart_hwmod_class,
1764         .clkdm_name     = "l4per_clkdm",
1765         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1766         .main_clk       = "func_48m_fclk",
1767         .prcm = {
1768                 .omap4 = {
1769                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1770                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1771                         .modulemode   = MODULEMODE_SWCTRL,
1772                 },
1773         },
1774 };
1775
1776 /*
1777  * 'usb_host_hs' class
1778  * high-speed multi-port usb host controller
1779  */
1780
1781 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1782         .rev_offs       = 0x0000,
1783         .sysc_offs      = 0x0010,
1784         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1785                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1786         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1787                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1788                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1789         .sysc_fields    = &omap_hwmod_sysc_type2,
1790 };
1791
1792 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1793         .name   = "usb_host_hs",
1794         .sysc   = &omap54xx_usb_host_hs_sysc,
1795 };
1796
1797 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1798         .name           = "usb_host_hs",
1799         .class          = &omap54xx_usb_host_hs_hwmod_class,
1800         .clkdm_name     = "l3init_clkdm",
1801         /*
1802          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1803          * id: i660
1804          *
1805          * Description:
1806          * In the following configuration :
1807          * - USBHOST module is set to smart-idle mode
1808          * - PRCM asserts idle_req to the USBHOST module ( This typically
1809          *   happens when the system is going to a low power mode : all ports
1810          *   have been suspended, the master part of the USBHOST module has
1811          *   entered the standby state, and SW has cut the functional clocks)
1812          * - an USBHOST interrupt occurs before the module is able to answer
1813          *   idle_ack, typically a remote wakeup IRQ.
1814          * Then the USB HOST module will enter a deadlock situation where it
1815          * is no more accessible nor functional.
1816          *
1817          * Workaround:
1818          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1819          */
1820
1821         /*
1822          * Errata: USB host EHCI may stall when entering smart-standby mode
1823          * Id: i571
1824          *
1825          * Description:
1826          * When the USBHOST module is set to smart-standby mode, and when it is
1827          * ready to enter the standby state (i.e. all ports are suspended and
1828          * all attached devices are in suspend mode), then it can wrongly assert
1829          * the Mstandby signal too early while there are still some residual OCP
1830          * transactions ongoing. If this condition occurs, the internal state
1831          * machine may go to an undefined state and the USB link may be stuck
1832          * upon the next resume.
1833          *
1834          * Workaround:
1835          * Don't use smart standby; use only force standby,
1836          * hence HWMOD_SWSUP_MSTANDBY
1837          */
1838
1839         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1840         .main_clk       = "l3init_60m_fclk",
1841         .prcm = {
1842                 .omap4 = {
1843                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1844                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1845                         .modulemode   = MODULEMODE_SWCTRL,
1846                 },
1847         },
1848 };
1849
1850 /*
1851  * 'usb_tll_hs' class
1852  * usb_tll_hs module is the adapter on the usb_host_hs ports
1853  */
1854
1855 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1856         .rev_offs       = 0x0000,
1857         .sysc_offs      = 0x0010,
1858         .syss_offs      = 0x0014,
1859         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1860                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1861                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1862         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1863         .sysc_fields    = &omap_hwmod_sysc_type1,
1864 };
1865
1866 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1867         .name   = "usb_tll_hs",
1868         .sysc   = &omap54xx_usb_tll_hs_sysc,
1869 };
1870
1871 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1872         .name           = "usb_tll_hs",
1873         .class          = &omap54xx_usb_tll_hs_hwmod_class,
1874         .clkdm_name     = "l3init_clkdm",
1875         .main_clk       = "l4_root_clk_div",
1876         .prcm = {
1877                 .omap4 = {
1878                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1879                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1880                         .modulemode   = MODULEMODE_HWCTRL,
1881                 },
1882         },
1883 };
1884
1885 /*
1886  * 'usb_otg_ss' class
1887  * 2.0 super speed (usb_otg_ss) controller
1888  */
1889
1890 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1891         .rev_offs       = 0x0000,
1892         .sysc_offs      = 0x0010,
1893         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1894                            SYSC_HAS_SIDLEMODE),
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1897                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1898         .sysc_fields    = &omap_hwmod_sysc_type2,
1899 };
1900
1901 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1902         .name   = "usb_otg_ss",
1903         .sysc   = &omap54xx_usb_otg_ss_sysc,
1904 };
1905
1906 /* usb_otg_ss */
1907 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1908         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1909 };
1910
1911 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1912         .name           = "usb_otg_ss",
1913         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1914         .clkdm_name     = "l3init_clkdm",
1915         .flags          = HWMOD_SWSUP_SIDLE,
1916         .main_clk       = "dpll_core_h13x2_ck",
1917         .prcm = {
1918                 .omap4 = {
1919                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1920                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1921                         .modulemode   = MODULEMODE_HWCTRL,
1922                 },
1923         },
1924         .opt_clks       = usb_otg_ss_opt_clks,
1925         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1926 };
1927
1928 /*
1929  * 'wd_timer' class
1930  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1931  * overflow condition
1932  */
1933
1934 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1935         .rev_offs       = 0x0000,
1936         .sysc_offs      = 0x0010,
1937         .syss_offs      = 0x0014,
1938         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1939                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1940         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1941                            SIDLE_SMART_WKUP),
1942         .sysc_fields    = &omap_hwmod_sysc_type1,
1943 };
1944
1945 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1946         .name           = "wd_timer",
1947         .sysc           = &omap54xx_wd_timer_sysc,
1948         .pre_shutdown   = &omap2_wd_timer_disable,
1949 };
1950
1951 /* wd_timer2 */
1952 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1953         .name           = "wd_timer2",
1954         .class          = &omap54xx_wd_timer_hwmod_class,
1955         .clkdm_name     = "wkupaon_clkdm",
1956         .main_clk       = "sys_32k_ck",
1957         .prcm = {
1958                 .omap4 = {
1959                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1960                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1961                         .modulemode   = MODULEMODE_SWCTRL,
1962                 },
1963         },
1964 };
1965
1966 /*
1967  * 'ocp2scp' class
1968  * bridge to transform ocp interface protocol to scp (serial control port)
1969  * protocol
1970  */
1971 /* ocp2scp3 */
1972 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
1973 /* l4_cfg -> ocp2scp3 */
1974 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
1975         .master         = &omap54xx_l4_cfg_hwmod,
1976         .slave          = &omap54xx_ocp2scp3_hwmod,
1977         .clk            = "l4_root_clk_div",
1978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1979 };
1980
1981 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
1982         .name           = "ocp2scp3",
1983         .class          = &omap54xx_ocp2scp_hwmod_class,
1984         .clkdm_name     = "l3init_clkdm",
1985         .prcm = {
1986                 .omap4 = {
1987                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1988                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1989                         .modulemode   = MODULEMODE_HWCTRL,
1990                 },
1991         },
1992 };
1993
1994 /*
1995  * 'sata' class
1996  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
1997  */
1998
1999 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2000         .sysc_offs      = 0x0000,
2001         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2002         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2003                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2004                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2005         .sysc_fields    = &omap_hwmod_sysc_type2,
2006 };
2007
2008 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2009         .name   = "sata",
2010         .sysc   = &omap54xx_sata_sysc,
2011 };
2012
2013 /* sata */
2014 static struct omap_hwmod omap54xx_sata_hwmod = {
2015         .name           = "sata",
2016         .class          = &omap54xx_sata_hwmod_class,
2017         .clkdm_name     = "l3init_clkdm",
2018         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2019         .main_clk       = "func_48m_fclk",
2020         .mpu_rt_idx     = 1,
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2024                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2025                         .modulemode   = MODULEMODE_SWCTRL,
2026                 },
2027         },
2028 };
2029
2030 /* l4_cfg -> sata */
2031 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2032         .master         = &omap54xx_l4_cfg_hwmod,
2033         .slave          = &omap54xx_sata_hwmod,
2034         .clk            = "l3_iclk_div",
2035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2036 };
2037
2038 /*
2039  * Interfaces
2040  */
2041
2042 /* l3_main_1 -> dmm */
2043 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2044         .master         = &omap54xx_l3_main_1_hwmod,
2045         .slave          = &omap54xx_dmm_hwmod,
2046         .clk            = "l3_iclk_div",
2047         .user           = OCP_USER_SDMA,
2048 };
2049
2050 /* l3_main_3 -> l3_instr */
2051 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2052         .master         = &omap54xx_l3_main_3_hwmod,
2053         .slave          = &omap54xx_l3_instr_hwmod,
2054         .clk            = "l3_iclk_div",
2055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2056 };
2057
2058 /* l3_main_2 -> l3_main_1 */
2059 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2060         .master         = &omap54xx_l3_main_2_hwmod,
2061         .slave          = &omap54xx_l3_main_1_hwmod,
2062         .clk            = "l3_iclk_div",
2063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2064 };
2065
2066 /* l4_cfg -> l3_main_1 */
2067 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2068         .master         = &omap54xx_l4_cfg_hwmod,
2069         .slave          = &omap54xx_l3_main_1_hwmod,
2070         .clk            = "l3_iclk_div",
2071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2072 };
2073
2074 /* l4_cfg -> mmu_dsp */
2075 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2076         .master         = &omap54xx_l4_cfg_hwmod,
2077         .slave          = &omap54xx_mmu_dsp_hwmod,
2078         .clk            = "l4_root_clk_div",
2079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2080 };
2081
2082 /* mpu -> l3_main_1 */
2083 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2084         .master         = &omap54xx_mpu_hwmod,
2085         .slave          = &omap54xx_l3_main_1_hwmod,
2086         .clk            = "l3_iclk_div",
2087         .user           = OCP_USER_MPU,
2088 };
2089
2090 /* l3_main_1 -> l3_main_2 */
2091 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2092         .master         = &omap54xx_l3_main_1_hwmod,
2093         .slave          = &omap54xx_l3_main_2_hwmod,
2094         .clk            = "l3_iclk_div",
2095         .user           = OCP_USER_MPU,
2096 };
2097
2098 /* l4_cfg -> l3_main_2 */
2099 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2100         .master         = &omap54xx_l4_cfg_hwmod,
2101         .slave          = &omap54xx_l3_main_2_hwmod,
2102         .clk            = "l3_iclk_div",
2103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2104 };
2105
2106 /* l3_main_2 -> mmu_ipu */
2107 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2108         .master         = &omap54xx_l3_main_2_hwmod,
2109         .slave          = &omap54xx_mmu_ipu_hwmod,
2110         .clk            = "l3_iclk_div",
2111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2112 };
2113
2114 /* l3_main_1 -> l3_main_3 */
2115 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2116         .master         = &omap54xx_l3_main_1_hwmod,
2117         .slave          = &omap54xx_l3_main_3_hwmod,
2118         .clk            = "l3_iclk_div",
2119         .user           = OCP_USER_MPU,
2120 };
2121
2122 /* l3_main_2 -> l3_main_3 */
2123 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2124         .master         = &omap54xx_l3_main_2_hwmod,
2125         .slave          = &omap54xx_l3_main_3_hwmod,
2126         .clk            = "l3_iclk_div",
2127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2128 };
2129
2130 /* l4_cfg -> l3_main_3 */
2131 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2132         .master         = &omap54xx_l4_cfg_hwmod,
2133         .slave          = &omap54xx_l3_main_3_hwmod,
2134         .clk            = "l3_iclk_div",
2135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2136 };
2137
2138 /* l3_main_1 -> l4_abe */
2139 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2140         .master         = &omap54xx_l3_main_1_hwmod,
2141         .slave          = &omap54xx_l4_abe_hwmod,
2142         .clk            = "abe_iclk",
2143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2144 };
2145
2146 /* mpu -> l4_abe */
2147 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2148         .master         = &omap54xx_mpu_hwmod,
2149         .slave          = &omap54xx_l4_abe_hwmod,
2150         .clk            = "abe_iclk",
2151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2152 };
2153
2154 /* l3_main_1 -> l4_cfg */
2155 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2156         .master         = &omap54xx_l3_main_1_hwmod,
2157         .slave          = &omap54xx_l4_cfg_hwmod,
2158         .clk            = "l4_root_clk_div",
2159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2160 };
2161
2162 /* l3_main_2 -> l4_per */
2163 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2164         .master         = &omap54xx_l3_main_2_hwmod,
2165         .slave          = &omap54xx_l4_per_hwmod,
2166         .clk            = "l4_root_clk_div",
2167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2168 };
2169
2170 /* l3_main_1 -> l4_wkup */
2171 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2172         .master         = &omap54xx_l3_main_1_hwmod,
2173         .slave          = &omap54xx_l4_wkup_hwmod,
2174         .clk            = "wkupaon_iclk_mux",
2175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2176 };
2177
2178 /* mpu -> mpu_private */
2179 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2180         .master         = &omap54xx_mpu_hwmod,
2181         .slave          = &omap54xx_mpu_private_hwmod,
2182         .clk            = "l3_iclk_div",
2183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2184 };
2185
2186 /* l4_wkup -> counter_32k */
2187 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2188         .master         = &omap54xx_l4_wkup_hwmod,
2189         .slave          = &omap54xx_counter_32k_hwmod,
2190         .clk            = "wkupaon_iclk_mux",
2191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 /* l4_cfg -> dma_system */
2195 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2196         .master         = &omap54xx_l4_cfg_hwmod,
2197         .slave          = &omap54xx_dma_system_hwmod,
2198         .clk            = "l4_root_clk_div",
2199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2200 };
2201
2202 /* l4_abe -> dmic */
2203 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2204         .master         = &omap54xx_l4_abe_hwmod,
2205         .slave          = &omap54xx_dmic_hwmod,
2206         .clk            = "abe_iclk",
2207         .user           = OCP_USER_MPU,
2208 };
2209
2210 /* l3_main_2 -> dss */
2211 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2212         .master         = &omap54xx_l3_main_2_hwmod,
2213         .slave          = &omap54xx_dss_hwmod,
2214         .clk            = "l3_iclk_div",
2215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2216 };
2217
2218 /* l3_main_2 -> dss_dispc */
2219 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2220         .master         = &omap54xx_l3_main_2_hwmod,
2221         .slave          = &omap54xx_dss_dispc_hwmod,
2222         .clk            = "l3_iclk_div",
2223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2224 };
2225
2226 /* l3_main_2 -> dss_dsi1_a */
2227 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2228         .master         = &omap54xx_l3_main_2_hwmod,
2229         .slave          = &omap54xx_dss_dsi1_a_hwmod,
2230         .clk            = "l3_iclk_div",
2231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 /* l3_main_2 -> dss_dsi1_c */
2235 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2236         .master         = &omap54xx_l3_main_2_hwmod,
2237         .slave          = &omap54xx_dss_dsi1_c_hwmod,
2238         .clk            = "l3_iclk_div",
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* l3_main_2 -> dss_hdmi */
2243 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2244         .master         = &omap54xx_l3_main_2_hwmod,
2245         .slave          = &omap54xx_dss_hdmi_hwmod,
2246         .clk            = "l3_iclk_div",
2247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* l3_main_2 -> dss_rfbi */
2251 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2252         .master         = &omap54xx_l3_main_2_hwmod,
2253         .slave          = &omap54xx_dss_rfbi_hwmod,
2254         .clk            = "l3_iclk_div",
2255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 /* mpu -> emif1 */
2259 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2260         .master         = &omap54xx_mpu_hwmod,
2261         .slave          = &omap54xx_emif1_hwmod,
2262         .clk            = "dpll_core_h11x2_ck",
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* mpu -> emif2 */
2267 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2268         .master         = &omap54xx_mpu_hwmod,
2269         .slave          = &omap54xx_emif2_hwmod,
2270         .clk            = "dpll_core_h11x2_ck",
2271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2272 };
2273
2274 /* l4_wkup -> gpio1 */
2275 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2276         .master         = &omap54xx_l4_wkup_hwmod,
2277         .slave          = &omap54xx_gpio1_hwmod,
2278         .clk            = "wkupaon_iclk_mux",
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282 /* l4_per -> gpio2 */
2283 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2284         .master         = &omap54xx_l4_per_hwmod,
2285         .slave          = &omap54xx_gpio2_hwmod,
2286         .clk            = "l4_root_clk_div",
2287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2288 };
2289
2290 /* l4_per -> gpio3 */
2291 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2292         .master         = &omap54xx_l4_per_hwmod,
2293         .slave          = &omap54xx_gpio3_hwmod,
2294         .clk            = "l4_root_clk_div",
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* l4_per -> gpio4 */
2299 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2300         .master         = &omap54xx_l4_per_hwmod,
2301         .slave          = &omap54xx_gpio4_hwmod,
2302         .clk            = "l4_root_clk_div",
2303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2304 };
2305
2306 /* l4_per -> gpio5 */
2307 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2308         .master         = &omap54xx_l4_per_hwmod,
2309         .slave          = &omap54xx_gpio5_hwmod,
2310         .clk            = "l4_root_clk_div",
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312 };
2313
2314 /* l4_per -> gpio6 */
2315 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2316         .master         = &omap54xx_l4_per_hwmod,
2317         .slave          = &omap54xx_gpio6_hwmod,
2318         .clk            = "l4_root_clk_div",
2319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 /* l4_per -> gpio7 */
2323 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2324         .master         = &omap54xx_l4_per_hwmod,
2325         .slave          = &omap54xx_gpio7_hwmod,
2326         .clk            = "l4_root_clk_div",
2327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2328 };
2329
2330 /* l4_per -> gpio8 */
2331 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2332         .master         = &omap54xx_l4_per_hwmod,
2333         .slave          = &omap54xx_gpio8_hwmod,
2334         .clk            = "l4_root_clk_div",
2335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* l4_per -> i2c1 */
2339 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2340         .master         = &omap54xx_l4_per_hwmod,
2341         .slave          = &omap54xx_i2c1_hwmod,
2342         .clk            = "l4_root_clk_div",
2343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2344 };
2345
2346 /* l4_per -> i2c2 */
2347 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2348         .master         = &omap54xx_l4_per_hwmod,
2349         .slave          = &omap54xx_i2c2_hwmod,
2350         .clk            = "l4_root_clk_div",
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* l4_per -> i2c3 */
2355 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2356         .master         = &omap54xx_l4_per_hwmod,
2357         .slave          = &omap54xx_i2c3_hwmod,
2358         .clk            = "l4_root_clk_div",
2359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2360 };
2361
2362 /* l4_per -> i2c4 */
2363 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2364         .master         = &omap54xx_l4_per_hwmod,
2365         .slave          = &omap54xx_i2c4_hwmod,
2366         .clk            = "l4_root_clk_div",
2367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* l4_per -> i2c5 */
2371 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2372         .master         = &omap54xx_l4_per_hwmod,
2373         .slave          = &omap54xx_i2c5_hwmod,
2374         .clk            = "l4_root_clk_div",
2375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* l4_wkup -> kbd */
2379 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2380         .master         = &omap54xx_l4_wkup_hwmod,
2381         .slave          = &omap54xx_kbd_hwmod,
2382         .clk            = "wkupaon_iclk_mux",
2383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2384 };
2385
2386 /* l4_cfg -> mailbox */
2387 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2388         .master         = &omap54xx_l4_cfg_hwmod,
2389         .slave          = &omap54xx_mailbox_hwmod,
2390         .clk            = "l4_root_clk_div",
2391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2392 };
2393
2394 /* l4_abe -> mcbsp1 */
2395 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2396         .master         = &omap54xx_l4_abe_hwmod,
2397         .slave          = &omap54xx_mcbsp1_hwmod,
2398         .clk            = "abe_iclk",
2399         .user           = OCP_USER_MPU,
2400 };
2401
2402 /* l4_abe -> mcbsp2 */
2403 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2404         .master         = &omap54xx_l4_abe_hwmod,
2405         .slave          = &omap54xx_mcbsp2_hwmod,
2406         .clk            = "abe_iclk",
2407         .user           = OCP_USER_MPU,
2408 };
2409
2410 /* l4_abe -> mcbsp3 */
2411 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2412         .master         = &omap54xx_l4_abe_hwmod,
2413         .slave          = &omap54xx_mcbsp3_hwmod,
2414         .clk            = "abe_iclk",
2415         .user           = OCP_USER_MPU,
2416 };
2417
2418 /* l4_abe -> mcpdm */
2419 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2420         .master         = &omap54xx_l4_abe_hwmod,
2421         .slave          = &omap54xx_mcpdm_hwmod,
2422         .clk            = "abe_iclk",
2423         .user           = OCP_USER_MPU,
2424 };
2425
2426 /* l4_per -> mcspi1 */
2427 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2428         .master         = &omap54xx_l4_per_hwmod,
2429         .slave          = &omap54xx_mcspi1_hwmod,
2430         .clk            = "l4_root_clk_div",
2431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2432 };
2433
2434 /* l4_per -> mcspi2 */
2435 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2436         .master         = &omap54xx_l4_per_hwmod,
2437         .slave          = &omap54xx_mcspi2_hwmod,
2438         .clk            = "l4_root_clk_div",
2439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2440 };
2441
2442 /* l4_per -> mcspi3 */
2443 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2444         .master         = &omap54xx_l4_per_hwmod,
2445         .slave          = &omap54xx_mcspi3_hwmod,
2446         .clk            = "l4_root_clk_div",
2447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2448 };
2449
2450 /* l4_per -> mcspi4 */
2451 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2452         .master         = &omap54xx_l4_per_hwmod,
2453         .slave          = &omap54xx_mcspi4_hwmod,
2454         .clk            = "l4_root_clk_div",
2455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2456 };
2457
2458 /* l4_per -> mmc1 */
2459 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2460         .master         = &omap54xx_l4_per_hwmod,
2461         .slave          = &omap54xx_mmc1_hwmod,
2462         .clk            = "l3_iclk_div",
2463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2464 };
2465
2466 /* l4_per -> mmc2 */
2467 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2468         .master         = &omap54xx_l4_per_hwmod,
2469         .slave          = &omap54xx_mmc2_hwmod,
2470         .clk            = "l3_iclk_div",
2471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2472 };
2473
2474 /* l4_per -> mmc3 */
2475 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2476         .master         = &omap54xx_l4_per_hwmod,
2477         .slave          = &omap54xx_mmc3_hwmod,
2478         .clk            = "l4_root_clk_div",
2479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 /* l4_per -> mmc4 */
2483 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2484         .master         = &omap54xx_l4_per_hwmod,
2485         .slave          = &omap54xx_mmc4_hwmod,
2486         .clk            = "l4_root_clk_div",
2487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2488 };
2489
2490 /* l4_per -> mmc5 */
2491 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2492         .master         = &omap54xx_l4_per_hwmod,
2493         .slave          = &omap54xx_mmc5_hwmod,
2494         .clk            = "l4_root_clk_div",
2495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2496 };
2497
2498 /* l4_cfg -> mpu */
2499 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2500         .master         = &omap54xx_l4_cfg_hwmod,
2501         .slave          = &omap54xx_mpu_hwmod,
2502         .clk            = "l4_root_clk_div",
2503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2504 };
2505
2506 /* l4_cfg -> spinlock */
2507 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2508         .master         = &omap54xx_l4_cfg_hwmod,
2509         .slave          = &omap54xx_spinlock_hwmod,
2510         .clk            = "l4_root_clk_div",
2511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2512 };
2513
2514 /* l4_cfg -> ocp2scp1 */
2515 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2516         .master         = &omap54xx_l4_cfg_hwmod,
2517         .slave          = &omap54xx_ocp2scp1_hwmod,
2518         .clk            = "l4_root_clk_div",
2519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2520 };
2521
2522 /* l4_wkup -> timer1 */
2523 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2524         .master         = &omap54xx_l4_wkup_hwmod,
2525         .slave          = &omap54xx_timer1_hwmod,
2526         .clk            = "wkupaon_iclk_mux",
2527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2528 };
2529
2530 /* l4_per -> timer2 */
2531 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2532         .master         = &omap54xx_l4_per_hwmod,
2533         .slave          = &omap54xx_timer2_hwmod,
2534         .clk            = "l4_root_clk_div",
2535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2536 };
2537
2538 /* l4_per -> timer3 */
2539 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2540         .master         = &omap54xx_l4_per_hwmod,
2541         .slave          = &omap54xx_timer3_hwmod,
2542         .clk            = "l4_root_clk_div",
2543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2544 };
2545
2546 /* l4_per -> timer4 */
2547 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2548         .master         = &omap54xx_l4_per_hwmod,
2549         .slave          = &omap54xx_timer4_hwmod,
2550         .clk            = "l4_root_clk_div",
2551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554 /* l4_abe -> timer5 */
2555 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2556         .master         = &omap54xx_l4_abe_hwmod,
2557         .slave          = &omap54xx_timer5_hwmod,
2558         .clk            = "abe_iclk",
2559         .user           = OCP_USER_MPU,
2560 };
2561
2562 /* l4_abe -> timer6 */
2563 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2564         .master         = &omap54xx_l4_abe_hwmod,
2565         .slave          = &omap54xx_timer6_hwmod,
2566         .clk            = "abe_iclk",
2567         .user           = OCP_USER_MPU,
2568 };
2569
2570 /* l4_abe -> timer7 */
2571 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2572         .master         = &omap54xx_l4_abe_hwmod,
2573         .slave          = &omap54xx_timer7_hwmod,
2574         .clk            = "abe_iclk",
2575         .user           = OCP_USER_MPU,
2576 };
2577
2578 /* l4_abe -> timer8 */
2579 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2580         .master         = &omap54xx_l4_abe_hwmod,
2581         .slave          = &omap54xx_timer8_hwmod,
2582         .clk            = "abe_iclk",
2583         .user           = OCP_USER_MPU,
2584 };
2585
2586 /* l4_per -> timer9 */
2587 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2588         .master         = &omap54xx_l4_per_hwmod,
2589         .slave          = &omap54xx_timer9_hwmod,
2590         .clk            = "l4_root_clk_div",
2591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2592 };
2593
2594 /* l4_per -> timer10 */
2595 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2596         .master         = &omap54xx_l4_per_hwmod,
2597         .slave          = &omap54xx_timer10_hwmod,
2598         .clk            = "l4_root_clk_div",
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 /* l4_per -> timer11 */
2603 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2604         .master         = &omap54xx_l4_per_hwmod,
2605         .slave          = &omap54xx_timer11_hwmod,
2606         .clk            = "l4_root_clk_div",
2607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2608 };
2609
2610 /* l4_per -> uart1 */
2611 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2612         .master         = &omap54xx_l4_per_hwmod,
2613         .slave          = &omap54xx_uart1_hwmod,
2614         .clk            = "l4_root_clk_div",
2615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2616 };
2617
2618 /* l4_per -> uart2 */
2619 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2620         .master         = &omap54xx_l4_per_hwmod,
2621         .slave          = &omap54xx_uart2_hwmod,
2622         .clk            = "l4_root_clk_div",
2623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2624 };
2625
2626 /* l4_per -> uart3 */
2627 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2628         .master         = &omap54xx_l4_per_hwmod,
2629         .slave          = &omap54xx_uart3_hwmod,
2630         .clk            = "l4_root_clk_div",
2631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2632 };
2633
2634 /* l4_per -> uart4 */
2635 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2636         .master         = &omap54xx_l4_per_hwmod,
2637         .slave          = &omap54xx_uart4_hwmod,
2638         .clk            = "l4_root_clk_div",
2639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2640 };
2641
2642 /* l4_per -> uart5 */
2643 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2644         .master         = &omap54xx_l4_per_hwmod,
2645         .slave          = &omap54xx_uart5_hwmod,
2646         .clk            = "l4_root_clk_div",
2647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2648 };
2649
2650 /* l4_per -> uart6 */
2651 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2652         .master         = &omap54xx_l4_per_hwmod,
2653         .slave          = &omap54xx_uart6_hwmod,
2654         .clk            = "l4_root_clk_div",
2655         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2656 };
2657
2658 /* l4_cfg -> usb_host_hs */
2659 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2660         .master         = &omap54xx_l4_cfg_hwmod,
2661         .slave          = &omap54xx_usb_host_hs_hwmod,
2662         .clk            = "l3_iclk_div",
2663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2664 };
2665
2666 /* l4_cfg -> usb_tll_hs */
2667 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2668         .master         = &omap54xx_l4_cfg_hwmod,
2669         .slave          = &omap54xx_usb_tll_hs_hwmod,
2670         .clk            = "l4_root_clk_div",
2671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2672 };
2673
2674 /* l4_cfg -> usb_otg_ss */
2675 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2676         .master         = &omap54xx_l4_cfg_hwmod,
2677         .slave          = &omap54xx_usb_otg_ss_hwmod,
2678         .clk            = "dpll_core_h13x2_ck",
2679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2680 };
2681
2682 /* l4_wkup -> wd_timer2 */
2683 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2684         .master         = &omap54xx_l4_wkup_hwmod,
2685         .slave          = &omap54xx_wd_timer2_hwmod,
2686         .clk            = "wkupaon_iclk_mux",
2687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2688 };
2689
2690 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2691         &omap54xx_l3_main_1__dmm,
2692         &omap54xx_l3_main_3__l3_instr,
2693         &omap54xx_l3_main_2__l3_main_1,
2694         &omap54xx_l4_cfg__l3_main_1,
2695         &omap54xx_mpu__l3_main_1,
2696         &omap54xx_l3_main_1__l3_main_2,
2697         &omap54xx_l4_cfg__l3_main_2,
2698         &omap54xx_l3_main_1__l3_main_3,
2699         &omap54xx_l3_main_2__l3_main_3,
2700         &omap54xx_l4_cfg__l3_main_3,
2701         &omap54xx_l3_main_1__l4_abe,
2702         &omap54xx_mpu__l4_abe,
2703         &omap54xx_l3_main_1__l4_cfg,
2704         &omap54xx_l3_main_2__l4_per,
2705         &omap54xx_l3_main_1__l4_wkup,
2706         &omap54xx_mpu__mpu_private,
2707         &omap54xx_l4_wkup__counter_32k,
2708         &omap54xx_l4_cfg__dma_system,
2709         &omap54xx_l4_abe__dmic,
2710         &omap54xx_l4_cfg__mmu_dsp,
2711         &omap54xx_l3_main_2__dss,
2712         &omap54xx_l3_main_2__dss_dispc,
2713         &omap54xx_l3_main_2__dss_dsi1_a,
2714         &omap54xx_l3_main_2__dss_dsi1_c,
2715         &omap54xx_l3_main_2__dss_hdmi,
2716         &omap54xx_l3_main_2__dss_rfbi,
2717         &omap54xx_mpu__emif1,
2718         &omap54xx_mpu__emif2,
2719         &omap54xx_l4_wkup__gpio1,
2720         &omap54xx_l4_per__gpio2,
2721         &omap54xx_l4_per__gpio3,
2722         &omap54xx_l4_per__gpio4,
2723         &omap54xx_l4_per__gpio5,
2724         &omap54xx_l4_per__gpio6,
2725         &omap54xx_l4_per__gpio7,
2726         &omap54xx_l4_per__gpio8,
2727         &omap54xx_l4_per__i2c1,
2728         &omap54xx_l4_per__i2c2,
2729         &omap54xx_l4_per__i2c3,
2730         &omap54xx_l4_per__i2c4,
2731         &omap54xx_l4_per__i2c5,
2732         &omap54xx_l3_main_2__mmu_ipu,
2733         &omap54xx_l4_wkup__kbd,
2734         &omap54xx_l4_cfg__mailbox,
2735         &omap54xx_l4_abe__mcbsp1,
2736         &omap54xx_l4_abe__mcbsp2,
2737         &omap54xx_l4_abe__mcbsp3,
2738         &omap54xx_l4_abe__mcpdm,
2739         &omap54xx_l4_per__mcspi1,
2740         &omap54xx_l4_per__mcspi2,
2741         &omap54xx_l4_per__mcspi3,
2742         &omap54xx_l4_per__mcspi4,
2743         &omap54xx_l4_per__mmc1,
2744         &omap54xx_l4_per__mmc2,
2745         &omap54xx_l4_per__mmc3,
2746         &omap54xx_l4_per__mmc4,
2747         &omap54xx_l4_per__mmc5,
2748         &omap54xx_l4_cfg__mpu,
2749         &omap54xx_l4_cfg__spinlock,
2750         &omap54xx_l4_cfg__ocp2scp1,
2751         &omap54xx_l4_wkup__timer1,
2752         &omap54xx_l4_per__timer2,
2753         &omap54xx_l4_per__timer3,
2754         &omap54xx_l4_per__timer4,
2755         &omap54xx_l4_abe__timer5,
2756         &omap54xx_l4_abe__timer6,
2757         &omap54xx_l4_abe__timer7,
2758         &omap54xx_l4_abe__timer8,
2759         &omap54xx_l4_per__timer9,
2760         &omap54xx_l4_per__timer10,
2761         &omap54xx_l4_per__timer11,
2762         &omap54xx_l4_per__uart1,
2763         &omap54xx_l4_per__uart2,
2764         &omap54xx_l4_per__uart3,
2765         &omap54xx_l4_per__uart4,
2766         &omap54xx_l4_per__uart5,
2767         &omap54xx_l4_per__uart6,
2768         &omap54xx_l4_cfg__usb_host_hs,
2769         &omap54xx_l4_cfg__usb_tll_hs,
2770         &omap54xx_l4_cfg__usb_otg_ss,
2771         &omap54xx_l4_wkup__wd_timer2,
2772         &omap54xx_l4_cfg__ocp2scp3,
2773         &omap54xx_l4_cfg__sata,
2774         NULL,
2775 };
2776
2777 int __init omap54xx_hwmod_init(void)
2778 {
2779         omap_hwmod_init();
2780         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2781 }