arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "omap_hwmod_common_data.h"
  32 #include "cm1_54xx.h"
  33 #include "cm2_54xx.h"
  34 #include "prm54xx.h"
  35 #include "i2c.h"
  36 #include "mmc.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP5 interrupts external to MPUSS */
  40 #define OMAP54XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP5 dma requests */
  43 #define OMAP54XX_DMA_REQ_START  1
  44
  45
  46 /*
  47  * IP blocks
  48  */
  49
  50 /*
  51  * 'dmm' class
  52  * instance(s): dmm
  53  */
  54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  55         .name   = "dmm",
  56 };
  57
  58 /* dmm */
  59 static struct omap_hwmod omap54xx_dmm_hwmod = {
  60         .name           = "dmm",
  61         .class          = &omap54xx_dmm_hwmod_class,
  62         .clkdm_name     = "emif_clkdm",
  63         .prcm = {
  64                 .omap4 = {
  65                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  66                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  67                 },
  68         },
  69 };
  70
  71 /*
  72  * 'l3' class
  73  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  74  */
  75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  76         .name   = "l3",
  77 };
  78
  79 /* l3_instr */
  80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  81         .name           = "l3_instr",
  82         .class          = &omap54xx_l3_hwmod_class,
  83         .clkdm_name     = "l3instr_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  88                         .modulemode   = MODULEMODE_HWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /* l3_main_1 */
  94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  95         .name           = "l3_main_1",
  96         .class          = &omap54xx_l3_hwmod_class,
  97         .clkdm_name     = "l3main1_clkdm",
  98         .prcm = {
  99                 .omap4 = {
 100                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 101                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 102                 },
 103         },
 104 };
 105
 106 /* l3_main_2 */
 107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 108         .name           = "l3_main_2",
 109         .class          = &omap54xx_l3_hwmod_class,
 110         .clkdm_name     = "l3main2_clkdm",
 111         .prcm = {
 112                 .omap4 = {
 113                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 114                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 115                 },
 116         },
 117 };
 118
 119 /* l3_main_3 */
 120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 121         .name           = "l3_main_3",
 122         .class          = &omap54xx_l3_hwmod_class,
 123         .clkdm_name     = "l3instr_clkdm",
 124         .prcm = {
 125                 .omap4 = {
 126                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 127                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 128                         .modulemode   = MODULEMODE_HWCTRL,
 129                 },
 130         },
 131 };
 132
 133 /*
 134  * 'l4' class
 135  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 136  */
 137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 138         .name   = "l4",
 139 };
 140
 141 /* l4_abe */
 142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 143         .name           = "l4_abe",
 144         .class          = &omap54xx_l4_hwmod_class,
 145         .clkdm_name     = "abe_clkdm",
 146         .prcm = {
 147                 .omap4 = {
 148                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 149                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 150                 },
 151         },
 152 };
 153
 154 /* l4_cfg */
 155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 156         .name           = "l4_cfg",
 157         .class          = &omap54xx_l4_hwmod_class,
 158         .clkdm_name     = "l4cfg_clkdm",
 159         .prcm = {
 160                 .omap4 = {
 161                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 162                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 163                 },
 164         },
 165 };
 166
 167 /* l4_per */
 168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 169         .name           = "l4_per",
 170         .class          = &omap54xx_l4_hwmod_class,
 171         .clkdm_name     = "l4per_clkdm",
 172         .prcm = {
 173                 .omap4 = {
 174                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 175                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 176                 },
 177         },
 178 };
 179
 180 /* l4_wkup */
 181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 182         .name           = "l4_wkup",
 183         .class          = &omap54xx_l4_hwmod_class,
 184         .clkdm_name     = "wkupaon_clkdm",
 185         .prcm = {
 186                 .omap4 = {
 187                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 188                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 189                 },
 190         },
 191 };
 192
 193 /*
 194  * 'mpu_bus' class
 195  * instance(s): mpu_private
 196  */
 197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 198         .name   = "mpu_bus",
 199 };
 200
 201 /* mpu_private */
 202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 203         .name           = "mpu_private",
 204         .class          = &omap54xx_mpu_bus_hwmod_class,
 205         .clkdm_name     = "mpu_clkdm",
 206         .prcm = {
 207                 .omap4 = {
 208                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 209                 },
 210         },
 211 };
 212
 213 /*
 214  * 'counter' class
 215  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 216  */
 217
 218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 219         .rev_offs       = 0x0000,
 220         .sysc_offs      = 0x0010,
 221         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 222         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 223         .sysc_fields    = &omap_hwmod_sysc_type1,
 224 };
 225
 226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 227         .name   = "counter",
 228         .sysc   = &omap54xx_counter_sysc,
 229 };
 230
 231 /* counter_32k */
 232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 233         .name           = "counter_32k",
 234         .class          = &omap54xx_counter_hwmod_class,
 235         .clkdm_name     = "wkupaon_clkdm",
 236         .flags          = HWMOD_SWSUP_SIDLE,
 237         .main_clk       = "wkupaon_iclk_mux",
 238         .prcm = {
 239                 .omap4 = {
 240                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 241                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 242                 },
 243         },
 244 };
 245
 246 /*
 247  * 'dma' class
 248  * dma controller for data exchange between memory to memory (i.e. internal or
 249  * external memory) and gp peripherals to memory or memory to gp peripherals
 250  */
 251
 252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 253         .rev_offs       = 0x0000,
 254         .sysc_offs      = 0x002c,
 255         .syss_offs      = 0x0028,
 256         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 257                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 258                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 259                            SYSS_HAS_RESET_STATUS),
 260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 261                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 262         .sysc_fields    = &omap_hwmod_sysc_type1,
 263 };
 264
 265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 266         .name   = "dma",
 267         .sysc   = &omap54xx_dma_sysc,
 268 };
 269
 270 /* dma dev_attr */
 271 static struct omap_dma_dev_attr dma_dev_attr = {
 272         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 273                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 274         .lch_count      = 32,
 275 };
 276
 277 /* dma_system */
 278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 279         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 280         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 281         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 282         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 283         { .irq = -1 }
 284 };
 285
 286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 287         .name           = "dma_system",
 288         .class          = &omap54xx_dma_hwmod_class,
 289         .clkdm_name     = "dma_clkdm",
 290         .mpu_irqs       = omap54xx_dma_system_irqs,
 291         .main_clk       = "l3_iclk_div",
 292         .prcm = {
 293                 .omap4 = {
 294                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 295                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 296                 },
 297         },
 298         .dev_attr       = &dma_dev_attr,
 299 };
 300
 301 /*
 302  * 'dmic' class
 303  * digital microphone controller
 304  */
 305
 306 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 307         .rev_offs       = 0x0000,
 308         .sysc_offs      = 0x0010,
 309         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 310                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 311         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 312                            SIDLE_SMART_WKUP),
 313         .sysc_fields    = &omap_hwmod_sysc_type2,
 314 };
 315
 316 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 317         .name   = "dmic",
 318         .sysc   = &omap54xx_dmic_sysc,
 319 };
 320
 321 /* dmic */
 322 static struct omap_hwmod omap54xx_dmic_hwmod = {
 323         .name           = "dmic",
 324         .class          = &omap54xx_dmic_hwmod_class,
 325         .clkdm_name     = "abe_clkdm",
 326         .main_clk       = "dmic_gfclk",
 327         .prcm = {
 328                 .omap4 = {
 329                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 330                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 331                         .modulemode   = MODULEMODE_SWCTRL,
 332                 },
 333         },
 334 };
 335
 336 /*
 337  * 'dss' class
 338  * display sub-system
 339  */
 340 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 341         .rev_offs       = 0x0000,
 342         .syss_offs      = 0x0014,
 343         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 344 };
 345
 346 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 347         .name   = "dss",
 348         .sysc   = &omap54xx_dss_sysc,
 349         .reset  = omap_dss_reset,
 350 };
 351
 352 /* dss */
 353 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 354         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 355         { .role = "sys_clk", .clk = "dss_sys_clk" },
 356         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 357 };
 358
 359 static struct omap_hwmod omap54xx_dss_hwmod = {
 360         .name           = "dss_core",
 361         .class          = &omap54xx_dss_hwmod_class,
 362         .clkdm_name     = "dss_clkdm",
 363         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 364         .main_clk       = "dss_dss_clk",
 365         .prcm = {
 366                 .omap4 = {
 367                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 368                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 369                         .modulemode   = MODULEMODE_SWCTRL,
 370                 },
 371         },
 372         .opt_clks       = dss_opt_clks,
 373         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 374 };
 375
 376 /*
 377  * 'dispc' class
 378  * display controller
 379  */
 380
 381 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 382         .rev_offs       = 0x0000,
 383         .sysc_offs      = 0x0010,
 384         .syss_offs      = 0x0014,
 385         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 386                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 387                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 388                            SYSS_HAS_RESET_STATUS),
 389         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 390                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 391         .sysc_fields    = &omap_hwmod_sysc_type1,
 392 };
 393
 394 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 395         .name   = "dispc",
 396         .sysc   = &omap54xx_dispc_sysc,
 397 };
 398
 399 /* dss_dispc */
 400 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 401         { .role = "sys_clk", .clk = "dss_sys_clk" },
 402 };
 403
 404 /* dss_dispc dev_attr */
 405 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 406         .has_framedonetv_irq    = 1,
 407         .manager_count          = 4,
 408 };
 409
 410 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 411         .name           = "dss_dispc",
 412         .class          = &omap54xx_dispc_hwmod_class,
 413         .clkdm_name     = "dss_clkdm",
 414         .main_clk       = "dss_dss_clk",
 415         .prcm = {
 416                 .omap4 = {
 417                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 418                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 419                 },
 420         },
 421         .opt_clks       = dss_dispc_opt_clks,
 422         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 423         .dev_attr       = &dss_dispc_dev_attr,
 424 };
 425
 426 /*
 427  * 'dsi1' class
 428  * display serial interface controller
 429  */
 430
 431 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 432         .rev_offs       = 0x0000,
 433         .sysc_offs      = 0x0010,
 434         .syss_offs      = 0x0014,
 435         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 436                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 437                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 438         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 439         .sysc_fields    = &omap_hwmod_sysc_type1,
 440 };
 441
 442 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 443         .name   = "dsi1",
 444         .sysc   = &omap54xx_dsi1_sysc,
 445 };
 446
 447 /* dss_dsi1_a */
 448 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 449         { .role = "sys_clk", .clk = "dss_sys_clk" },
 450 };
 451
 452 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 453         .name           = "dss_dsi1",
 454         .class          = &omap54xx_dsi1_hwmod_class,
 455         .clkdm_name     = "dss_clkdm",
 456         .main_clk       = "dss_dss_clk",
 457         .prcm = {
 458                 .omap4 = {
 459                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 460                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 461                 },
 462         },
 463         .opt_clks       = dss_dsi1_a_opt_clks,
 464         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 465 };
 466
 467 /* dss_dsi1_c */
 468 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 469         { .role = "sys_clk", .clk = "dss_sys_clk" },
 470 };
 471
 472 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 473         .name           = "dss_dsi2",
 474         .class          = &omap54xx_dsi1_hwmod_class,
 475         .clkdm_name     = "dss_clkdm",
 476         .main_clk       = "dss_dss_clk",
 477         .prcm = {
 478                 .omap4 = {
 479                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 480                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 481                 },
 482         },
 483         .opt_clks       = dss_dsi1_c_opt_clks,
 484         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 485 };
 486
 487 /*
 488  * 'hdmi' class
 489  * hdmi controller
 490  */
 491
 492 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 493         .rev_offs       = 0x0000,
 494         .sysc_offs      = 0x0010,
 495         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 496                            SYSC_HAS_SOFTRESET),
 497         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 498                            SIDLE_SMART_WKUP),
 499         .sysc_fields    = &omap_hwmod_sysc_type2,
 500 };
 501
 502 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 503         .name   = "hdmi",
 504         .sysc   = &omap54xx_hdmi_sysc,
 505 };
 506
 507 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 508         { .role = "sys_clk", .clk = "dss_sys_clk" },
 509 };
 510
 511 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 512         .name           = "dss_hdmi",
 513         .class          = &omap54xx_hdmi_hwmod_class,
 514         .clkdm_name     = "dss_clkdm",
 515         .main_clk       = "dss_48mhz_clk",
 516         .prcm = {
 517                 .omap4 = {
 518                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 519                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 520                 },
 521         },
 522         .opt_clks       = dss_hdmi_opt_clks,
 523         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 524 };
 525
 526 /*
 527  * 'rfbi' class
 528  * remote frame buffer interface
 529  */
 530
 531 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 532         .rev_offs       = 0x0000,
 533         .sysc_offs      = 0x0010,
 534         .syss_offs      = 0x0014,
 535         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 536                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 537         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 538         .sysc_fields    = &omap_hwmod_sysc_type1,
 539 };
 540
 541 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 542         .name   = "rfbi",
 543         .sysc   = &omap54xx_rfbi_sysc,
 544 };
 545
 546 /* dss_rfbi */
 547 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 548         { .role = "ick", .clk = "l3_iclk_div" },
 549 };
 550
 551 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 552         .name           = "dss_rfbi",
 553         .class          = &omap54xx_rfbi_hwmod_class,
 554         .clkdm_name     = "dss_clkdm",
 555         .prcm = {
 556                 .omap4 = {
 557                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 558                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 559                 },
 560         },
 561         .opt_clks       = dss_rfbi_opt_clks,
 562         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 563 };
 564
 565 /*
 566  * 'emif' class
 567  * external memory interface no1 (wrapper)
 568  */
 569
 570 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 571         .rev_offs       = 0x0000,
 572 };
 573
 574 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 575         .name   = "emif",
 576         .sysc   = &omap54xx_emif_sysc,
 577 };
 578
 579 /* emif1 */
 580 static struct omap_hwmod omap54xx_emif1_hwmod = {
 581         .name           = "emif1",
 582         .class          = &omap54xx_emif_hwmod_class,
 583         .clkdm_name     = "emif_clkdm",
 584         .flags          = HWMOD_INIT_NO_IDLE,
 585         .main_clk       = "dpll_core_h11x2_ck",
 586         .prcm = {
 587                 .omap4 = {
 588                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 589                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 590                         .modulemode   = MODULEMODE_HWCTRL,
 591                 },
 592         },
 593 };
 594
 595 /* emif2 */
 596 static struct omap_hwmod omap54xx_emif2_hwmod = {
 597         .name           = "emif2",
 598         .class          = &omap54xx_emif_hwmod_class,
 599         .clkdm_name     = "emif_clkdm",
 600         .flags          = HWMOD_INIT_NO_IDLE,
 601         .main_clk       = "dpll_core_h11x2_ck",
 602         .prcm = {
 603                 .omap4 = {
 604                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 605                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 606                         .modulemode   = MODULEMODE_HWCTRL,
 607                 },
 608         },
 609 };
 610
 611 /*
 612  * 'gpio' class
 613  * general purpose io module
 614  */
 615
 616 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 617         .rev_offs       = 0x0000,
 618         .sysc_offs      = 0x0010,
 619         .syss_offs      = 0x0114,
 620         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 621                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 622                            SYSS_HAS_RESET_STATUS),
 623         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 624                            SIDLE_SMART_WKUP),
 625         .sysc_fields    = &omap_hwmod_sysc_type1,
 626 };
 627
 628 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 629         .name   = "gpio",
 630         .sysc   = &omap54xx_gpio_sysc,
 631         .rev    = 2,
 632 };
 633
 634 /* gpio dev_attr */
 635 static struct omap_gpio_dev_attr gpio_dev_attr = {
 636         .bank_width     = 32,
 637         .dbck_flag      = true,
 638 };
 639
 640 /* gpio1 */
 641 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 642         { .role = "dbclk", .clk = "gpio1_dbclk" },
 643 };
 644
 645 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 646         .name           = "gpio1",
 647         .class          = &omap54xx_gpio_hwmod_class,
 648         .clkdm_name     = "wkupaon_clkdm",
 649         .main_clk       = "wkupaon_iclk_mux",
 650         .prcm = {
 651                 .omap4 = {
 652                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 653                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 654                         .modulemode   = MODULEMODE_HWCTRL,
 655                 },
 656         },
 657         .opt_clks       = gpio1_opt_clks,
 658         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 659         .dev_attr       = &gpio_dev_attr,
 660 };
 661
 662 /* gpio2 */
 663 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 664         { .role = "dbclk", .clk = "gpio2_dbclk" },
 665 };
 666
 667 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 668         .name           = "gpio2",
 669         .class          = &omap54xx_gpio_hwmod_class,
 670         .clkdm_name     = "l4per_clkdm",
 671         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 672         .main_clk       = "l4_root_clk_div",
 673         .prcm = {
 674                 .omap4 = {
 675                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 676                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 677                         .modulemode   = MODULEMODE_HWCTRL,
 678                 },
 679         },
 680         .opt_clks       = gpio2_opt_clks,
 681         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 682         .dev_attr       = &gpio_dev_attr,
 683 };
 684
 685 /* gpio3 */
 686 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 687         { .role = "dbclk", .clk = "gpio3_dbclk" },
 688 };
 689
 690 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 691         .name           = "gpio3",
 692         .class          = &omap54xx_gpio_hwmod_class,
 693         .clkdm_name     = "l4per_clkdm",
 694         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 695         .main_clk       = "l4_root_clk_div",
 696         .prcm = {
 697                 .omap4 = {
 698                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 699                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 700                         .modulemode   = MODULEMODE_HWCTRL,
 701                 },
 702         },
 703         .opt_clks       = gpio3_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 705         .dev_attr       = &gpio_dev_attr,
 706 };
 707
 708 /* gpio4 */
 709 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 710         { .role = "dbclk", .clk = "gpio4_dbclk" },
 711 };
 712
 713 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 714         .name           = "gpio4",
 715         .class          = &omap54xx_gpio_hwmod_class,
 716         .clkdm_name     = "l4per_clkdm",
 717         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 718         .main_clk       = "l4_root_clk_div",
 719         .prcm = {
 720                 .omap4 = {
 721                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 722                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 723                         .modulemode   = MODULEMODE_HWCTRL,
 724                 },
 725         },
 726         .opt_clks       = gpio4_opt_clks,
 727         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 728         .dev_attr       = &gpio_dev_attr,
 729 };
 730
 731 /* gpio5 */
 732 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 733         { .role = "dbclk", .clk = "gpio5_dbclk" },
 734 };
 735
 736 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 737         .name           = "gpio5",
 738         .class          = &omap54xx_gpio_hwmod_class,
 739         .clkdm_name     = "l4per_clkdm",
 740         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 741         .main_clk       = "l4_root_clk_div",
 742         .prcm = {
 743                 .omap4 = {
 744                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 745                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 746                         .modulemode   = MODULEMODE_HWCTRL,
 747                 },
 748         },
 749         .opt_clks       = gpio5_opt_clks,
 750         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 751         .dev_attr       = &gpio_dev_attr,
 752 };
 753
 754 /* gpio6 */
 755 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 756         { .role = "dbclk", .clk = "gpio6_dbclk" },
 757 };
 758
 759 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 760         .name           = "gpio6",
 761         .class          = &omap54xx_gpio_hwmod_class,
 762         .clkdm_name     = "l4per_clkdm",
 763         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 764         .main_clk       = "l4_root_clk_div",
 765         .prcm = {
 766                 .omap4 = {
 767                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 768                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 769                         .modulemode   = MODULEMODE_HWCTRL,
 770                 },
 771         },
 772         .opt_clks       = gpio6_opt_clks,
 773         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 774         .dev_attr       = &gpio_dev_attr,
 775 };
 776
 777 /* gpio7 */
 778 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 779         { .role = "dbclk", .clk = "gpio7_dbclk" },
 780 };
 781
 782 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 783         .name           = "gpio7",
 784         .class          = &omap54xx_gpio_hwmod_class,
 785         .clkdm_name     = "l4per_clkdm",
 786         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 787         .main_clk       = "l4_root_clk_div",
 788         .prcm = {
 789                 .omap4 = {
 790                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 791                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 792                         .modulemode   = MODULEMODE_HWCTRL,
 793                 },
 794         },
 795         .opt_clks       = gpio7_opt_clks,
 796         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 797         .dev_attr       = &gpio_dev_attr,
 798 };
 799
 800 /* gpio8 */
 801 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 802         { .role = "dbclk", .clk = "gpio8_dbclk" },
 803 };
 804
 805 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 806         .name           = "gpio8",
 807         .class          = &omap54xx_gpio_hwmod_class,
 808         .clkdm_name     = "l4per_clkdm",
 809         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 810         .main_clk       = "l4_root_clk_div",
 811         .prcm = {
 812                 .omap4 = {
 813                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 814                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 815                         .modulemode   = MODULEMODE_HWCTRL,
 816                 },
 817         },
 818         .opt_clks       = gpio8_opt_clks,
 819         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 820         .dev_attr       = &gpio_dev_attr,
 821 };
 822
 823 /*
 824  * 'i2c' class
 825  * multimaster high-speed i2c controller
 826  */
 827
 828 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 829         .sysc_offs      = 0x0010,
 830         .syss_offs      = 0x0090,
 831         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 832                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 833                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 834         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 835                            SIDLE_SMART_WKUP),
 836         .clockact       = CLOCKACT_TEST_ICLK,
 837         .sysc_fields    = &omap_hwmod_sysc_type1,
 838 };
 839
 840 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 841         .name   = "i2c",
 842         .sysc   = &omap54xx_i2c_sysc,
 843         .reset  = &omap_i2c_reset,
 844         .rev    = OMAP_I2C_IP_VERSION_2,
 845 };
 846
 847 /* i2c dev_attr */
 848 static struct omap_i2c_dev_attr i2c_dev_attr = {
 849         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 850 };
 851
 852 /* i2c1 */
 853 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 854         .name           = "i2c1",
 855         .class          = &omap54xx_i2c_hwmod_class,
 856         .clkdm_name     = "l4per_clkdm",
 857         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 858         .main_clk       = "func_96m_fclk",
 859         .prcm = {
 860                 .omap4 = {
 861                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 862                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 863                         .modulemode   = MODULEMODE_SWCTRL,
 864                 },
 865         },
 866         .dev_attr       = &i2c_dev_attr,
 867 };
 868
 869 /* i2c2 */
 870 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 871         .name           = "i2c2",
 872         .class          = &omap54xx_i2c_hwmod_class,
 873         .clkdm_name     = "l4per_clkdm",
 874         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 875         .main_clk       = "func_96m_fclk",
 876         .prcm = {
 877                 .omap4 = {
 878                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 879                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 880                         .modulemode   = MODULEMODE_SWCTRL,
 881                 },
 882         },
 883         .dev_attr       = &i2c_dev_attr,
 884 };
 885
 886 /* i2c3 */
 887 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 888         .name           = "i2c3",
 889         .class          = &omap54xx_i2c_hwmod_class,
 890         .clkdm_name     = "l4per_clkdm",
 891         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 892         .main_clk       = "func_96m_fclk",
 893         .prcm = {
 894                 .omap4 = {
 895                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 896                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 897                         .modulemode   = MODULEMODE_SWCTRL,
 898                 },
 899         },
 900         .dev_attr       = &i2c_dev_attr,
 901 };
 902
 903 /* i2c4 */
 904 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 905         .name           = "i2c4",
 906         .class          = &omap54xx_i2c_hwmod_class,
 907         .clkdm_name     = "l4per_clkdm",
 908         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 909         .main_clk       = "func_96m_fclk",
 910         .prcm = {
 911                 .omap4 = {
 912                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 913                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 914                         .modulemode   = MODULEMODE_SWCTRL,
 915                 },
 916         },
 917         .dev_attr       = &i2c_dev_attr,
 918 };
 919
 920 /* i2c5 */
 921 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 922         .name           = "i2c5",
 923         .class          = &omap54xx_i2c_hwmod_class,
 924         .clkdm_name     = "l4per_clkdm",
 925         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 926         .main_clk       = "func_96m_fclk",
 927         .prcm = {
 928                 .omap4 = {
 929                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 930                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 931                         .modulemode   = MODULEMODE_SWCTRL,
 932                 },
 933         },
 934         .dev_attr       = &i2c_dev_attr,
 935 };
 936
 937 /*
 938  * 'kbd' class
 939  * keyboard controller
 940  */
 941
 942 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 943         .rev_offs       = 0x0000,
 944         .sysc_offs      = 0x0010,
 945         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 946                            SYSC_HAS_SOFTRESET),
 947         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 948         .sysc_fields    = &omap_hwmod_sysc_type1,
 949 };
 950
 951 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 952         .name   = "kbd",
 953         .sysc   = &omap54xx_kbd_sysc,
 954 };
 955
 956 /* kbd */
 957 static struct omap_hwmod omap54xx_kbd_hwmod = {
 958         .name           = "kbd",
 959         .class          = &omap54xx_kbd_hwmod_class,
 960         .clkdm_name     = "wkupaon_clkdm",
 961         .main_clk       = "sys_32k_ck",
 962         .prcm = {
 963                 .omap4 = {
 964                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 965                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 966                         .modulemode   = MODULEMODE_SWCTRL,
 967                 },
 968         },
 969 };
 970
 971 /*
 972  * 'mailbox' class
 973  * mailbox module allowing communication between the on-chip processors using a
 974  * queued mailbox-interrupt mechanism.
 975  */
 976
 977 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 978         .rev_offs       = 0x0000,
 979         .sysc_offs      = 0x0010,
 980         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 981                            SYSC_HAS_SOFTRESET),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type2,
 984 };
 985
 986 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 987         .name   = "mailbox",
 988         .sysc   = &omap54xx_mailbox_sysc,
 989 };
 990
 991 /* mailbox */
 992 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 993         .name           = "mailbox",
 994         .class          = &omap54xx_mailbox_hwmod_class,
 995         .clkdm_name     = "l4cfg_clkdm",
 996         .prcm = {
 997                 .omap4 = {
 998                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
 999                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1000                 },
1001         },
1002 };
1003
1004 /*
1005  * 'mcbsp' class
1006  * multi channel buffered serial port controller
1007  */
1008
1009 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
1010         .sysc_offs      = 0x008c,
1011         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1012                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1013         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1014         .sysc_fields    = &omap_hwmod_sysc_type1,
1015 };
1016
1017 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
1018         .name   = "mcbsp",
1019         .sysc   = &omap54xx_mcbsp_sysc,
1020         .rev    = MCBSP_CONFIG_TYPE4,
1021 };
1022
1023 /* mcbsp1 */
1024 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1025         { .role = "pad_fck", .clk = "pad_clks_ck" },
1026         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1027 };
1028
1029 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
1030         .name           = "mcbsp1",
1031         .class          = &omap54xx_mcbsp_hwmod_class,
1032         .clkdm_name     = "abe_clkdm",
1033         .main_clk       = "mcbsp1_gfclk",
1034         .prcm = {
1035                 .omap4 = {
1036                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1037                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1038                         .modulemode   = MODULEMODE_SWCTRL,
1039                 },
1040         },
1041         .opt_clks       = mcbsp1_opt_clks,
1042         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1043 };
1044
1045 /* mcbsp2 */
1046 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1047         { .role = "pad_fck", .clk = "pad_clks_ck" },
1048         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1049 };
1050
1051 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1052         .name           = "mcbsp2",
1053         .class          = &omap54xx_mcbsp_hwmod_class,
1054         .clkdm_name     = "abe_clkdm",
1055         .main_clk       = "mcbsp2_gfclk",
1056         .prcm = {
1057                 .omap4 = {
1058                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1059                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1060                         .modulemode   = MODULEMODE_SWCTRL,
1061                 },
1062         },
1063         .opt_clks       = mcbsp2_opt_clks,
1064         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1065 };
1066
1067 /* mcbsp3 */
1068 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1069         { .role = "pad_fck", .clk = "pad_clks_ck" },
1070         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1071 };
1072
1073 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1074         .name           = "mcbsp3",
1075         .class          = &omap54xx_mcbsp_hwmod_class,
1076         .clkdm_name     = "abe_clkdm",
1077         .main_clk       = "mcbsp3_gfclk",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085         .opt_clks       = mcbsp3_opt_clks,
1086         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1087 };
1088
1089 /*
1090  * 'mcpdm' class
1091  * multi channel pdm controller (proprietary interface with phoenix power
1092  * ic)
1093  */
1094
1095 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1096         .rev_offs       = 0x0000,
1097         .sysc_offs      = 0x0010,
1098         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1099                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1100         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1101                            SIDLE_SMART_WKUP),
1102         .sysc_fields    = &omap_hwmod_sysc_type2,
1103 };
1104
1105 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1106         .name   = "mcpdm",
1107         .sysc   = &omap54xx_mcpdm_sysc,
1108 };
1109
1110 /* mcpdm */
1111 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1112         .name           = "mcpdm",
1113         .class          = &omap54xx_mcpdm_hwmod_class,
1114         .clkdm_name     = "abe_clkdm",
1115         /*
1116          * It's suspected that the McPDM requires an off-chip main
1117          * functional clock, controlled via I2C.  This IP block is
1118          * currently reset very early during boot, before I2C is
1119          * available, so it doesn't seem that we have any choice in
1120          * the kernel other than to avoid resetting it.  XXX This is
1121          * really a hardware issue workaround: every IP block should
1122          * be able to source its main functional clock from either
1123          * on-chip or off-chip sources.  McPDM seems to be the only
1124          * current exception.
1125          */
1126
1127         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1128         .main_clk       = "pad_clks_ck",
1129         .prcm = {
1130                 .omap4 = {
1131                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1132                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1133                         .modulemode   = MODULEMODE_SWCTRL,
1134                 },
1135         },
1136 };
1137
1138 /*
1139  * 'mcspi' class
1140  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1141  * bus
1142  */
1143
1144 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1145         .rev_offs       = 0x0000,
1146         .sysc_offs      = 0x0010,
1147         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1148                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1149         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1150                            SIDLE_SMART_WKUP),
1151         .sysc_fields    = &omap_hwmod_sysc_type2,
1152 };
1153
1154 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1155         .name   = "mcspi",
1156         .sysc   = &omap54xx_mcspi_sysc,
1157         .rev    = OMAP4_MCSPI_REV,
1158 };
1159
1160 /* mcspi1 */
1161 /* mcspi1 dev_attr */
1162 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1163         .num_chipselect = 4,
1164 };
1165
1166 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1167         .name           = "mcspi1",
1168         .class          = &omap54xx_mcspi_hwmod_class,
1169         .clkdm_name     = "l4per_clkdm",
1170         .main_clk       = "func_48m_fclk",
1171         .prcm = {
1172                 .omap4 = {
1173                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1174                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1175                         .modulemode   = MODULEMODE_SWCTRL,
1176                 },
1177         },
1178         .dev_attr       = &mcspi1_dev_attr,
1179 };
1180
1181 /* mcspi2 */
1182 /* mcspi2 dev_attr */
1183 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1184         .num_chipselect = 2,
1185 };
1186
1187 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1188         .name           = "mcspi2",
1189         .class          = &omap54xx_mcspi_hwmod_class,
1190         .clkdm_name     = "l4per_clkdm",
1191         .main_clk       = "func_48m_fclk",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_SWCTRL,
1197                 },
1198         },
1199         .dev_attr       = &mcspi2_dev_attr,
1200 };
1201
1202 /* mcspi3 */
1203 /* mcspi3 dev_attr */
1204 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1205         .num_chipselect = 2,
1206 };
1207
1208 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1209         .name           = "mcspi3",
1210         .class          = &omap54xx_mcspi_hwmod_class,
1211         .clkdm_name     = "l4per_clkdm",
1212         .main_clk       = "func_48m_fclk",
1213         .prcm = {
1214                 .omap4 = {
1215                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1216                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1217                         .modulemode   = MODULEMODE_SWCTRL,
1218                 },
1219         },
1220         .dev_attr       = &mcspi3_dev_attr,
1221 };
1222
1223 /* mcspi4 */
1224 /* mcspi4 dev_attr */
1225 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1226         .num_chipselect = 1,
1227 };
1228
1229 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1230         .name           = "mcspi4",
1231         .class          = &omap54xx_mcspi_hwmod_class,
1232         .clkdm_name     = "l4per_clkdm",
1233         .main_clk       = "func_48m_fclk",
1234         .prcm = {
1235                 .omap4 = {
1236                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1237                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1238                         .modulemode   = MODULEMODE_SWCTRL,
1239                 },
1240         },
1241         .dev_attr       = &mcspi4_dev_attr,
1242 };
1243
1244 /*
1245  * 'mmc' class
1246  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1247  */
1248
1249 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1250         .rev_offs       = 0x0000,
1251         .sysc_offs      = 0x0010,
1252         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1253                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1254                            SYSC_HAS_SOFTRESET),
1255         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1256                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1257                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1258         .sysc_fields    = &omap_hwmod_sysc_type2,
1259 };
1260
1261 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1262         .name   = "mmc",
1263         .sysc   = &omap54xx_mmc_sysc,
1264 };
1265
1266 /* mmc1 */
1267 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1268         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1269 };
1270
1271 /* mmc1 dev_attr */
1272 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1273         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1274 };
1275
1276 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1277         .name           = "mmc1",
1278         .class          = &omap54xx_mmc_hwmod_class,
1279         .clkdm_name     = "l3init_clkdm",
1280         .main_clk       = "mmc1_fclk",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_SWCTRL,
1286                 },
1287         },
1288         .opt_clks       = mmc1_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1290         .dev_attr       = &mmc1_dev_attr,
1291 };
1292
1293 /* mmc2 */
1294 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1295         .name           = "mmc2",
1296         .class          = &omap54xx_mmc_hwmod_class,
1297         .clkdm_name     = "l3init_clkdm",
1298         .main_clk       = "mmc2_fclk",
1299         .prcm = {
1300                 .omap4 = {
1301                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1302                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1303                         .modulemode   = MODULEMODE_SWCTRL,
1304                 },
1305         },
1306 };
1307
1308 /* mmc3 */
1309 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1310         .name           = "mmc3",
1311         .class          = &omap54xx_mmc_hwmod_class,
1312         .clkdm_name     = "l4per_clkdm",
1313         .main_clk       = "func_48m_fclk",
1314         .prcm = {
1315                 .omap4 = {
1316                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1317                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1318                         .modulemode   = MODULEMODE_SWCTRL,
1319                 },
1320         },
1321 };
1322
1323 /* mmc4 */
1324 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1325         .name           = "mmc4",
1326         .class          = &omap54xx_mmc_hwmod_class,
1327         .clkdm_name     = "l4per_clkdm",
1328         .main_clk       = "func_48m_fclk",
1329         .prcm = {
1330                 .omap4 = {
1331                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1332                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1333                         .modulemode   = MODULEMODE_SWCTRL,
1334                 },
1335         },
1336 };
1337
1338 /* mmc5 */
1339 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1340         .name           = "mmc5",
1341         .class          = &omap54xx_mmc_hwmod_class,
1342         .clkdm_name     = "l4per_clkdm",
1343         .main_clk       = "func_96m_fclk",
1344         .prcm = {
1345                 .omap4 = {
1346                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1347                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1348                         .modulemode   = MODULEMODE_SWCTRL,
1349                 },
1350         },
1351 };
1352
1353 /*
1354  * 'mmu' class
1355  * The memory management unit performs virtual to physical address translation
1356  * for its requestors.
1357  */
1358
1359 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1360         .rev_offs       = 0x0000,
1361         .sysc_offs      = 0x0010,
1362         .syss_offs      = 0x0014,
1363         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1364                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1365                            SYSS_HAS_RESET_STATUS),
1366         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1367         .sysc_fields    = &omap_hwmod_sysc_type1,
1368 };
1369
1370 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1371         .name = "mmu",
1372         .sysc = &omap54xx_mmu_sysc,
1373 };
1374
1375 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1376         { .name = "mmu_cache", .rst_shift = 1 },
1377 };
1378
1379 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1380         .name           = "mmu_dsp",
1381         .class          = &omap54xx_mmu_hwmod_class,
1382         .clkdm_name     = "dsp_clkdm",
1383         .rst_lines      = omap54xx_mmu_dsp_resets,
1384         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1385         .main_clk       = "dpll_iva_h11x2_ck",
1386         .prcm = {
1387                 .omap4 = {
1388                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1389                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1390                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1391                         .modulemode   = MODULEMODE_HWCTRL,
1392                 },
1393         },
1394 };
1395
1396 /* mmu ipu */
1397 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1398         { .name = "mmu_cache", .rst_shift = 2 },
1399 };
1400
1401 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1402         .name           = "mmu_ipu",
1403         .class          = &omap54xx_mmu_hwmod_class,
1404         .clkdm_name     = "ipu_clkdm",
1405         .rst_lines      = omap54xx_mmu_ipu_resets,
1406         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1407         .main_clk       = "dpll_core_h22x2_ck",
1408         .prcm = {
1409                 .omap4 = {
1410                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1411                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1412                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_HWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'mpu' class
1420  * mpu sub-system
1421  */
1422
1423 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1424         .name   = "mpu",
1425 };
1426
1427 /* mpu */
1428 static struct omap_hwmod omap54xx_mpu_hwmod = {
1429         .name           = "mpu",
1430         .class          = &omap54xx_mpu_hwmod_class,
1431         .clkdm_name     = "mpu_clkdm",
1432         .flags          = HWMOD_INIT_NO_IDLE,
1433         .main_clk       = "dpll_mpu_m2_ck",
1434         .prcm = {
1435                 .omap4 = {
1436                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1437                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1438                 },
1439         },
1440 };
1441
1442 /*
1443  * 'spinlock' class
1444  * spinlock provides hardware assistance for synchronizing the processes
1445  * running on multiple processors
1446  */
1447
1448 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1449         .rev_offs       = 0x0000,
1450         .sysc_offs      = 0x0010,
1451         .syss_offs      = 0x0014,
1452         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1453                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1454                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1455         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1456         .sysc_fields    = &omap_hwmod_sysc_type1,
1457 };
1458
1459 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1460         .name   = "spinlock",
1461         .sysc   = &omap54xx_spinlock_sysc,
1462 };
1463
1464 /* spinlock */
1465 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1466         .name           = "spinlock",
1467         .class          = &omap54xx_spinlock_hwmod_class,
1468         .clkdm_name     = "l4cfg_clkdm",
1469         .prcm = {
1470                 .omap4 = {
1471                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1472                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1473                 },
1474         },
1475 };
1476
1477 /*
1478  * 'ocp2scp' class
1479  * bridge to transform ocp interface protocol to scp (serial control port)
1480  * protocol
1481  */
1482
1483 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1484         .rev_offs       = 0x0000,
1485         .sysc_offs      = 0x0010,
1486         .syss_offs      = 0x0014,
1487         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1488                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1490         .sysc_fields    = &omap_hwmod_sysc_type1,
1491 };
1492
1493 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1494         .name   = "ocp2scp",
1495         .sysc   = &omap54xx_ocp2scp_sysc,
1496 };
1497
1498 /* ocp2scp1 */
1499 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1500         .name           = "ocp2scp1",
1501         .class          = &omap54xx_ocp2scp_hwmod_class,
1502         .clkdm_name     = "l3init_clkdm",
1503         .main_clk       = "l4_root_clk_div",
1504         .prcm = {
1505                 .omap4 = {
1506                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1507                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1508                         .modulemode   = MODULEMODE_HWCTRL,
1509                 },
1510         },
1511 };
1512
1513 /*
1514  * 'timer' class
1515  * general purpose timer module with accurate 1ms tick
1516  * This class contains several variants: ['timer_1ms', 'timer']
1517  */
1518
1519 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1520         .rev_offs       = 0x0000,
1521         .sysc_offs      = 0x0010,
1522         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1523                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1524         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1525                            SIDLE_SMART_WKUP),
1526         .sysc_fields    = &omap_hwmod_sysc_type2,
1527         .clockact       = CLOCKACT_TEST_ICLK,
1528 };
1529
1530 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1531         .name   = "timer",
1532         .sysc   = &omap54xx_timer_1ms_sysc,
1533 };
1534
1535 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1536         .rev_offs       = 0x0000,
1537         .sysc_offs      = 0x0010,
1538         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1539                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1540         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1541                            SIDLE_SMART_WKUP),
1542         .sysc_fields    = &omap_hwmod_sysc_type2,
1543 };
1544
1545 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1546         .name   = "timer",
1547         .sysc   = &omap54xx_timer_sysc,
1548 };
1549
1550 /* timer1 */
1551 static struct omap_hwmod omap54xx_timer1_hwmod = {
1552         .name           = "timer1",
1553         .class          = &omap54xx_timer_1ms_hwmod_class,
1554         .clkdm_name     = "wkupaon_clkdm",
1555         .main_clk       = "timer1_gfclk_mux",
1556         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1557         .prcm = {
1558                 .omap4 = {
1559                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1560                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1561                         .modulemode   = MODULEMODE_SWCTRL,
1562                 },
1563         },
1564 };
1565
1566 /* timer2 */
1567 static struct omap_hwmod omap54xx_timer2_hwmod = {
1568         .name           = "timer2",
1569         .class          = &omap54xx_timer_1ms_hwmod_class,
1570         .clkdm_name     = "l4per_clkdm",
1571         .main_clk       = "timer2_gfclk_mux",
1572         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1573         .prcm = {
1574                 .omap4 = {
1575                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1576                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1577                         .modulemode   = MODULEMODE_SWCTRL,
1578                 },
1579         },
1580 };
1581
1582 /* timer3 */
1583 static struct omap_hwmod omap54xx_timer3_hwmod = {
1584         .name           = "timer3",
1585         .class          = &omap54xx_timer_hwmod_class,
1586         .clkdm_name     = "l4per_clkdm",
1587         .main_clk       = "timer3_gfclk_mux",
1588         .prcm = {
1589                 .omap4 = {
1590                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1591                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1592                         .modulemode   = MODULEMODE_SWCTRL,
1593                 },
1594         },
1595 };
1596
1597 /* timer4 */
1598 static struct omap_hwmod omap54xx_timer4_hwmod = {
1599         .name           = "timer4",
1600         .class          = &omap54xx_timer_hwmod_class,
1601         .clkdm_name     = "l4per_clkdm",
1602         .main_clk       = "timer4_gfclk_mux",
1603         .prcm = {
1604                 .omap4 = {
1605                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1606                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1607                         .modulemode   = MODULEMODE_SWCTRL,
1608                 },
1609         },
1610 };
1611
1612 /* timer5 */
1613 static struct omap_hwmod omap54xx_timer5_hwmod = {
1614         .name           = "timer5",
1615         .class          = &omap54xx_timer_hwmod_class,
1616         .clkdm_name     = "abe_clkdm",
1617         .main_clk       = "timer5_gfclk_mux",
1618         .prcm = {
1619                 .omap4 = {
1620                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1621                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1622                         .modulemode   = MODULEMODE_SWCTRL,
1623                 },
1624         },
1625 };
1626
1627 /* timer6 */
1628 static struct omap_hwmod omap54xx_timer6_hwmod = {
1629         .name           = "timer6",
1630         .class          = &omap54xx_timer_hwmod_class,
1631         .clkdm_name     = "abe_clkdm",
1632         .main_clk       = "timer6_gfclk_mux",
1633         .prcm = {
1634                 .omap4 = {
1635                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1636                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1637                         .modulemode   = MODULEMODE_SWCTRL,
1638                 },
1639         },
1640 };
1641
1642 /* timer7 */
1643 static struct omap_hwmod omap54xx_timer7_hwmod = {
1644         .name           = "timer7",
1645         .class          = &omap54xx_timer_hwmod_class,
1646         .clkdm_name     = "abe_clkdm",
1647         .main_clk       = "timer7_gfclk_mux",
1648         .prcm = {
1649                 .omap4 = {
1650                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1651                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1652                         .modulemode   = MODULEMODE_SWCTRL,
1653                 },
1654         },
1655 };
1656
1657 /* timer8 */
1658 static struct omap_hwmod omap54xx_timer8_hwmod = {
1659         .name           = "timer8",
1660         .class          = &omap54xx_timer_hwmod_class,
1661         .clkdm_name     = "abe_clkdm",
1662         .main_clk       = "timer8_gfclk_mux",
1663         .prcm = {
1664                 .omap4 = {
1665                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1666                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1667                         .modulemode   = MODULEMODE_SWCTRL,
1668                 },
1669         },
1670 };
1671
1672 /* timer9 */
1673 static struct omap_hwmod omap54xx_timer9_hwmod = {
1674         .name           = "timer9",
1675         .class          = &omap54xx_timer_hwmod_class,
1676         .clkdm_name     = "l4per_clkdm",
1677         .main_clk       = "timer9_gfclk_mux",
1678         .prcm = {
1679                 .omap4 = {
1680                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1681                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1682                         .modulemode   = MODULEMODE_SWCTRL,
1683                 },
1684         },
1685 };
1686
1687 /* timer10 */
1688 static struct omap_hwmod omap54xx_timer10_hwmod = {
1689         .name           = "timer10",
1690         .class          = &omap54xx_timer_1ms_hwmod_class,
1691         .clkdm_name     = "l4per_clkdm",
1692         .main_clk       = "timer10_gfclk_mux",
1693         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1694         .prcm = {
1695                 .omap4 = {
1696                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1697                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1698                         .modulemode   = MODULEMODE_SWCTRL,
1699                 },
1700         },
1701 };
1702
1703 /* timer11 */
1704 static struct omap_hwmod omap54xx_timer11_hwmod = {
1705         .name           = "timer11",
1706         .class          = &omap54xx_timer_hwmod_class,
1707         .clkdm_name     = "l4per_clkdm",
1708         .main_clk       = "timer11_gfclk_mux",
1709         .prcm = {
1710                 .omap4 = {
1711                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1712                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1713                         .modulemode   = MODULEMODE_SWCTRL,
1714                 },
1715         },
1716 };
1717
1718 /*
1719  * 'uart' class
1720  * universal asynchronous receiver/transmitter (uart)
1721  */
1722
1723 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1724         .rev_offs       = 0x0050,
1725         .sysc_offs      = 0x0054,
1726         .syss_offs      = 0x0058,
1727         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1728                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1729                            SYSS_HAS_RESET_STATUS),
1730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1731                            SIDLE_SMART_WKUP),
1732         .sysc_fields    = &omap_hwmod_sysc_type1,
1733 };
1734
1735 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1736         .name   = "uart",
1737         .sysc   = &omap54xx_uart_sysc,
1738 };
1739
1740 /* uart1 */
1741 static struct omap_hwmod omap54xx_uart1_hwmod = {
1742         .name           = "uart1",
1743         .class          = &omap54xx_uart_hwmod_class,
1744         .clkdm_name     = "l4per_clkdm",
1745         .main_clk       = "func_48m_fclk",
1746         .prcm = {
1747                 .omap4 = {
1748                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1749                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1750                         .modulemode   = MODULEMODE_SWCTRL,
1751                 },
1752         },
1753 };
1754
1755 /* uart2 */
1756 static struct omap_hwmod omap54xx_uart2_hwmod = {
1757         .name           = "uart2",
1758         .class          = &omap54xx_uart_hwmod_class,
1759         .clkdm_name     = "l4per_clkdm",
1760         .main_clk       = "func_48m_fclk",
1761         .prcm = {
1762                 .omap4 = {
1763                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1764                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1765                         .modulemode   = MODULEMODE_SWCTRL,
1766                 },
1767         },
1768 };
1769
1770 /* uart3 */
1771 static struct omap_hwmod omap54xx_uart3_hwmod = {
1772         .name           = "uart3",
1773         .class          = &omap54xx_uart_hwmod_class,
1774         .clkdm_name     = "l4per_clkdm",
1775         .flags          = DEBUG_OMAP4UART3_FLAGS,
1776         .main_clk       = "func_48m_fclk",
1777         .prcm = {
1778                 .omap4 = {
1779                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1780                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1781                         .modulemode   = MODULEMODE_SWCTRL,
1782                 },
1783         },
1784 };
1785
1786 /* uart4 */
1787 static struct omap_hwmod omap54xx_uart4_hwmod = {
1788         .name           = "uart4",
1789         .class          = &omap54xx_uart_hwmod_class,
1790         .clkdm_name     = "l4per_clkdm",
1791         .flags          = DEBUG_OMAP4UART4_FLAGS,
1792         .main_clk       = "func_48m_fclk",
1793         .prcm = {
1794                 .omap4 = {
1795                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1796                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1797                         .modulemode   = MODULEMODE_SWCTRL,
1798                 },
1799         },
1800 };
1801
1802 /* uart5 */
1803 static struct omap_hwmod omap54xx_uart5_hwmod = {
1804         .name           = "uart5",
1805         .class          = &omap54xx_uart_hwmod_class,
1806         .clkdm_name     = "l4per_clkdm",
1807         .main_clk       = "func_48m_fclk",
1808         .prcm = {
1809                 .omap4 = {
1810                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1811                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1812                         .modulemode   = MODULEMODE_SWCTRL,
1813                 },
1814         },
1815 };
1816
1817 /* uart6 */
1818 static struct omap_hwmod omap54xx_uart6_hwmod = {
1819         .name           = "uart6",
1820         .class          = &omap54xx_uart_hwmod_class,
1821         .clkdm_name     = "l4per_clkdm",
1822         .main_clk       = "func_48m_fclk",
1823         .prcm = {
1824                 .omap4 = {
1825                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1826                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1827                         .modulemode   = MODULEMODE_SWCTRL,
1828                 },
1829         },
1830 };
1831
1832 /*
1833  * 'usb_host_hs' class
1834  * high-speed multi-port usb host controller
1835  */
1836
1837 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1838         .rev_offs       = 0x0000,
1839         .sysc_offs      = 0x0010,
1840         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1841                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1842                            SYSC_HAS_RESET_STATUS),
1843         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1844                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1845                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1846         .sysc_fields    = &omap_hwmod_sysc_type2,
1847 };
1848
1849 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1850         .name   = "usb_host_hs",
1851         .sysc   = &omap54xx_usb_host_hs_sysc,
1852 };
1853
1854 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1855         .name           = "usb_host_hs",
1856         .class          = &omap54xx_usb_host_hs_hwmod_class,
1857         .clkdm_name     = "l3init_clkdm",
1858         /*
1859          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1860          * id: i660
1861          *
1862          * Description:
1863          * In the following configuration :
1864          * - USBHOST module is set to smart-idle mode
1865          * - PRCM asserts idle_req to the USBHOST module ( This typically
1866          *   happens when the system is going to a low power mode : all ports
1867          *   have been suspended, the master part of the USBHOST module has
1868          *   entered the standby state, and SW has cut the functional clocks)
1869          * - an USBHOST interrupt occurs before the module is able to answer
1870          *   idle_ack, typically a remote wakeup IRQ.
1871          * Then the USB HOST module will enter a deadlock situation where it
1872          * is no more accessible nor functional.
1873          *
1874          * Workaround:
1875          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1876          */
1877
1878         /*
1879          * Errata: USB host EHCI may stall when entering smart-standby mode
1880          * Id: i571
1881          *
1882          * Description:
1883          * When the USBHOST module is set to smart-standby mode, and when it is
1884          * ready to enter the standby state (i.e. all ports are suspended and
1885          * all attached devices are in suspend mode), then it can wrongly assert
1886          * the Mstandby signal too early while there are still some residual OCP
1887          * transactions ongoing. If this condition occurs, the internal state
1888          * machine may go to an undefined state and the USB link may be stuck
1889          * upon the next resume.
1890          *
1891          * Workaround:
1892          * Don't use smart standby; use only force standby,
1893          * hence HWMOD_SWSUP_MSTANDBY
1894          */
1895
1896         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1897         .main_clk       = "l3init_60m_fclk",
1898         .prcm = {
1899                 .omap4 = {
1900                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1901                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1902                         .modulemode   = MODULEMODE_SWCTRL,
1903                 },
1904         },
1905 };
1906
1907 /*
1908  * 'usb_tll_hs' class
1909  * usb_tll_hs module is the adapter on the usb_host_hs ports
1910  */
1911
1912 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1913         .rev_offs       = 0x0000,
1914         .sysc_offs      = 0x0010,
1915         .syss_offs      = 0x0014,
1916         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1917                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1918                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1919         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1920         .sysc_fields    = &omap_hwmod_sysc_type1,
1921 };
1922
1923 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1924         .name   = "usb_tll_hs",
1925         .sysc   = &omap54xx_usb_tll_hs_sysc,
1926 };
1927
1928 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1929         .name           = "usb_tll_hs",
1930         .class          = &omap54xx_usb_tll_hs_hwmod_class,
1931         .clkdm_name     = "l3init_clkdm",
1932         .main_clk       = "l4_root_clk_div",
1933         .prcm = {
1934                 .omap4 = {
1935                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1936                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1937                         .modulemode   = MODULEMODE_HWCTRL,
1938                 },
1939         },
1940 };
1941
1942 /*
1943  * 'usb_otg_ss' class
1944  * 2.0 super speed (usb_otg_ss) controller
1945  */
1946
1947 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1948         .rev_offs       = 0x0000,
1949         .sysc_offs      = 0x0010,
1950         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1951                            SYSC_HAS_SIDLEMODE),
1952         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1953                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1954                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1955         .sysc_fields    = &omap_hwmod_sysc_type2,
1956 };
1957
1958 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1959         .name   = "usb_otg_ss",
1960         .sysc   = &omap54xx_usb_otg_ss_sysc,
1961 };
1962
1963 /* usb_otg_ss */
1964 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1965         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1966 };
1967
1968 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1969         .name           = "usb_otg_ss",
1970         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1971         .clkdm_name     = "l3init_clkdm",
1972         .flags          = HWMOD_SWSUP_SIDLE,
1973         .main_clk       = "dpll_core_h13x2_ck",
1974         .prcm = {
1975                 .omap4 = {
1976                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1977                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1978                         .modulemode   = MODULEMODE_HWCTRL,
1979                 },
1980         },
1981         .opt_clks       = usb_otg_ss_opt_clks,
1982         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1983 };
1984
1985 /*
1986  * 'wd_timer' class
1987  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1988  * overflow condition
1989  */
1990
1991 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1992         .rev_offs       = 0x0000,
1993         .sysc_offs      = 0x0010,
1994         .syss_offs      = 0x0014,
1995         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1996                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1997         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1998                            SIDLE_SMART_WKUP),
1999         .sysc_fields    = &omap_hwmod_sysc_type1,
2000 };
2001
2002 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
2003         .name           = "wd_timer",
2004         .sysc           = &omap54xx_wd_timer_sysc,
2005         .pre_shutdown   = &omap2_wd_timer_disable,
2006 };
2007
2008 /* wd_timer2 */
2009 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2010         .name           = "wd_timer2",
2011         .class          = &omap54xx_wd_timer_hwmod_class,
2012         .clkdm_name     = "wkupaon_clkdm",
2013         .main_clk       = "sys_32k_ck",
2014         .prcm = {
2015                 .omap4 = {
2016                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2017                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2018                         .modulemode   = MODULEMODE_SWCTRL,
2019                 },
2020         },
2021 };
2022
2023 /*
2024  * 'ocp2scp' class
2025  * bridge to transform ocp interface protocol to scp (serial control port)
2026  * protocol
2027  */
2028 /* ocp2scp3 */
2029 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2030 /* l4_cfg -> ocp2scp3 */
2031 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2032         .master         = &omap54xx_l4_cfg_hwmod,
2033         .slave          = &omap54xx_ocp2scp3_hwmod,
2034         .clk            = "l4_root_clk_div",
2035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2036 };
2037
2038 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2039         .name           = "ocp2scp3",
2040         .class          = &omap54xx_ocp2scp_hwmod_class,
2041         .clkdm_name     = "l3init_clkdm",
2042         .prcm = {
2043                 .omap4 = {
2044                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2045                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2046                         .modulemode   = MODULEMODE_HWCTRL,
2047                 },
2048         },
2049 };
2050
2051 /*
2052  * 'sata' class
2053  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
2054  */
2055
2056 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2057         .sysc_offs      = 0x0000,
2058         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2059         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2060                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2061                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2062         .sysc_fields    = &omap_hwmod_sysc_type2,
2063 };
2064
2065 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2066         .name   = "sata",
2067         .sysc   = &omap54xx_sata_sysc,
2068 };
2069
2070 /* sata */
2071 static struct omap_hwmod omap54xx_sata_hwmod = {
2072         .name           = "sata",
2073         .class          = &omap54xx_sata_hwmod_class,
2074         .clkdm_name     = "l3init_clkdm",
2075         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2076         .main_clk       = "func_48m_fclk",
2077         .mpu_rt_idx     = 1,
2078         .prcm = {
2079                 .omap4 = {
2080                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2081                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2082                         .modulemode   = MODULEMODE_SWCTRL,
2083                 },
2084         },
2085 };
2086
2087 /* l4_cfg -> sata */
2088 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2089         .master         = &omap54xx_l4_cfg_hwmod,
2090         .slave          = &omap54xx_sata_hwmod,
2091         .clk            = "l3_iclk_div",
2092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2093 };
2094
2095 /*
2096  * Interfaces
2097  */
2098
2099 /* l3_main_1 -> dmm */
2100 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2101         .master         = &omap54xx_l3_main_1_hwmod,
2102         .slave          = &omap54xx_dmm_hwmod,
2103         .clk            = "l3_iclk_div",
2104         .user           = OCP_USER_SDMA,
2105 };
2106
2107 /* l3_main_3 -> l3_instr */
2108 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2109         .master         = &omap54xx_l3_main_3_hwmod,
2110         .slave          = &omap54xx_l3_instr_hwmod,
2111         .clk            = "l3_iclk_div",
2112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2113 };
2114
2115 /* l3_main_2 -> l3_main_1 */
2116 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2117         .master         = &omap54xx_l3_main_2_hwmod,
2118         .slave          = &omap54xx_l3_main_1_hwmod,
2119         .clk            = "l3_iclk_div",
2120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2121 };
2122
2123 /* l4_cfg -> l3_main_1 */
2124 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2125         .master         = &omap54xx_l4_cfg_hwmod,
2126         .slave          = &omap54xx_l3_main_1_hwmod,
2127         .clk            = "l3_iclk_div",
2128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2129 };
2130
2131 /* l4_cfg -> mmu_dsp */
2132 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2133         .master         = &omap54xx_l4_cfg_hwmod,
2134         .slave          = &omap54xx_mmu_dsp_hwmod,
2135         .clk            = "l4_root_clk_div",
2136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2137 };
2138
2139 /* mpu -> l3_main_1 */
2140 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2141         .master         = &omap54xx_mpu_hwmod,
2142         .slave          = &omap54xx_l3_main_1_hwmod,
2143         .clk            = "l3_iclk_div",
2144         .user           = OCP_USER_MPU,
2145 };
2146
2147 /* l3_main_1 -> l3_main_2 */
2148 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2149         .master         = &omap54xx_l3_main_1_hwmod,
2150         .slave          = &omap54xx_l3_main_2_hwmod,
2151         .clk            = "l3_iclk_div",
2152         .user           = OCP_USER_MPU,
2153 };
2154
2155 /* l4_cfg -> l3_main_2 */
2156 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2157         .master         = &omap54xx_l4_cfg_hwmod,
2158         .slave          = &omap54xx_l3_main_2_hwmod,
2159         .clk            = "l3_iclk_div",
2160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2161 };
2162
2163 /* l3_main_2 -> mmu_ipu */
2164 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2165         .master         = &omap54xx_l3_main_2_hwmod,
2166         .slave          = &omap54xx_mmu_ipu_hwmod,
2167         .clk            = "l3_iclk_div",
2168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2169 };
2170
2171 /* l3_main_1 -> l3_main_3 */
2172 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2173         .master         = &omap54xx_l3_main_1_hwmod,
2174         .slave          = &omap54xx_l3_main_3_hwmod,
2175         .clk            = "l3_iclk_div",
2176         .user           = OCP_USER_MPU,
2177 };
2178
2179 /* l3_main_2 -> l3_main_3 */
2180 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2181         .master         = &omap54xx_l3_main_2_hwmod,
2182         .slave          = &omap54xx_l3_main_3_hwmod,
2183         .clk            = "l3_iclk_div",
2184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2185 };
2186
2187 /* l4_cfg -> l3_main_3 */
2188 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2189         .master         = &omap54xx_l4_cfg_hwmod,
2190         .slave          = &omap54xx_l3_main_3_hwmod,
2191         .clk            = "l3_iclk_div",
2192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2193 };
2194
2195 /* l3_main_1 -> l4_abe */
2196 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2197         .master         = &omap54xx_l3_main_1_hwmod,
2198         .slave          = &omap54xx_l4_abe_hwmod,
2199         .clk            = "abe_iclk",
2200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2201 };
2202
2203 /* mpu -> l4_abe */
2204 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2205         .master         = &omap54xx_mpu_hwmod,
2206         .slave          = &omap54xx_l4_abe_hwmod,
2207         .clk            = "abe_iclk",
2208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2209 };
2210
2211 /* l3_main_1 -> l4_cfg */
2212 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2213         .master         = &omap54xx_l3_main_1_hwmod,
2214         .slave          = &omap54xx_l4_cfg_hwmod,
2215         .clk            = "l4_root_clk_div",
2216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2217 };
2218
2219 /* l3_main_2 -> l4_per */
2220 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2221         .master         = &omap54xx_l3_main_2_hwmod,
2222         .slave          = &omap54xx_l4_per_hwmod,
2223         .clk            = "l4_root_clk_div",
2224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2225 };
2226
2227 /* l3_main_1 -> l4_wkup */
2228 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2229         .master         = &omap54xx_l3_main_1_hwmod,
2230         .slave          = &omap54xx_l4_wkup_hwmod,
2231         .clk            = "wkupaon_iclk_mux",
2232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2233 };
2234
2235 /* mpu -> mpu_private */
2236 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2237         .master         = &omap54xx_mpu_hwmod,
2238         .slave          = &omap54xx_mpu_private_hwmod,
2239         .clk            = "l3_iclk_div",
2240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2241 };
2242
2243 /* l4_wkup -> counter_32k */
2244 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2245         .master         = &omap54xx_l4_wkup_hwmod,
2246         .slave          = &omap54xx_counter_32k_hwmod,
2247         .clk            = "wkupaon_iclk_mux",
2248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2249 };
2250
2251 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
2252         {
2253                 .pa_start       = 0x4a056000,
2254                 .pa_end         = 0x4a056fff,
2255                 .flags          = ADDR_TYPE_RT
2256         },
2257         { }
2258 };
2259
2260 /* l4_cfg -> dma_system */
2261 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2262         .master         = &omap54xx_l4_cfg_hwmod,
2263         .slave          = &omap54xx_dma_system_hwmod,
2264         .clk            = "l4_root_clk_div",
2265         .addr           = omap54xx_dma_system_addrs,
2266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268
2269 /* l4_abe -> dmic */
2270 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2271         .master         = &omap54xx_l4_abe_hwmod,
2272         .slave          = &omap54xx_dmic_hwmod,
2273         .clk            = "abe_iclk",
2274         .user           = OCP_USER_MPU,
2275 };
2276
2277 /* l3_main_2 -> dss */
2278 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2279         .master         = &omap54xx_l3_main_2_hwmod,
2280         .slave          = &omap54xx_dss_hwmod,
2281         .clk            = "l3_iclk_div",
2282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284
2285 /* l3_main_2 -> dss_dispc */
2286 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2287         .master         = &omap54xx_l3_main_2_hwmod,
2288         .slave          = &omap54xx_dss_dispc_hwmod,
2289         .clk            = "l3_iclk_div",
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292
2293 /* l3_main_2 -> dss_dsi1_a */
2294 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2295         .master         = &omap54xx_l3_main_2_hwmod,
2296         .slave          = &omap54xx_dss_dsi1_a_hwmod,
2297         .clk            = "l3_iclk_div",
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* l3_main_2 -> dss_dsi1_c */
2302 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2303         .master         = &omap54xx_l3_main_2_hwmod,
2304         .slave          = &omap54xx_dss_dsi1_c_hwmod,
2305         .clk            = "l3_iclk_div",
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* l3_main_2 -> dss_hdmi */
2310 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2311         .master         = &omap54xx_l3_main_2_hwmod,
2312         .slave          = &omap54xx_dss_hdmi_hwmod,
2313         .clk            = "l3_iclk_div",
2314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2315 };
2316
2317 /* l3_main_2 -> dss_rfbi */
2318 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2319         .master         = &omap54xx_l3_main_2_hwmod,
2320         .slave          = &omap54xx_dss_rfbi_hwmod,
2321         .clk            = "l3_iclk_div",
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 /* mpu -> emif1 */
2326 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2327         .master         = &omap54xx_mpu_hwmod,
2328         .slave          = &omap54xx_emif1_hwmod,
2329         .clk            = "dpll_core_h11x2_ck",
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332
2333 /* mpu -> emif2 */
2334 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2335         .master         = &omap54xx_mpu_hwmod,
2336         .slave          = &omap54xx_emif2_hwmod,
2337         .clk            = "dpll_core_h11x2_ck",
2338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2339 };
2340
2341 /* l4_wkup -> gpio1 */
2342 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2343         .master         = &omap54xx_l4_wkup_hwmod,
2344         .slave          = &omap54xx_gpio1_hwmod,
2345         .clk            = "wkupaon_iclk_mux",
2346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2347 };
2348
2349 /* l4_per -> gpio2 */
2350 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2351         .master         = &omap54xx_l4_per_hwmod,
2352         .slave          = &omap54xx_gpio2_hwmod,
2353         .clk            = "l4_root_clk_div",
2354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356
2357 /* l4_per -> gpio3 */
2358 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2359         .master         = &omap54xx_l4_per_hwmod,
2360         .slave          = &omap54xx_gpio3_hwmod,
2361         .clk            = "l4_root_clk_div",
2362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2363 };
2364
2365 /* l4_per -> gpio4 */
2366 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2367         .master         = &omap54xx_l4_per_hwmod,
2368         .slave          = &omap54xx_gpio4_hwmod,
2369         .clk            = "l4_root_clk_div",
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373 /* l4_per -> gpio5 */
2374 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2375         .master         = &omap54xx_l4_per_hwmod,
2376         .slave          = &omap54xx_gpio5_hwmod,
2377         .clk            = "l4_root_clk_div",
2378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380
2381 /* l4_per -> gpio6 */
2382 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2383         .master         = &omap54xx_l4_per_hwmod,
2384         .slave          = &omap54xx_gpio6_hwmod,
2385         .clk            = "l4_root_clk_div",
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389 /* l4_per -> gpio7 */
2390 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2391         .master         = &omap54xx_l4_per_hwmod,
2392         .slave          = &omap54xx_gpio7_hwmod,
2393         .clk            = "l4_root_clk_div",
2394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2395 };
2396
2397 /* l4_per -> gpio8 */
2398 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2399         .master         = &omap54xx_l4_per_hwmod,
2400         .slave          = &omap54xx_gpio8_hwmod,
2401         .clk            = "l4_root_clk_div",
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* l4_per -> i2c1 */
2406 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2407         .master         = &omap54xx_l4_per_hwmod,
2408         .slave          = &omap54xx_i2c1_hwmod,
2409         .clk            = "l4_root_clk_div",
2410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2411 };
2412
2413 /* l4_per -> i2c2 */
2414 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2415         .master         = &omap54xx_l4_per_hwmod,
2416         .slave          = &omap54xx_i2c2_hwmod,
2417         .clk            = "l4_root_clk_div",
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420
2421 /* l4_per -> i2c3 */
2422 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2423         .master         = &omap54xx_l4_per_hwmod,
2424         .slave          = &omap54xx_i2c3_hwmod,
2425         .clk            = "l4_root_clk_div",
2426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 /* l4_per -> i2c4 */
2430 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2431         .master         = &omap54xx_l4_per_hwmod,
2432         .slave          = &omap54xx_i2c4_hwmod,
2433         .clk            = "l4_root_clk_div",
2434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436
2437 /* l4_per -> i2c5 */
2438 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2439         .master         = &omap54xx_l4_per_hwmod,
2440         .slave          = &omap54xx_i2c5_hwmod,
2441         .clk            = "l4_root_clk_div",
2442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444
2445 /* l4_wkup -> kbd */
2446 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2447         .master         = &omap54xx_l4_wkup_hwmod,
2448         .slave          = &omap54xx_kbd_hwmod,
2449         .clk            = "wkupaon_iclk_mux",
2450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2451 };
2452
2453 /* l4_cfg -> mailbox */
2454 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2455         .master         = &omap54xx_l4_cfg_hwmod,
2456         .slave          = &omap54xx_mailbox_hwmod,
2457         .clk            = "l4_root_clk_div",
2458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2459 };
2460
2461 /* l4_abe -> mcbsp1 */
2462 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2463         .master         = &omap54xx_l4_abe_hwmod,
2464         .slave          = &omap54xx_mcbsp1_hwmod,
2465         .clk            = "abe_iclk",
2466         .user           = OCP_USER_MPU,
2467 };
2468
2469 /* l4_abe -> mcbsp2 */
2470 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2471         .master         = &omap54xx_l4_abe_hwmod,
2472         .slave          = &omap54xx_mcbsp2_hwmod,
2473         .clk            = "abe_iclk",
2474         .user           = OCP_USER_MPU,
2475 };
2476
2477 /* l4_abe -> mcbsp3 */
2478 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2479         .master         = &omap54xx_l4_abe_hwmod,
2480         .slave          = &omap54xx_mcbsp3_hwmod,
2481         .clk            = "abe_iclk",
2482         .user           = OCP_USER_MPU,
2483 };
2484
2485 /* l4_abe -> mcpdm */
2486 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2487         .master         = &omap54xx_l4_abe_hwmod,
2488         .slave          = &omap54xx_mcpdm_hwmod,
2489         .clk            = "abe_iclk",
2490         .user           = OCP_USER_MPU,
2491 };
2492
2493 /* l4_per -> mcspi1 */
2494 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2495         .master         = &omap54xx_l4_per_hwmod,
2496         .slave          = &omap54xx_mcspi1_hwmod,
2497         .clk            = "l4_root_clk_div",
2498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2499 };
2500
2501 /* l4_per -> mcspi2 */
2502 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2503         .master         = &omap54xx_l4_per_hwmod,
2504         .slave          = &omap54xx_mcspi2_hwmod,
2505         .clk            = "l4_root_clk_div",
2506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2507 };
2508
2509 /* l4_per -> mcspi3 */
2510 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2511         .master         = &omap54xx_l4_per_hwmod,
2512         .slave          = &omap54xx_mcspi3_hwmod,
2513         .clk            = "l4_root_clk_div",
2514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2515 };
2516
2517 /* l4_per -> mcspi4 */
2518 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2519         .master         = &omap54xx_l4_per_hwmod,
2520         .slave          = &omap54xx_mcspi4_hwmod,
2521         .clk            = "l4_root_clk_div",
2522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2523 };
2524
2525 /* l4_per -> mmc1 */
2526 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2527         .master         = &omap54xx_l4_per_hwmod,
2528         .slave          = &omap54xx_mmc1_hwmod,
2529         .clk            = "l3_iclk_div",
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532
2533 /* l4_per -> mmc2 */
2534 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2535         .master         = &omap54xx_l4_per_hwmod,
2536         .slave          = &omap54xx_mmc2_hwmod,
2537         .clk            = "l3_iclk_div",
2538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2539 };
2540
2541 /* l4_per -> mmc3 */
2542 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2543         .master         = &omap54xx_l4_per_hwmod,
2544         .slave          = &omap54xx_mmc3_hwmod,
2545         .clk            = "l4_root_clk_div",
2546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2547 };
2548
2549 /* l4_per -> mmc4 */
2550 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2551         .master         = &omap54xx_l4_per_hwmod,
2552         .slave          = &omap54xx_mmc4_hwmod,
2553         .clk            = "l4_root_clk_div",
2554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2555 };
2556
2557 /* l4_per -> mmc5 */
2558 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2559         .master         = &omap54xx_l4_per_hwmod,
2560         .slave          = &omap54xx_mmc5_hwmod,
2561         .clk            = "l4_root_clk_div",
2562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2563 };
2564
2565 /* l4_cfg -> mpu */
2566 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2567         .master         = &omap54xx_l4_cfg_hwmod,
2568         .slave          = &omap54xx_mpu_hwmod,
2569         .clk            = "l4_root_clk_div",
2570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2571 };
2572
2573 /* l4_cfg -> spinlock */
2574 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2575         .master         = &omap54xx_l4_cfg_hwmod,
2576         .slave          = &omap54xx_spinlock_hwmod,
2577         .clk            = "l4_root_clk_div",
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 /* l4_cfg -> ocp2scp1 */
2582 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2583         .master         = &omap54xx_l4_cfg_hwmod,
2584         .slave          = &omap54xx_ocp2scp1_hwmod,
2585         .clk            = "l4_root_clk_div",
2586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588
2589 /* l4_wkup -> timer1 */
2590 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2591         .master         = &omap54xx_l4_wkup_hwmod,
2592         .slave          = &omap54xx_timer1_hwmod,
2593         .clk            = "wkupaon_iclk_mux",
2594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 /* l4_per -> timer2 */
2598 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2599         .master         = &omap54xx_l4_per_hwmod,
2600         .slave          = &omap54xx_timer2_hwmod,
2601         .clk            = "l4_root_clk_div",
2602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2603 };
2604
2605 /* l4_per -> timer3 */
2606 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2607         .master         = &omap54xx_l4_per_hwmod,
2608         .slave          = &omap54xx_timer3_hwmod,
2609         .clk            = "l4_root_clk_div",
2610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2611 };
2612
2613 /* l4_per -> timer4 */
2614 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2615         .master         = &omap54xx_l4_per_hwmod,
2616         .slave          = &omap54xx_timer4_hwmod,
2617         .clk            = "l4_root_clk_div",
2618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2619 };
2620
2621 /* l4_abe -> timer5 */
2622 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2623         .master         = &omap54xx_l4_abe_hwmod,
2624         .slave          = &omap54xx_timer5_hwmod,
2625         .clk            = "abe_iclk",
2626         .user           = OCP_USER_MPU,
2627 };
2628
2629 /* l4_abe -> timer6 */
2630 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2631         .master         = &omap54xx_l4_abe_hwmod,
2632         .slave          = &omap54xx_timer6_hwmod,
2633         .clk            = "abe_iclk",
2634         .user           = OCP_USER_MPU,
2635 };
2636
2637 /* l4_abe -> timer7 */
2638 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2639         .master         = &omap54xx_l4_abe_hwmod,
2640         .slave          = &omap54xx_timer7_hwmod,
2641         .clk            = "abe_iclk",
2642         .user           = OCP_USER_MPU,
2643 };
2644
2645 /* l4_abe -> timer8 */
2646 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2647         .master         = &omap54xx_l4_abe_hwmod,
2648         .slave          = &omap54xx_timer8_hwmod,
2649         .clk            = "abe_iclk",
2650         .user           = OCP_USER_MPU,
2651 };
2652
2653 /* l4_per -> timer9 */
2654 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2655         .master         = &omap54xx_l4_per_hwmod,
2656         .slave          = &omap54xx_timer9_hwmod,
2657         .clk            = "l4_root_clk_div",
2658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2659 };
2660
2661 /* l4_per -> timer10 */
2662 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2663         .master         = &omap54xx_l4_per_hwmod,
2664         .slave          = &omap54xx_timer10_hwmod,
2665         .clk            = "l4_root_clk_div",
2666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 /* l4_per -> timer11 */
2670 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2671         .master         = &omap54xx_l4_per_hwmod,
2672         .slave          = &omap54xx_timer11_hwmod,
2673         .clk            = "l4_root_clk_div",
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676
2677 /* l4_per -> uart1 */
2678 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2679         .master         = &omap54xx_l4_per_hwmod,
2680         .slave          = &omap54xx_uart1_hwmod,
2681         .clk            = "l4_root_clk_div",
2682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2683 };
2684
2685 /* l4_per -> uart2 */
2686 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2687         .master         = &omap54xx_l4_per_hwmod,
2688         .slave          = &omap54xx_uart2_hwmod,
2689         .clk            = "l4_root_clk_div",
2690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692
2693 /* l4_per -> uart3 */
2694 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2695         .master         = &omap54xx_l4_per_hwmod,
2696         .slave          = &omap54xx_uart3_hwmod,
2697         .clk            = "l4_root_clk_div",
2698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2699 };
2700
2701 /* l4_per -> uart4 */
2702 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2703         .master         = &omap54xx_l4_per_hwmod,
2704         .slave          = &omap54xx_uart4_hwmod,
2705         .clk            = "l4_root_clk_div",
2706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2707 };
2708
2709 /* l4_per -> uart5 */
2710 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2711         .master         = &omap54xx_l4_per_hwmod,
2712         .slave          = &omap54xx_uart5_hwmod,
2713         .clk            = "l4_root_clk_div",
2714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716
2717 /* l4_per -> uart6 */
2718 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2719         .master         = &omap54xx_l4_per_hwmod,
2720         .slave          = &omap54xx_uart6_hwmod,
2721         .clk            = "l4_root_clk_div",
2722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2723 };
2724
2725 /* l4_cfg -> usb_host_hs */
2726 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2727         .master         = &omap54xx_l4_cfg_hwmod,
2728         .slave          = &omap54xx_usb_host_hs_hwmod,
2729         .clk            = "l3_iclk_div",
2730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2732
2733 /* l4_cfg -> usb_tll_hs */
2734 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2735         .master         = &omap54xx_l4_cfg_hwmod,
2736         .slave          = &omap54xx_usb_tll_hs_hwmod,
2737         .clk            = "l4_root_clk_div",
2738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2739 };
2740
2741 /* l4_cfg -> usb_otg_ss */
2742 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2743         .master         = &omap54xx_l4_cfg_hwmod,
2744         .slave          = &omap54xx_usb_otg_ss_hwmod,
2745         .clk            = "dpll_core_h13x2_ck",
2746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748
2749 /* l4_wkup -> wd_timer2 */
2750 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2751         .master         = &omap54xx_l4_wkup_hwmod,
2752         .slave          = &omap54xx_wd_timer2_hwmod,
2753         .clk            = "wkupaon_iclk_mux",
2754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2755 };
2756
2757 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2758         &omap54xx_l3_main_1__dmm,
2759         &omap54xx_l3_main_3__l3_instr,
2760         &omap54xx_l3_main_2__l3_main_1,
2761         &omap54xx_l4_cfg__l3_main_1,
2762         &omap54xx_mpu__l3_main_1,
2763         &omap54xx_l3_main_1__l3_main_2,
2764         &omap54xx_l4_cfg__l3_main_2,
2765         &omap54xx_l3_main_1__l3_main_3,
2766         &omap54xx_l3_main_2__l3_main_3,
2767         &omap54xx_l4_cfg__l3_main_3,
2768         &omap54xx_l3_main_1__l4_abe,
2769         &omap54xx_mpu__l4_abe,
2770         &omap54xx_l3_main_1__l4_cfg,
2771         &omap54xx_l3_main_2__l4_per,
2772         &omap54xx_l3_main_1__l4_wkup,
2773         &omap54xx_mpu__mpu_private,
2774         &omap54xx_l4_wkup__counter_32k,
2775         &omap54xx_l4_cfg__dma_system,
2776         &omap54xx_l4_abe__dmic,
2777         &omap54xx_l4_cfg__mmu_dsp,
2778         &omap54xx_l3_main_2__dss,
2779         &omap54xx_l3_main_2__dss_dispc,
2780         &omap54xx_l3_main_2__dss_dsi1_a,
2781         &omap54xx_l3_main_2__dss_dsi1_c,
2782         &omap54xx_l3_main_2__dss_hdmi,
2783         &omap54xx_l3_main_2__dss_rfbi,
2784         &omap54xx_mpu__emif1,
2785         &omap54xx_mpu__emif2,
2786         &omap54xx_l4_wkup__gpio1,
2787         &omap54xx_l4_per__gpio2,
2788         &omap54xx_l4_per__gpio3,
2789         &omap54xx_l4_per__gpio4,
2790         &omap54xx_l4_per__gpio5,
2791         &omap54xx_l4_per__gpio6,
2792         &omap54xx_l4_per__gpio7,
2793         &omap54xx_l4_per__gpio8,
2794         &omap54xx_l4_per__i2c1,
2795         &omap54xx_l4_per__i2c2,
2796         &omap54xx_l4_per__i2c3,
2797         &omap54xx_l4_per__i2c4,
2798         &omap54xx_l4_per__i2c5,
2799         &omap54xx_l3_main_2__mmu_ipu,
2800         &omap54xx_l4_wkup__kbd,
2801         &omap54xx_l4_cfg__mailbox,
2802         &omap54xx_l4_abe__mcbsp1,
2803         &omap54xx_l4_abe__mcbsp2,
2804         &omap54xx_l4_abe__mcbsp3,
2805         &omap54xx_l4_abe__mcpdm,
2806         &omap54xx_l4_per__mcspi1,
2807         &omap54xx_l4_per__mcspi2,
2808         &omap54xx_l4_per__mcspi3,
2809         &omap54xx_l4_per__mcspi4,
2810         &omap54xx_l4_per__mmc1,
2811         &omap54xx_l4_per__mmc2,
2812         &omap54xx_l4_per__mmc3,
2813         &omap54xx_l4_per__mmc4,
2814         &omap54xx_l4_per__mmc5,
2815         &omap54xx_l4_cfg__mpu,
2816         &omap54xx_l4_cfg__spinlock,
2817         &omap54xx_l4_cfg__ocp2scp1,
2818         &omap54xx_l4_wkup__timer1,
2819         &omap54xx_l4_per__timer2,
2820         &omap54xx_l4_per__timer3,
2821         &omap54xx_l4_per__timer4,
2822         &omap54xx_l4_abe__timer5,
2823         &omap54xx_l4_abe__timer6,
2824         &omap54xx_l4_abe__timer7,
2825         &omap54xx_l4_abe__timer8,
2826         &omap54xx_l4_per__timer9,
2827         &omap54xx_l4_per__timer10,
2828         &omap54xx_l4_per__timer11,
2829         &omap54xx_l4_per__uart1,
2830         &omap54xx_l4_per__uart2,
2831         &omap54xx_l4_per__uart3,
2832         &omap54xx_l4_per__uart4,
2833         &omap54xx_l4_per__uart5,
2834         &omap54xx_l4_per__uart6,
2835         &omap54xx_l4_cfg__usb_host_hs,
2836         &omap54xx_l4_cfg__usb_tll_hs,
2837         &omap54xx_l4_cfg__usb_otg_ss,
2838         &omap54xx_l4_wkup__wd_timer2,
2839         &omap54xx_l4_cfg__ocp2scp3,
2840         &omap54xx_l4_cfg__sata,
2841         NULL,
2842 };
2843
2844 int __init omap54xx_hwmod_init(void)
2845 {
2846         omap_hwmod_init();
2847         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2848 }