arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22
  23 #include <linux/omap-dma.h>
  24 #include "l3_3xxx.h"
  25 #include "l4_3xxx.h"
  26 #include <linux/platform_data/asoc-ti-mcbsp.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "soc.h"
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "serial.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /* L3 */
  56 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  57         { .irq = 9 + OMAP_INTC_START, },
  58         { .irq = 10 + OMAP_INTC_START, },
  59         { .irq = -1 },
  60 };
  61
  62 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  63         .name           = "l3_main",
  64         .class          = &l3_hwmod_class,
  65         .mpu_irqs       = omap3xxx_l3_main_irqs,
  66         .flags          = HWMOD_NO_IDLEST,
  67 };
  68
  69 /* L4 CORE */
  70 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  71         .name           = "l4_core",
  72         .class          = &l4_hwmod_class,
  73         .flags          = HWMOD_NO_IDLEST,
  74 };
  75
  76 /* L4 PER */
  77 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  78         .name           = "l4_per",
  79         .class          = &l4_hwmod_class,
  80         .flags          = HWMOD_NO_IDLEST,
  81 };
  82
  83 /* L4 WKUP */
  84 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  85         .name           = "l4_wkup",
  86         .class          = &l4_hwmod_class,
  87         .flags          = HWMOD_NO_IDLEST,
  88 };
  89
  90 /* L4 SEC */
  91 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  92         .name           = "l4_sec",
  93         .class          = &l4_hwmod_class,
  94         .flags          = HWMOD_NO_IDLEST,
  95 };
  96
  97 /* MPU */
  98 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
  99         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 100         { .irq = -1 }
 101 };
 102
 103 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 104         .name           = "mpu",
 105         .mpu_irqs       = omap3xxx_mpu_irqs,
 106         .class          = &mpu_hwmod_class,
 107         .main_clk       = "arm_fck",
 108 };
 109
 110 /* IVA2 (IVA2) */
 111 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 112         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 113         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 114         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 115 };
 116
 117 static struct omap_hwmod omap3xxx_iva_hwmod = {
 118         .name           = "iva",
 119         .class          = &iva_hwmod_class,
 120         .clkdm_name     = "iva2_clkdm",
 121         .rst_lines      = omap3xxx_iva_resets,
 122         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 123         .main_clk       = "iva2_ck",
 124         .prcm = {
 125                 .omap2 = {
 126                         .module_offs = OMAP3430_IVA2_MOD,
 127                         .prcm_reg_id = 1,
 128                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 129                         .idlest_reg_id = 1,
 130                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 131                 }
 132         },
 133 };
 134
 135 /*
 136  * 'debugss' class
 137  * debug and emulation sub system
 138  */
 139
 140 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 141         .name   = "debugss",
 142 };
 143
 144 /* debugss */
 145 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 146         .name           = "debugss",
 147         .class          = &omap3xxx_debugss_hwmod_class,
 148         .clkdm_name     = "emu_clkdm",
 149         .main_clk       = "emu_src_ck",
 150         .flags          = HWMOD_NO_IDLEST,
 151 };
 152
 153 /* timer class */
 154 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 155         .rev_offs       = 0x0000,
 156         .sysc_offs      = 0x0010,
 157         .syss_offs      = 0x0014,
 158         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 159                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 160                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 161                            SYSS_HAS_RESET_STATUS),
 162         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 163         .clockact       = CLOCKACT_TEST_ICLK,
 164         .sysc_fields    = &omap_hwmod_sysc_type1,
 165 };
 166
 167 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 168         .name = "timer",
 169         .sysc = &omap3xxx_timer_sysc,
 170 };
 171
 172 /* secure timers dev attribute */
 173 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 174         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 175 };
 176
 177 /* always-on timers dev attribute */
 178 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 179         .timer_capability       = OMAP_TIMER_ALWON,
 180 };
 181
 182 /* pwm timers dev attribute */
 183 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 184         .timer_capability       = OMAP_TIMER_HAS_PWM,
 185 };
 186
 187 /* timers with DSP interrupt dev attribute */
 188 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 189         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 190 };
 191
 192 /* pwm timers with DSP interrupt dev attribute */
 193 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 194         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 195 };
 196
 197 /* timer1 */
 198 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 199         .name           = "timer1",
 200         .mpu_irqs       = omap2_timer1_mpu_irqs,
 201         .main_clk       = "gpt1_fck",
 202         .prcm           = {
 203                 .omap2 = {
 204                         .prcm_reg_id = 1,
 205                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 206                         .module_offs = WKUP_MOD,
 207                         .idlest_reg_id = 1,
 208                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 209                 },
 210         },
 211         .dev_attr       = &capability_alwon_dev_attr,
 212         .class          = &omap3xxx_timer_hwmod_class,
 213         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 214 };
 215
 216 /* timer2 */
 217 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 218         .name           = "timer2",
 219         .mpu_irqs       = omap2_timer2_mpu_irqs,
 220         .main_clk       = "gpt2_fck",
 221         .prcm           = {
 222                 .omap2 = {
 223                         .prcm_reg_id = 1,
 224                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 225                         .module_offs = OMAP3430_PER_MOD,
 226                         .idlest_reg_id = 1,
 227                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 228                 },
 229         },
 230         .class          = &omap3xxx_timer_hwmod_class,
 231         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 232 };
 233
 234 /* timer3 */
 235 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 236         .name           = "timer3",
 237         .mpu_irqs       = omap2_timer3_mpu_irqs,
 238         .main_clk       = "gpt3_fck",
 239         .prcm           = {
 240                 .omap2 = {
 241                         .prcm_reg_id = 1,
 242                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 243                         .module_offs = OMAP3430_PER_MOD,
 244                         .idlest_reg_id = 1,
 245                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 246                 },
 247         },
 248         .class          = &omap3xxx_timer_hwmod_class,
 249         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 250 };
 251
 252 /* timer4 */
 253 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 254         .name           = "timer4",
 255         .mpu_irqs       = omap2_timer4_mpu_irqs,
 256         .main_clk       = "gpt4_fck",
 257         .prcm           = {
 258                 .omap2 = {
 259                         .prcm_reg_id = 1,
 260                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 261                         .module_offs = OMAP3430_PER_MOD,
 262                         .idlest_reg_id = 1,
 263                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 264                 },
 265         },
 266         .class          = &omap3xxx_timer_hwmod_class,
 267         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 268 };
 269
 270 /* timer5 */
 271 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 272         .name           = "timer5",
 273         .mpu_irqs       = omap2_timer5_mpu_irqs,
 274         .main_clk       = "gpt5_fck",
 275         .prcm           = {
 276                 .omap2 = {
 277                         .prcm_reg_id = 1,
 278                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 279                         .module_offs = OMAP3430_PER_MOD,
 280                         .idlest_reg_id = 1,
 281                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 282                 },
 283         },
 284         .dev_attr       = &capability_dsp_dev_attr,
 285         .class          = &omap3xxx_timer_hwmod_class,
 286         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 287 };
 288
 289 /* timer6 */
 290 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 291         .name           = "timer6",
 292         .mpu_irqs       = omap2_timer6_mpu_irqs,
 293         .main_clk       = "gpt6_fck",
 294         .prcm           = {
 295                 .omap2 = {
 296                         .prcm_reg_id = 1,
 297                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 298                         .module_offs = OMAP3430_PER_MOD,
 299                         .idlest_reg_id = 1,
 300                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 301                 },
 302         },
 303         .dev_attr       = &capability_dsp_dev_attr,
 304         .class          = &omap3xxx_timer_hwmod_class,
 305         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 306 };
 307
 308 /* timer7 */
 309 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 310         .name           = "timer7",
 311         .mpu_irqs       = omap2_timer7_mpu_irqs,
 312         .main_clk       = "gpt7_fck",
 313         .prcm           = {
 314                 .omap2 = {
 315                         .prcm_reg_id = 1,
 316                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 317                         .module_offs = OMAP3430_PER_MOD,
 318                         .idlest_reg_id = 1,
 319                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 320                 },
 321         },
 322         .dev_attr       = &capability_dsp_dev_attr,
 323         .class          = &omap3xxx_timer_hwmod_class,
 324         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 325 };
 326
 327 /* timer8 */
 328 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 329         .name           = "timer8",
 330         .mpu_irqs       = omap2_timer8_mpu_irqs,
 331         .main_clk       = "gpt8_fck",
 332         .prcm           = {
 333                 .omap2 = {
 334                         .prcm_reg_id = 1,
 335                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 336                         .module_offs = OMAP3430_PER_MOD,
 337                         .idlest_reg_id = 1,
 338                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 339                 },
 340         },
 341         .dev_attr       = &capability_dsp_pwm_dev_attr,
 342         .class          = &omap3xxx_timer_hwmod_class,
 343         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 344 };
 345
 346 /* timer9 */
 347 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 348         .name           = "timer9",
 349         .mpu_irqs       = omap2_timer9_mpu_irqs,
 350         .main_clk       = "gpt9_fck",
 351         .prcm           = {
 352                 .omap2 = {
 353                         .prcm_reg_id = 1,
 354                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 355                         .module_offs = OMAP3430_PER_MOD,
 356                         .idlest_reg_id = 1,
 357                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 358                 },
 359         },
 360         .dev_attr       = &capability_pwm_dev_attr,
 361         .class          = &omap3xxx_timer_hwmod_class,
 362         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 363 };
 364
 365 /* timer10 */
 366 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 367         .name           = "timer10",
 368         .mpu_irqs       = omap2_timer10_mpu_irqs,
 369         .main_clk       = "gpt10_fck",
 370         .prcm           = {
 371                 .omap2 = {
 372                         .prcm_reg_id = 1,
 373                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 374                         .module_offs = CORE_MOD,
 375                         .idlest_reg_id = 1,
 376                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 377                 },
 378         },
 379         .dev_attr       = &capability_pwm_dev_attr,
 380         .class          = &omap3xxx_timer_hwmod_class,
 381         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 382 };
 383
 384 /* timer11 */
 385 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 386         .name           = "timer11",
 387         .mpu_irqs       = omap2_timer11_mpu_irqs,
 388         .main_clk       = "gpt11_fck",
 389         .prcm           = {
 390                 .omap2 = {
 391                         .prcm_reg_id = 1,
 392                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 393                         .module_offs = CORE_MOD,
 394                         .idlest_reg_id = 1,
 395                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 396                 },
 397         },
 398         .dev_attr       = &capability_pwm_dev_attr,
 399         .class          = &omap3xxx_timer_hwmod_class,
 400         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 401 };
 402
 403 /* timer12 */
 404 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 405         { .irq = 95 + OMAP_INTC_START, },
 406         { .irq = -1 },
 407 };
 408
 409 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 410         .name           = "timer12",
 411         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 412         .main_clk       = "gpt12_fck",
 413         .prcm           = {
 414                 .omap2 = {
 415                         .prcm_reg_id = 1,
 416                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 417                         .module_offs = WKUP_MOD,
 418                         .idlest_reg_id = 1,
 419                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 420                 },
 421         },
 422         .dev_attr       = &capability_secure_dev_attr,
 423         .class          = &omap3xxx_timer_hwmod_class,
 424         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 425 };
 426
 427 /*
 428  * 'wd_timer' class
 429  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 430  * overflow condition
 431  */
 432
 433 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 434         .rev_offs       = 0x0000,
 435         .sysc_offs      = 0x0010,
 436         .syss_offs      = 0x0014,
 437         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 438                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 439                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 440                            SYSS_HAS_RESET_STATUS),
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 442         .sysc_fields    = &omap_hwmod_sysc_type1,
 443 };
 444
 445 /* I2C common */
 446 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 447         .rev_offs       = 0x00,
 448         .sysc_offs      = 0x20,
 449         .syss_offs      = 0x10,
 450         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 451                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 452                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 453         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 454         .clockact       = CLOCKACT_TEST_ICLK,
 455         .sysc_fields    = &omap_hwmod_sysc_type1,
 456 };
 457
 458 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 459         .name           = "wd_timer",
 460         .sysc           = &omap3xxx_wd_timer_sysc,
 461         .pre_shutdown   = &omap2_wd_timer_disable,
 462         .reset          = &omap2_wd_timer_reset,
 463 };
 464
 465 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 466         .name           = "wd_timer2",
 467         .class          = &omap3xxx_wd_timer_hwmod_class,
 468         .main_clk       = "wdt2_fck",
 469         .prcm           = {
 470                 .omap2 = {
 471                         .prcm_reg_id = 1,
 472                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 473                         .module_offs = WKUP_MOD,
 474                         .idlest_reg_id = 1,
 475                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 476                 },
 477         },
 478         /*
 479          * XXX: Use software supervised mode, HW supervised smartidle seems to
 480          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 481          */
 482         .flags          = HWMOD_SWSUP_SIDLE,
 483 };
 484
 485 /* UART1 */
 486 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 487         .name           = "uart1",
 488         .mpu_irqs       = omap2_uart1_mpu_irqs,
 489         .sdma_reqs      = omap2_uart1_sdma_reqs,
 490         .main_clk       = "uart1_fck",
 491         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 492         .prcm           = {
 493                 .omap2 = {
 494                         .module_offs = CORE_MOD,
 495                         .prcm_reg_id = 1,
 496                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 497                         .idlest_reg_id = 1,
 498                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 499                 },
 500         },
 501         .class          = &omap2_uart_class,
 502 };
 503
 504 /* UART2 */
 505 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 506         .name           = "uart2",
 507         .mpu_irqs       = omap2_uart2_mpu_irqs,
 508         .sdma_reqs      = omap2_uart2_sdma_reqs,
 509         .main_clk       = "uart2_fck",
 510         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 511         .prcm           = {
 512                 .omap2 = {
 513                         .module_offs = CORE_MOD,
 514                         .prcm_reg_id = 1,
 515                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 516                         .idlest_reg_id = 1,
 517                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 518                 },
 519         },
 520         .class          = &omap2_uart_class,
 521 };
 522
 523 /* UART3 */
 524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 525         .name           = "uart3",
 526         .mpu_irqs       = omap2_uart3_mpu_irqs,
 527         .sdma_reqs      = omap2_uart3_sdma_reqs,
 528         .main_clk       = "uart3_fck",
 529         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 530                                 HWMOD_SWSUP_SIDLE,
 531         .prcm           = {
 532                 .omap2 = {
 533                         .module_offs = OMAP3430_PER_MOD,
 534                         .prcm_reg_id = 1,
 535                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 536                         .idlest_reg_id = 1,
 537                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 538                 },
 539         },
 540         .class          = &omap2_uart_class,
 541 };
 542
 543 /* UART4 */
 544 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 545         { .irq = 80 + OMAP_INTC_START, },
 546         { .irq = -1 },
 547 };
 548
 549 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 550         { .name = "rx", .dma_req = 82, },
 551         { .name = "tx", .dma_req = 81, },
 552         { .dma_req = -1 }
 553 };
 554
 555 static struct omap_hwmod omap36xx_uart4_hwmod = {
 556         .name           = "uart4",
 557         .mpu_irqs       = uart4_mpu_irqs,
 558         .sdma_reqs      = uart4_sdma_reqs,
 559         .main_clk       = "uart4_fck",
 560         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 561         .prcm           = {
 562                 .omap2 = {
 563                         .module_offs = OMAP3430_PER_MOD,
 564                         .prcm_reg_id = 1,
 565                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 566                         .idlest_reg_id = 1,
 567                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 568                 },
 569         },
 570         .class          = &omap2_uart_class,
 571 };
 572
 573 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 574         { .irq = 84 + OMAP_INTC_START, },
 575         { .irq = -1 },
 576 };
 577
 578 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 579         { .name = "rx", .dma_req = 55, },
 580         { .name = "tx", .dma_req = 54, },
 581         { .dma_req = -1 }
 582 };
 583
 584 /*
 585  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 586  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 587  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 588  * should not be needed.  The functional clock structure of the AM35xx
 589  * UART4 is extremely unclear and opaque; it is unclear what the role
 590  * of uart1/2_fck is for the UART4.  Any clarification from either
 591  * empirical testing or the AM3505/3517 hardware designers would be
 592  * most welcome.
 593  */
 594 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 595         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 596 };
 597
 598 static struct omap_hwmod am35xx_uart4_hwmod = {
 599         .name           = "uart4",
 600         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 601         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 602         .main_clk       = "uart4_fck",
 603         .prcm           = {
 604                 .omap2 = {
 605                         .module_offs = CORE_MOD,
 606                         .prcm_reg_id = 1,
 607                         .module_bit = AM35XX_EN_UART4_SHIFT,
 608                         .idlest_reg_id = 1,
 609                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 610                 },
 611         },
 612         .opt_clks       = am35xx_uart4_opt_clks,
 613         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 614         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 615         .class          = &omap2_uart_class,
 616 };
 617
 618 static struct omap_hwmod_class i2c_class = {
 619         .name   = "i2c",
 620         .sysc   = &i2c_sysc,
 621         .rev    = OMAP_I2C_IP_VERSION_1,
 622         .reset  = &omap_i2c_reset,
 623 };
 624
 625 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 626         { .name = "dispc", .dma_req = 5 },
 627         { .name = "dsi1", .dma_req = 74 },
 628         { .dma_req = -1 }
 629 };
 630
 631 /* dss */
 632 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 633         /*
 634          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 635          * driver does not use these clocks.
 636          */
 637         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 638         { .role = "tv_clk", .clk = "dss_tv_fck" },
 639         /* required only on OMAP3430 */
 640         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 641 };
 642
 643 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 644         .name           = "dss_core",
 645         .class          = &omap2_dss_hwmod_class,
 646         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 647         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 648         .prcm           = {
 649                 .omap2 = {
 650                         .prcm_reg_id = 1,
 651                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 652                         .module_offs = OMAP3430_DSS_MOD,
 653                         .idlest_reg_id = 1,
 654                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 655                 },
 656         },
 657         .opt_clks       = dss_opt_clks,
 658         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 659         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 660 };
 661
 662 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 663         .name           = "dss_core",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .class          = &omap2_dss_hwmod_class,
 666         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 667         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 668         .prcm           = {
 669                 .omap2 = {
 670                         .prcm_reg_id = 1,
 671                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 672                         .module_offs = OMAP3430_DSS_MOD,
 673                         .idlest_reg_id = 1,
 674                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 675                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 676                 },
 677         },
 678         .opt_clks       = dss_opt_clks,
 679         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 680 };
 681
 682 /*
 683  * 'dispc' class
 684  * display controller
 685  */
 686
 687 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 688         .rev_offs       = 0x0000,
 689         .sysc_offs      = 0x0010,
 690         .syss_offs      = 0x0014,
 691         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 692                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 693                            SYSC_HAS_ENAWAKEUP),
 694         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 695                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 696         .sysc_fields    = &omap_hwmod_sysc_type1,
 697 };
 698
 699 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 700         .name   = "dispc",
 701         .sysc   = &omap3_dispc_sysc,
 702 };
 703
 704 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 705         .name           = "dss_dispc",
 706         .class          = &omap3_dispc_hwmod_class,
 707         .mpu_irqs       = omap2_dispc_irqs,
 708         .main_clk       = "dss1_alwon_fck",
 709         .prcm           = {
 710                 .omap2 = {
 711                         .prcm_reg_id = 1,
 712                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 713                         .module_offs = OMAP3430_DSS_MOD,
 714                 },
 715         },
 716         .flags          = HWMOD_NO_IDLEST,
 717         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 718 };
 719
 720 /*
 721  * 'dsi' class
 722  * display serial interface controller
 723  */
 724
 725 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 726         .name = "dsi",
 727 };
 728
 729 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 730         { .irq = 25 + OMAP_INTC_START, },
 731         { .irq = -1 },
 732 };
 733
 734 /* dss_dsi1 */
 735 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 736         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 737 };
 738
 739 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 740         .name           = "dss_dsi1",
 741         .class          = &omap3xxx_dsi_hwmod_class,
 742         .mpu_irqs       = omap3xxx_dsi1_irqs,
 743         .main_clk       = "dss1_alwon_fck",
 744         .prcm           = {
 745                 .omap2 = {
 746                         .prcm_reg_id = 1,
 747                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 748                         .module_offs = OMAP3430_DSS_MOD,
 749                 },
 750         },
 751         .opt_clks       = dss_dsi1_opt_clks,
 752         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 753         .flags          = HWMOD_NO_IDLEST,
 754 };
 755
 756 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 757         { .role = "ick", .clk = "dss_ick" },
 758 };
 759
 760 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 761         .name           = "dss_rfbi",
 762         .class          = &omap2_rfbi_hwmod_class,
 763         .main_clk       = "dss1_alwon_fck",
 764         .prcm           = {
 765                 .omap2 = {
 766                         .prcm_reg_id = 1,
 767                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 768                         .module_offs = OMAP3430_DSS_MOD,
 769                 },
 770         },
 771         .opt_clks       = dss_rfbi_opt_clks,
 772         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 773         .flags          = HWMOD_NO_IDLEST,
 774 };
 775
 776 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 777         /* required only on OMAP3430 */
 778         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 779 };
 780
 781 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 782         .name           = "dss_venc",
 783         .class          = &omap2_venc_hwmod_class,
 784         .main_clk       = "dss_tv_fck",
 785         .prcm           = {
 786                 .omap2 = {
 787                         .prcm_reg_id = 1,
 788                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 789                         .module_offs = OMAP3430_DSS_MOD,
 790                 },
 791         },
 792         .opt_clks       = dss_venc_opt_clks,
 793         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 794         .flags          = HWMOD_NO_IDLEST,
 795 };
 796
 797 /* I2C1 */
 798 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 799         .fifo_depth     = 8, /* bytes */
 800         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 801 };
 802
 803 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 804         .name           = "i2c1",
 805         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 806         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 807         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 808         .main_clk       = "i2c1_fck",
 809         .prcm           = {
 810                 .omap2 = {
 811                         .module_offs = CORE_MOD,
 812                         .prcm_reg_id = 1,
 813                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 814                         .idlest_reg_id = 1,
 815                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 816                 },
 817         },
 818         .class          = &i2c_class,
 819         .dev_attr       = &i2c1_dev_attr,
 820 };
 821
 822 /* I2C2 */
 823 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 824         .fifo_depth     = 8, /* bytes */
 825         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 826 };
 827
 828 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 829         .name           = "i2c2",
 830         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 831         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 832         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 833         .main_clk       = "i2c2_fck",
 834         .prcm           = {
 835                 .omap2 = {
 836                         .module_offs = CORE_MOD,
 837                         .prcm_reg_id = 1,
 838                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 839                         .idlest_reg_id = 1,
 840                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 841                 },
 842         },
 843         .class          = &i2c_class,
 844         .dev_attr       = &i2c2_dev_attr,
 845 };
 846
 847 /* I2C3 */
 848 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 849         .fifo_depth     = 64, /* bytes */
 850         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 851 };
 852
 853 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 854         { .irq = 61 + OMAP_INTC_START, },
 855         { .irq = -1 },
 856 };
 857
 858 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 859         { .name = "tx", .dma_req = 25 },
 860         { .name = "rx", .dma_req = 26 },
 861         { .dma_req = -1 }
 862 };
 863
 864 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 865         .name           = "i2c3",
 866         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 867         .mpu_irqs       = i2c3_mpu_irqs,
 868         .sdma_reqs      = i2c3_sdma_reqs,
 869         .main_clk       = "i2c3_fck",
 870         .prcm           = {
 871                 .omap2 = {
 872                         .module_offs = CORE_MOD,
 873                         .prcm_reg_id = 1,
 874                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 875                         .idlest_reg_id = 1,
 876                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 877                 },
 878         },
 879         .class          = &i2c_class,
 880         .dev_attr       = &i2c3_dev_attr,
 881 };
 882
 883 /*
 884  * 'gpio' class
 885  * general purpose io module
 886  */
 887
 888 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 889         .rev_offs       = 0x0000,
 890         .sysc_offs      = 0x0010,
 891         .syss_offs      = 0x0014,
 892         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 893                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 894                            SYSS_HAS_RESET_STATUS),
 895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 896         .sysc_fields    = &omap_hwmod_sysc_type1,
 897 };
 898
 899 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 900         .name = "gpio",
 901         .sysc = &omap3xxx_gpio_sysc,
 902         .rev = 1,
 903 };
 904
 905 /* gpio_dev_attr */
 906 static struct omap_gpio_dev_attr gpio_dev_attr = {
 907         .bank_width = 32,
 908         .dbck_flag = true,
 909 };
 910
 911 /* gpio1 */
 912 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 913         { .role = "dbclk", .clk = "gpio1_dbck", },
 914 };
 915
 916 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 917         .name           = "gpio1",
 918         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 919         .mpu_irqs       = omap2_gpio1_irqs,
 920         .main_clk       = "gpio1_ick",
 921         .opt_clks       = gpio1_opt_clks,
 922         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 923         .prcm           = {
 924                 .omap2 = {
 925                         .prcm_reg_id = 1,
 926                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 927                         .module_offs = WKUP_MOD,
 928                         .idlest_reg_id = 1,
 929                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 930                 },
 931         },
 932         .class          = &omap3xxx_gpio_hwmod_class,
 933         .dev_attr       = &gpio_dev_attr,
 934 };
 935
 936 /* gpio2 */
 937 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 938         { .role = "dbclk", .clk = "gpio2_dbck", },
 939 };
 940
 941 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 942         .name           = "gpio2",
 943         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 944         .mpu_irqs       = omap2_gpio2_irqs,
 945         .main_clk       = "gpio2_ick",
 946         .opt_clks       = gpio2_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 948         .prcm           = {
 949                 .omap2 = {
 950                         .prcm_reg_id = 1,
 951                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 952                         .module_offs = OMAP3430_PER_MOD,
 953                         .idlest_reg_id = 1,
 954                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 955                 },
 956         },
 957         .class          = &omap3xxx_gpio_hwmod_class,
 958         .dev_attr       = &gpio_dev_attr,
 959 };
 960
 961 /* gpio3 */
 962 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 963         { .role = "dbclk", .clk = "gpio3_dbck", },
 964 };
 965
 966 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 967         .name           = "gpio3",
 968         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 969         .mpu_irqs       = omap2_gpio3_irqs,
 970         .main_clk       = "gpio3_ick",
 971         .opt_clks       = gpio3_opt_clks,
 972         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 973         .prcm           = {
 974                 .omap2 = {
 975                         .prcm_reg_id = 1,
 976                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 977                         .module_offs = OMAP3430_PER_MOD,
 978                         .idlest_reg_id = 1,
 979                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 980                 },
 981         },
 982         .class          = &omap3xxx_gpio_hwmod_class,
 983         .dev_attr       = &gpio_dev_attr,
 984 };
 985
 986 /* gpio4 */
 987 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 988         { .role = "dbclk", .clk = "gpio4_dbck", },
 989 };
 990
 991 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 992         .name           = "gpio4",
 993         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 994         .mpu_irqs       = omap2_gpio4_irqs,
 995         .main_clk       = "gpio4_ick",
 996         .opt_clks       = gpio4_opt_clks,
 997         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 998         .prcm           = {
 999                 .omap2 = {
1000                         .prcm_reg_id = 1,
1001                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1002                         .module_offs = OMAP3430_PER_MOD,
1003                         .idlest_reg_id = 1,
1004                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1005                 },
1006         },
1007         .class          = &omap3xxx_gpio_hwmod_class,
1008         .dev_attr       = &gpio_dev_attr,
1009 };
1010
1011 /* gpio5 */
1012 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1013         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1014         { .irq = -1 },
1015 };
1016
1017 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1018         { .role = "dbclk", .clk = "gpio5_dbck", },
1019 };
1020
1021 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1022         .name           = "gpio5",
1023         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1024         .mpu_irqs       = omap3xxx_gpio5_irqs,
1025         .main_clk       = "gpio5_ick",
1026         .opt_clks       = gpio5_opt_clks,
1027         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1028         .prcm           = {
1029                 .omap2 = {
1030                         .prcm_reg_id = 1,
1031                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1032                         .module_offs = OMAP3430_PER_MOD,
1033                         .idlest_reg_id = 1,
1034                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1035                 },
1036         },
1037         .class          = &omap3xxx_gpio_hwmod_class,
1038         .dev_attr       = &gpio_dev_attr,
1039 };
1040
1041 /* gpio6 */
1042 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1043         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1044         { .irq = -1 },
1045 };
1046
1047 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1048         { .role = "dbclk", .clk = "gpio6_dbck", },
1049 };
1050
1051 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1052         .name           = "gpio6",
1053         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054         .mpu_irqs       = omap3xxx_gpio6_irqs,
1055         .main_clk       = "gpio6_ick",
1056         .opt_clks       = gpio6_opt_clks,
1057         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1058         .prcm           = {
1059                 .omap2 = {
1060                         .prcm_reg_id = 1,
1061                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1062                         .module_offs = OMAP3430_PER_MOD,
1063                         .idlest_reg_id = 1,
1064                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1065                 },
1066         },
1067         .class          = &omap3xxx_gpio_hwmod_class,
1068         .dev_attr       = &gpio_dev_attr,
1069 };
1070
1071 /* dma attributes */
1072 static struct omap_dma_dev_attr dma_dev_attr = {
1073         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1074                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1075         .lch_count = 32,
1076 };
1077
1078 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1079         .rev_offs       = 0x0000,
1080         .sysc_offs      = 0x002c,
1081         .syss_offs      = 0x0028,
1082         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1083                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1084                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1085                            SYSS_HAS_RESET_STATUS),
1086         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1087                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1088         .sysc_fields    = &omap_hwmod_sysc_type1,
1089 };
1090
1091 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1092         .name = "dma",
1093         .sysc = &omap3xxx_dma_sysc,
1094 };
1095
1096 /* dma_system */
1097 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1098         .name           = "dma",
1099         .class          = &omap3xxx_dma_hwmod_class,
1100         .mpu_irqs       = omap2_dma_system_irqs,
1101         .main_clk       = "core_l3_ick",
1102         .prcm = {
1103                 .omap2 = {
1104                         .module_offs            = CORE_MOD,
1105                         .prcm_reg_id            = 1,
1106                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1107                         .idlest_reg_id          = 1,
1108                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1109                 },
1110         },
1111         .dev_attr       = &dma_dev_attr,
1112         .flags          = HWMOD_NO_IDLEST,
1113 };
1114
1115 /*
1116  * 'mcbsp' class
1117  * multi channel buffered serial port controller
1118  */
1119
1120 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1121         .sysc_offs      = 0x008c,
1122         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1123                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1124         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1125         .sysc_fields    = &omap_hwmod_sysc_type1,
1126         .clockact       = 0x2,
1127 };
1128
1129 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1130         .name = "mcbsp",
1131         .sysc = &omap3xxx_mcbsp_sysc,
1132         .rev  = MCBSP_CONFIG_TYPE3,
1133 };
1134
1135 /* McBSP functional clock mapping */
1136 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1137         { .role = "pad_fck", .clk = "mcbsp_clks" },
1138         { .role = "prcm_fck", .clk = "core_96m_fck" },
1139 };
1140
1141 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1142         { .role = "pad_fck", .clk = "mcbsp_clks" },
1143         { .role = "prcm_fck", .clk = "per_96m_fck" },
1144 };
1145
1146 /* mcbsp1 */
1147 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1148         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1149         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1150         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1151         { .irq = -1 },
1152 };
1153
1154 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1155         .name           = "mcbsp1",
1156         .class          = &omap3xxx_mcbsp_hwmod_class,
1157         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1158         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1159         .main_clk       = "mcbsp1_fck",
1160         .prcm           = {
1161                 .omap2 = {
1162                         .prcm_reg_id = 1,
1163                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1164                         .module_offs = CORE_MOD,
1165                         .idlest_reg_id = 1,
1166                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1167                 },
1168         },
1169         .opt_clks       = mcbsp15_opt_clks,
1170         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1171 };
1172
1173 /* mcbsp2 */
1174 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1175         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1176         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1177         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1178         { .irq = -1 },
1179 };
1180
1181 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1182         .sidetone       = "mcbsp2_sidetone",
1183 };
1184
1185 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1186         .name           = "mcbsp2",
1187         .class          = &omap3xxx_mcbsp_hwmod_class,
1188         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1189         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1190         .main_clk       = "mcbsp2_fck",
1191         .prcm           = {
1192                 .omap2 = {
1193                         .prcm_reg_id = 1,
1194                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1195                         .module_offs = OMAP3430_PER_MOD,
1196                         .idlest_reg_id = 1,
1197                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1198                 },
1199         },
1200         .opt_clks       = mcbsp234_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1202         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1203 };
1204
1205 /* mcbsp3 */
1206 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1207         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1208         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1209         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1210         { .irq = -1 },
1211 };
1212
1213 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1214         .sidetone       = "mcbsp3_sidetone",
1215 };
1216
1217 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1218         .name           = "mcbsp3",
1219         .class          = &omap3xxx_mcbsp_hwmod_class,
1220         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1221         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1222         .main_clk       = "mcbsp3_fck",
1223         .prcm           = {
1224                 .omap2 = {
1225                         .prcm_reg_id = 1,
1226                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1227                         .module_offs = OMAP3430_PER_MOD,
1228                         .idlest_reg_id = 1,
1229                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1230                 },
1231         },
1232         .opt_clks       = mcbsp234_opt_clks,
1233         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1234         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1235 };
1236
1237 /* mcbsp4 */
1238 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1239         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1240         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1241         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1242         { .irq = -1 },
1243 };
1244
1245 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1246         { .name = "rx", .dma_req = 20 },
1247         { .name = "tx", .dma_req = 19 },
1248         { .dma_req = -1 }
1249 };
1250
1251 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1252         .name           = "mcbsp4",
1253         .class          = &omap3xxx_mcbsp_hwmod_class,
1254         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1255         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1256         .main_clk       = "mcbsp4_fck",
1257         .prcm           = {
1258                 .omap2 = {
1259                         .prcm_reg_id = 1,
1260                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1261                         .module_offs = OMAP3430_PER_MOD,
1262                         .idlest_reg_id = 1,
1263                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1264                 },
1265         },
1266         .opt_clks       = mcbsp234_opt_clks,
1267         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1268 };
1269
1270 /* mcbsp5 */
1271 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1272         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1273         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1274         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1275         { .irq = -1 },
1276 };
1277
1278 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1279         { .name = "rx", .dma_req = 22 },
1280         { .name = "tx", .dma_req = 21 },
1281         { .dma_req = -1 }
1282 };
1283
1284 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1285         .name           = "mcbsp5",
1286         .class          = &omap3xxx_mcbsp_hwmod_class,
1287         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1288         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1289         .main_clk       = "mcbsp5_fck",
1290         .prcm           = {
1291                 .omap2 = {
1292                         .prcm_reg_id = 1,
1293                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1294                         .module_offs = CORE_MOD,
1295                         .idlest_reg_id = 1,
1296                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1297                 },
1298         },
1299         .opt_clks       = mcbsp15_opt_clks,
1300         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1301 };
1302
1303 /* 'mcbsp sidetone' class */
1304 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1305         .sysc_offs      = 0x0010,
1306         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1307         .sysc_fields    = &omap_hwmod_sysc_type1,
1308 };
1309
1310 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1311         .name = "mcbsp_sidetone",
1312         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1313 };
1314
1315 /* mcbsp2_sidetone */
1316 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1317         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1318         { .irq = -1 },
1319 };
1320
1321 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1322         .name           = "mcbsp2_sidetone",
1323         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1324         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1325         .main_clk       = "mcbsp2_fck",
1326         .prcm           = {
1327                 .omap2 = {
1328                         .prcm_reg_id = 1,
1329                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1330                         .module_offs = OMAP3430_PER_MOD,
1331                         .idlest_reg_id = 1,
1332                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1333                 },
1334         },
1335 };
1336
1337 /* mcbsp3_sidetone */
1338 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1339         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1340         { .irq = -1 },
1341 };
1342
1343 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1344         .name           = "mcbsp3_sidetone",
1345         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1346         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1347         .main_clk       = "mcbsp3_fck",
1348         .prcm           = {
1349                 .omap2 = {
1350                         .prcm_reg_id = 1,
1351                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1352                         .module_offs = OMAP3430_PER_MOD,
1353                         .idlest_reg_id = 1,
1354                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1355                 },
1356         },
1357 };
1358
1359 /* SR common */
1360 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1361         .clkact_shift   = 20,
1362 };
1363
1364 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1365         .sysc_offs      = 0x24,
1366         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1367         .clockact       = CLOCKACT_TEST_ICLK,
1368         .sysc_fields    = &omap34xx_sr_sysc_fields,
1369 };
1370
1371 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1372         .name = "smartreflex",
1373         .sysc = &omap34xx_sr_sysc,
1374         .rev  = 1,
1375 };
1376
1377 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1378         .sidle_shift    = 24,
1379         .enwkup_shift   = 26,
1380 };
1381
1382 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1383         .sysc_offs      = 0x38,
1384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1385         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1386                         SYSC_NO_CACHE),
1387         .sysc_fields    = &omap36xx_sr_sysc_fields,
1388 };
1389
1390 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1391         .name = "smartreflex",
1392         .sysc = &omap36xx_sr_sysc,
1393         .rev  = 2,
1394 };
1395
1396 /* SR1 */
1397 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1398         .sensor_voltdm_name   = "mpu_iva",
1399 };
1400
1401 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1402         { .irq = 18 + OMAP_INTC_START, },
1403         { .irq = -1 },
1404 };
1405
1406 static struct omap_hwmod omap34xx_sr1_hwmod = {
1407         .name           = "smartreflex_mpu_iva",
1408         .class          = &omap34xx_smartreflex_hwmod_class,
1409         .main_clk       = "sr1_fck",
1410         .prcm           = {
1411                 .omap2 = {
1412                         .prcm_reg_id = 1,
1413                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1414                         .module_offs = WKUP_MOD,
1415                         .idlest_reg_id = 1,
1416                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1417                 },
1418         },
1419         .dev_attr       = &sr1_dev_attr,
1420         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1421         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1422 };
1423
1424 static struct omap_hwmod omap36xx_sr1_hwmod = {
1425         .name           = "smartreflex_mpu_iva",
1426         .class          = &omap36xx_smartreflex_hwmod_class,
1427         .main_clk       = "sr1_fck",
1428         .prcm           = {
1429                 .omap2 = {
1430                         .prcm_reg_id = 1,
1431                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1432                         .module_offs = WKUP_MOD,
1433                         .idlest_reg_id = 1,
1434                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1435                 },
1436         },
1437         .dev_attr       = &sr1_dev_attr,
1438         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1439 };
1440
1441 /* SR2 */
1442 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1443         .sensor_voltdm_name     = "core",
1444 };
1445
1446 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1447         { .irq = 19 + OMAP_INTC_START, },
1448         { .irq = -1 },
1449 };
1450
1451 static struct omap_hwmod omap34xx_sr2_hwmod = {
1452         .name           = "smartreflex_core",
1453         .class          = &omap34xx_smartreflex_hwmod_class,
1454         .main_clk       = "sr2_fck",
1455         .prcm           = {
1456                 .omap2 = {
1457                         .prcm_reg_id = 1,
1458                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1459                         .module_offs = WKUP_MOD,
1460                         .idlest_reg_id = 1,
1461                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1462                 },
1463         },
1464         .dev_attr       = &sr2_dev_attr,
1465         .mpu_irqs       = omap3_smartreflex_core_irqs,
1466         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1467 };
1468
1469 static struct omap_hwmod omap36xx_sr2_hwmod = {
1470         .name           = "smartreflex_core",
1471         .class          = &omap36xx_smartreflex_hwmod_class,
1472         .main_clk       = "sr2_fck",
1473         .prcm           = {
1474                 .omap2 = {
1475                         .prcm_reg_id = 1,
1476                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1477                         .module_offs = WKUP_MOD,
1478                         .idlest_reg_id = 1,
1479                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1480                 },
1481         },
1482         .dev_attr       = &sr2_dev_attr,
1483         .mpu_irqs       = omap3_smartreflex_core_irqs,
1484 };
1485
1486 /*
1487  * 'mailbox' class
1488  * mailbox module allowing communication between the on-chip processors
1489  * using a queued mailbox-interrupt mechanism.
1490  */
1491
1492 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1493         .rev_offs       = 0x000,
1494         .sysc_offs      = 0x010,
1495         .syss_offs      = 0x014,
1496         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1497                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1498         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1499         .sysc_fields    = &omap_hwmod_sysc_type1,
1500 };
1501
1502 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1503         .name = "mailbox",
1504         .sysc = &omap3xxx_mailbox_sysc,
1505 };
1506
1507 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1508         .name           = "mailbox",
1509         .class          = &omap3xxx_mailbox_hwmod_class,
1510         .main_clk       = "mailboxes_ick",
1511         .prcm           = {
1512                 .omap2 = {
1513                         .prcm_reg_id = 1,
1514                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1515                         .module_offs = CORE_MOD,
1516                         .idlest_reg_id = 1,
1517                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1518                 },
1519         },
1520 };
1521
1522 /*
1523  * 'mcspi' class
1524  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1525  * bus
1526  */
1527
1528 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1529         .rev_offs       = 0x0000,
1530         .sysc_offs      = 0x0010,
1531         .syss_offs      = 0x0014,
1532         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1533                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1534                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1535         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1536         .sysc_fields    = &omap_hwmod_sysc_type1,
1537 };
1538
1539 static struct omap_hwmod_class omap34xx_mcspi_class = {
1540         .name = "mcspi",
1541         .sysc = &omap34xx_mcspi_sysc,
1542         .rev = OMAP3_MCSPI_REV,
1543 };
1544
1545 /* mcspi1 */
1546 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1547         .num_chipselect = 4,
1548 };
1549
1550 static struct omap_hwmod omap34xx_mcspi1 = {
1551         .name           = "mcspi1",
1552         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1553         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1554         .main_clk       = "mcspi1_fck",
1555         .prcm           = {
1556                 .omap2 = {
1557                         .module_offs = CORE_MOD,
1558                         .prcm_reg_id = 1,
1559                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1560                         .idlest_reg_id = 1,
1561                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1562                 },
1563         },
1564         .class          = &omap34xx_mcspi_class,
1565         .dev_attr       = &omap_mcspi1_dev_attr,
1566 };
1567
1568 /* mcspi2 */
1569 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1570         .num_chipselect = 2,
1571 };
1572
1573 static struct omap_hwmod omap34xx_mcspi2 = {
1574         .name           = "mcspi2",
1575         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1576         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1577         .main_clk       = "mcspi2_fck",
1578         .prcm           = {
1579                 .omap2 = {
1580                         .module_offs = CORE_MOD,
1581                         .prcm_reg_id = 1,
1582                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1583                         .idlest_reg_id = 1,
1584                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1585                 },
1586         },
1587         .class          = &omap34xx_mcspi_class,
1588         .dev_attr       = &omap_mcspi2_dev_attr,
1589 };
1590
1591 /* mcspi3 */
1592 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1593         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1594         { .irq = -1 },
1595 };
1596
1597 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1598         { .name = "tx0", .dma_req = 15 },
1599         { .name = "rx0", .dma_req = 16 },
1600         { .name = "tx1", .dma_req = 23 },
1601         { .name = "rx1", .dma_req = 24 },
1602         { .dma_req = -1 }
1603 };
1604
1605 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1606         .num_chipselect = 2,
1607 };
1608
1609 static struct omap_hwmod omap34xx_mcspi3 = {
1610         .name           = "mcspi3",
1611         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1612         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1613         .main_clk       = "mcspi3_fck",
1614         .prcm           = {
1615                 .omap2 = {
1616                         .module_offs = CORE_MOD,
1617                         .prcm_reg_id = 1,
1618                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1619                         .idlest_reg_id = 1,
1620                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1621                 },
1622         },
1623         .class          = &omap34xx_mcspi_class,
1624         .dev_attr       = &omap_mcspi3_dev_attr,
1625 };
1626
1627 /* mcspi4 */
1628 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1629         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1630         { .irq = -1 },
1631 };
1632
1633 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1634         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1635         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1636         { .dma_req = -1 }
1637 };
1638
1639 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1640         .num_chipselect = 1,
1641 };
1642
1643 static struct omap_hwmod omap34xx_mcspi4 = {
1644         .name           = "mcspi4",
1645         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1646         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1647         .main_clk       = "mcspi4_fck",
1648         .prcm           = {
1649                 .omap2 = {
1650                         .module_offs = CORE_MOD,
1651                         .prcm_reg_id = 1,
1652                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1653                         .idlest_reg_id = 1,
1654                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1655                 },
1656         },
1657         .class          = &omap34xx_mcspi_class,
1658         .dev_attr       = &omap_mcspi4_dev_attr,
1659 };
1660
1661 /* usbhsotg */
1662 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1663         .rev_offs       = 0x0400,
1664         .sysc_offs      = 0x0404,
1665         .syss_offs      = 0x0408,
1666         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1667                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1668                           SYSC_HAS_AUTOIDLE),
1669         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1670                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1671         .sysc_fields    = &omap_hwmod_sysc_type1,
1672 };
1673
1674 static struct omap_hwmod_class usbotg_class = {
1675         .name = "usbotg",
1676         .sysc = &omap3xxx_usbhsotg_sysc,
1677 };
1678
1679 /* usb_otg_hs */
1680 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1681
1682         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1683         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1684         { .irq = -1 },
1685 };
1686
1687 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1688         .name           = "usb_otg_hs",
1689         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1690         .main_clk       = "hsotgusb_ick",
1691         .prcm           = {
1692                 .omap2 = {
1693                         .prcm_reg_id = 1,
1694                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1695                         .module_offs = CORE_MOD,
1696                         .idlest_reg_id = 1,
1697                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1698                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1699                 },
1700         },
1701         .class          = &usbotg_class,
1702
1703         /*
1704          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1705          * broken when autoidle is enabled
1706          * workaround is to disable the autoidle bit at module level.
1707          *
1708          * Enabling the device in any other MIDLEMODE setting but force-idle
1709          * causes core_pwrdm not enter idle states at least on OMAP3630.
1710          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1711          * signal when MIDLEMODE is set to force-idle.
1712          */
1713         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1714                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1715 };
1716
1717 /* usb_otg_hs */
1718 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1719         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1720         { .irq = -1 },
1721 };
1722
1723 static struct omap_hwmod_class am35xx_usbotg_class = {
1724         .name = "am35xx_usbotg",
1725 };
1726
1727 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1728         .name           = "am35x_otg_hs",
1729         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1730         .main_clk       = "hsotgusb_fck",
1731         .class          = &am35xx_usbotg_class,
1732         .flags          = HWMOD_NO_IDLEST,
1733 };
1734
1735 /* MMC/SD/SDIO common */
1736 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1737         .rev_offs       = 0x1fc,
1738         .sysc_offs      = 0x10,
1739         .syss_offs      = 0x14,
1740         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1741                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1742                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1743         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1744         .sysc_fields    = &omap_hwmod_sysc_type1,
1745 };
1746
1747 static struct omap_hwmod_class omap34xx_mmc_class = {
1748         .name = "mmc",
1749         .sysc = &omap34xx_mmc_sysc,
1750 };
1751
1752 /* MMC/SD/SDIO1 */
1753
1754 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1755         { .irq = 83 + OMAP_INTC_START, },
1756         { .irq = -1 },
1757 };
1758
1759 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1760         { .name = "tx", .dma_req = 61, },
1761         { .name = "rx", .dma_req = 62, },
1762         { .dma_req = -1 }
1763 };
1764
1765 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1766         { .role = "dbck", .clk = "omap_32k_fck", },
1767 };
1768
1769 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1770         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1771 };
1772
1773 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1774 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1775         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1776                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1777 };
1778
1779 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1780         .name           = "mmc1",
1781         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1782         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1783         .opt_clks       = omap34xx_mmc1_opt_clks,
1784         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1785         .main_clk       = "mmchs1_fck",
1786         .prcm           = {
1787                 .omap2 = {
1788                         .module_offs = CORE_MOD,
1789                         .prcm_reg_id = 1,
1790                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1791                         .idlest_reg_id = 1,
1792                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1793                 },
1794         },
1795         .dev_attr       = &mmc1_pre_es3_dev_attr,
1796         .class          = &omap34xx_mmc_class,
1797 };
1798
1799 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1800         .name           = "mmc1",
1801         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1802         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1803         .opt_clks       = omap34xx_mmc1_opt_clks,
1804         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1805         .main_clk       = "mmchs1_fck",
1806         .prcm           = {
1807                 .omap2 = {
1808                         .module_offs = CORE_MOD,
1809                         .prcm_reg_id = 1,
1810                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1811                         .idlest_reg_id = 1,
1812                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1813                 },
1814         },
1815         .dev_attr       = &mmc1_dev_attr,
1816         .class          = &omap34xx_mmc_class,
1817 };
1818
1819 /* MMC/SD/SDIO2 */
1820
1821 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1822         { .irq = 86 + OMAP_INTC_START, },
1823         { .irq = -1 },
1824 };
1825
1826 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1827         { .name = "tx", .dma_req = 47, },
1828         { .name = "rx", .dma_req = 48, },
1829         { .dma_req = -1 }
1830 };
1831
1832 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1833         { .role = "dbck", .clk = "omap_32k_fck", },
1834 };
1835
1836 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1837 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1838         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1839 };
1840
1841 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1842         .name           = "mmc2",
1843         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1844         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1845         .opt_clks       = omap34xx_mmc2_opt_clks,
1846         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1847         .main_clk       = "mmchs2_fck",
1848         .prcm           = {
1849                 .omap2 = {
1850                         .module_offs = CORE_MOD,
1851                         .prcm_reg_id = 1,
1852                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1853                         .idlest_reg_id = 1,
1854                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1855                 },
1856         },
1857         .dev_attr       = &mmc2_pre_es3_dev_attr,
1858         .class          = &omap34xx_mmc_class,
1859 };
1860
1861 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1862         .name           = "mmc2",
1863         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1864         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1865         .opt_clks       = omap34xx_mmc2_opt_clks,
1866         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1867         .main_clk       = "mmchs2_fck",
1868         .prcm           = {
1869                 .omap2 = {
1870                         .module_offs = CORE_MOD,
1871                         .prcm_reg_id = 1,
1872                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1873                         .idlest_reg_id = 1,
1874                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1875                 },
1876         },
1877         .class          = &omap34xx_mmc_class,
1878 };
1879
1880 /* MMC/SD/SDIO3 */
1881
1882 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1883         { .irq = 94 + OMAP_INTC_START, },
1884         { .irq = -1 },
1885 };
1886
1887 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1888         { .name = "tx", .dma_req = 77, },
1889         { .name = "rx", .dma_req = 78, },
1890         { .dma_req = -1 }
1891 };
1892
1893 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1894         { .role = "dbck", .clk = "omap_32k_fck", },
1895 };
1896
1897 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1898         .name           = "mmc3",
1899         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1900         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1901         .opt_clks       = omap34xx_mmc3_opt_clks,
1902         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1903         .main_clk       = "mmchs3_fck",
1904         .prcm           = {
1905                 .omap2 = {
1906                         .prcm_reg_id = 1,
1907                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1908                         .idlest_reg_id = 1,
1909                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1910                 },
1911         },
1912         .class          = &omap34xx_mmc_class,
1913 };
1914
1915 /*
1916  * 'usb_host_hs' class
1917  * high-speed multi-port usb host controller
1918  */
1919
1920 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1921         .rev_offs       = 0x0000,
1922         .sysc_offs      = 0x0010,
1923         .syss_offs      = 0x0014,
1924         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1925                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1926                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1927                            SYSS_HAS_RESET_STATUS),
1928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1929                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1930         .sysc_fields    = &omap_hwmod_sysc_type1,
1931 };
1932
1933 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1934         .name = "usb_host_hs",
1935         .sysc = &omap3xxx_usb_host_hs_sysc,
1936 };
1937
1938 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1939         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1940         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1941         { .irq = -1 },
1942 };
1943
1944 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1945         .name           = "usb_host_hs",
1946         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1947         .clkdm_name     = "usbhost_clkdm",
1948         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1949         .main_clk       = "usbhost_48m_fck",
1950         .prcm = {
1951                 .omap2 = {
1952                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1953                         .prcm_reg_id = 1,
1954                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1955                         .idlest_reg_id = 1,
1956                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1957                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1958                 },
1959         },
1960
1961         /*
1962          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1963          * id: i660
1964          *
1965          * Description:
1966          * In the following configuration :
1967          * - USBHOST module is set to smart-idle mode
1968          * - PRCM asserts idle_req to the USBHOST module ( This typically
1969          *   happens when the system is going to a low power mode : all ports
1970          *   have been suspended, the master part of the USBHOST module has
1971          *   entered the standby state, and SW has cut the functional clocks)
1972          * - an USBHOST interrupt occurs before the module is able to answer
1973          *   idle_ack, typically a remote wakeup IRQ.
1974          * Then the USB HOST module will enter a deadlock situation where it
1975          * is no more accessible nor functional.
1976          *
1977          * Workaround:
1978          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1979          */
1980
1981         /*
1982          * Errata: USB host EHCI may stall when entering smart-standby mode
1983          * Id: i571
1984          *
1985          * Description:
1986          * When the USBHOST module is set to smart-standby mode, and when it is
1987          * ready to enter the standby state (i.e. all ports are suspended and
1988          * all attached devices are in suspend mode), then it can wrongly assert
1989          * the Mstandby signal too early while there are still some residual OCP
1990          * transactions ongoing. If this condition occurs, the internal state
1991          * machine may go to an undefined state and the USB link may be stuck
1992          * upon the next resume.
1993          *
1994          * Workaround:
1995          * Don't use smart standby; use only force standby,
1996          * hence HWMOD_SWSUP_MSTANDBY
1997          */
1998
1999         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2000 };
2001
2002 /*
2003  * 'usb_tll_hs' class
2004  * usb_tll_hs module is the adapter on the usb_host_hs ports
2005  */
2006 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2007         .rev_offs       = 0x0000,
2008         .sysc_offs      = 0x0010,
2009         .syss_offs      = 0x0014,
2010         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2011                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2012                            SYSC_HAS_AUTOIDLE),
2013         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2014         .sysc_fields    = &omap_hwmod_sysc_type1,
2015 };
2016
2017 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2018         .name = "usb_tll_hs",
2019         .sysc = &omap3xxx_usb_tll_hs_sysc,
2020 };
2021
2022 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2023         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2024         { .irq = -1 },
2025 };
2026
2027 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2028         .name           = "usb_tll_hs",
2029         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2030         .clkdm_name     = "core_l4_clkdm",
2031         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2032         .main_clk       = "usbtll_fck",
2033         .prcm = {
2034                 .omap2 = {
2035                         .module_offs = CORE_MOD,
2036                         .prcm_reg_id = 3,
2037                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2038                         .idlest_reg_id = 3,
2039                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2040                 },
2041         },
2042 };
2043
2044 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2045         .name           = "hdq1w",
2046         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2047         .main_clk       = "hdq_fck",
2048         .prcm           = {
2049                 .omap2 = {
2050                         .module_offs = CORE_MOD,
2051                         .prcm_reg_id = 1,
2052                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2053                         .idlest_reg_id = 1,
2054                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2055                 },
2056         },
2057         .class          = &omap2_hdq1w_class,
2058 };
2059
2060 /* SAD2D */
2061 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2062         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2063         { .name = "rst_modem_sw", .rst_shift = 1 },
2064 };
2065
2066 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2067         .name                   = "sad2d",
2068 };
2069
2070 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2071         .name           = "sad2d",
2072         .rst_lines      = omap3xxx_sad2d_resets,
2073         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2074         .main_clk       = "sad2d_ick",
2075         .prcm           = {
2076                 .omap2 = {
2077                         .module_offs = CORE_MOD,
2078                         .prcm_reg_id = 1,
2079                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2080                         .idlest_reg_id = 1,
2081                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2082                 },
2083         },
2084         .class          = &omap3xxx_sad2d_class,
2085 };
2086
2087 /*
2088  * '32K sync counter' class
2089  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2090  */
2091 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2092         .rev_offs       = 0x0000,
2093         .sysc_offs      = 0x0004,
2094         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2095         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2096         .sysc_fields    = &omap_hwmod_sysc_type1,
2097 };
2098
2099 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2100         .name   = "counter",
2101         .sysc   = &omap3xxx_counter_sysc,
2102 };
2103
2104 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2105         .name           = "counter_32k",
2106         .class          = &omap3xxx_counter_hwmod_class,
2107         .clkdm_name     = "wkup_clkdm",
2108         .flags          = HWMOD_SWSUP_SIDLE,
2109         .main_clk       = "wkup_32k_fck",
2110         .prcm           = {
2111                 .omap2  = {
2112                         .module_offs = WKUP_MOD,
2113                         .prcm_reg_id = 1,
2114                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2115                         .idlest_reg_id = 1,
2116                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2117                 },
2118         },
2119 };
2120
2121 /*
2122  * 'gpmc' class
2123  * general purpose memory controller
2124  */
2125
2126 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2127         .rev_offs       = 0x0000,
2128         .sysc_offs      = 0x0010,
2129         .syss_offs      = 0x0014,
2130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2131                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2133         .sysc_fields    = &omap_hwmod_sysc_type1,
2134 };
2135
2136 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2137         .name   = "gpmc",
2138         .sysc   = &omap3xxx_gpmc_sysc,
2139 };
2140
2141 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2142         { .irq = 20 + OMAP_INTC_START, },
2143         { .irq = -1 }
2144 };
2145
2146 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2147         .name           = "gpmc",
2148         .class          = &omap3xxx_gpmc_hwmod_class,
2149         .clkdm_name     = "core_l3_clkdm",
2150         .mpu_irqs       = omap3xxx_gpmc_irqs,
2151         .main_clk       = "gpmc_fck",
2152         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2153         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
2154 };
2155
2156 /*
2157  * interfaces
2158  */
2159
2160 /* L3 -> L4_CORE interface */
2161 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2162         .master = &omap3xxx_l3_main_hwmod,
2163         .slave  = &omap3xxx_l4_core_hwmod,
2164         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2165 };
2166
2167 /* L3 -> L4_PER interface */
2168 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2169         .master = &omap3xxx_l3_main_hwmod,
2170         .slave  = &omap3xxx_l4_per_hwmod,
2171         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2172 };
2173
2174 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2175         {
2176                 .pa_start       = 0x68000000,
2177                 .pa_end         = 0x6800ffff,
2178                 .flags          = ADDR_TYPE_RT,
2179         },
2180         { }
2181 };
2182
2183 /* MPU -> L3 interface */
2184 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2185         .master   = &omap3xxx_mpu_hwmod,
2186         .slave    = &omap3xxx_l3_main_hwmod,
2187         .addr     = omap3xxx_l3_main_addrs,
2188         .user   = OCP_USER_MPU,
2189 };
2190
2191 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2192         {
2193                 .pa_start       = 0x54000000,
2194                 .pa_end         = 0x547fffff,
2195                 .flags          = ADDR_TYPE_RT,
2196         },
2197         { }
2198 };
2199
2200 /* l3 -> debugss */
2201 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2202         .master         = &omap3xxx_l3_main_hwmod,
2203         .slave          = &omap3xxx_debugss_hwmod,
2204         .addr           = omap3xxx_l4_emu_addrs,
2205         .user           = OCP_USER_MPU,
2206 };
2207
2208 /* DSS -> l3 */
2209 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2210         .master         = &omap3430es1_dss_core_hwmod,
2211         .slave          = &omap3xxx_l3_main_hwmod,
2212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2213 };
2214
2215 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2216         .master         = &omap3xxx_dss_core_hwmod,
2217         .slave          = &omap3xxx_l3_main_hwmod,
2218         .fw = {
2219                 .omap2 = {
2220                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2221                         .flags  = OMAP_FIREWALL_L3,
2222                 }
2223         },
2224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2225 };
2226
2227 /* l3_core -> usbhsotg interface */
2228 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2229         .master         = &omap3xxx_usbhsotg_hwmod,
2230         .slave          = &omap3xxx_l3_main_hwmod,
2231         .clk            = "core_l3_ick",
2232         .user           = OCP_USER_MPU,
2233 };
2234
2235 /* l3_core -> am35xx_usbhsotg interface */
2236 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2237         .master         = &am35xx_usbhsotg_hwmod,
2238         .slave          = &omap3xxx_l3_main_hwmod,
2239         .clk            = "hsotgusb_ick",
2240         .user           = OCP_USER_MPU,
2241 };
2242
2243 /* l3_core -> sad2d interface */
2244 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2245         .master         = &omap3xxx_sad2d_hwmod,
2246         .slave          = &omap3xxx_l3_main_hwmod,
2247         .clk            = "core_l3_ick",
2248         .user           = OCP_USER_MPU,
2249 };
2250
2251 /* L4_CORE -> L4_WKUP interface */
2252 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2253         .master = &omap3xxx_l4_core_hwmod,
2254         .slave  = &omap3xxx_l4_wkup_hwmod,
2255         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 /* L4 CORE -> MMC1 interface */
2259 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2260         .master         = &omap3xxx_l4_core_hwmod,
2261         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2262         .clk            = "mmchs1_ick",
2263         .addr           = omap2430_mmc1_addr_space,
2264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2265         .flags          = OMAP_FIREWALL_L4
2266 };
2267
2268 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2269         .master         = &omap3xxx_l4_core_hwmod,
2270         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2271         .clk            = "mmchs1_ick",
2272         .addr           = omap2430_mmc1_addr_space,
2273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2274         .flags          = OMAP_FIREWALL_L4
2275 };
2276
2277 /* L4 CORE -> MMC2 interface */
2278 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2279         .master         = &omap3xxx_l4_core_hwmod,
2280         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2281         .clk            = "mmchs2_ick",
2282         .addr           = omap2430_mmc2_addr_space,
2283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2284         .flags          = OMAP_FIREWALL_L4
2285 };
2286
2287 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2288         .master         = &omap3xxx_l4_core_hwmod,
2289         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2290         .clk            = "mmchs2_ick",
2291         .addr           = omap2430_mmc2_addr_space,
2292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2293         .flags          = OMAP_FIREWALL_L4
2294 };
2295
2296 /* L4 CORE -> MMC3 interface */
2297 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2298         {
2299                 .pa_start       = 0x480ad000,
2300                 .pa_end         = 0x480ad1ff,
2301                 .flags          = ADDR_TYPE_RT,
2302         },
2303         { }
2304 };
2305
2306 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2307         .master         = &omap3xxx_l4_core_hwmod,
2308         .slave          = &omap3xxx_mmc3_hwmod,
2309         .clk            = "mmchs3_ick",
2310         .addr           = omap3xxx_mmc3_addr_space,
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312         .flags          = OMAP_FIREWALL_L4
2313 };
2314
2315 /* L4 CORE -> UART1 interface */
2316 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2317         {
2318                 .pa_start       = OMAP3_UART1_BASE,
2319                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2320                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2321         },
2322         { }
2323 };
2324
2325 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2326         .master         = &omap3xxx_l4_core_hwmod,
2327         .slave          = &omap3xxx_uart1_hwmod,
2328         .clk            = "uart1_ick",
2329         .addr           = omap3xxx_uart1_addr_space,
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332
2333 /* L4 CORE -> UART2 interface */
2334 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2335         {
2336                 .pa_start       = OMAP3_UART2_BASE,
2337                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2338                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2339         },
2340         { }
2341 };
2342
2343 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2344         .master         = &omap3xxx_l4_core_hwmod,
2345         .slave          = &omap3xxx_uart2_hwmod,
2346         .clk            = "uart2_ick",
2347         .addr           = omap3xxx_uart2_addr_space,
2348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2349 };
2350
2351 /* L4 PER -> UART3 interface */
2352 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2353         {
2354                 .pa_start       = OMAP3_UART3_BASE,
2355                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2356                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2357         },
2358         { }
2359 };
2360
2361 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2362         .master         = &omap3xxx_l4_per_hwmod,
2363         .slave          = &omap3xxx_uart3_hwmod,
2364         .clk            = "uart3_ick",
2365         .addr           = omap3xxx_uart3_addr_space,
2366         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2367 };
2368
2369 /* L4 PER -> UART4 interface */
2370 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2371         {
2372                 .pa_start       = OMAP3_UART4_BASE,
2373                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2374                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2375         },
2376         { }
2377 };
2378
2379 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2380         .master         = &omap3xxx_l4_per_hwmod,
2381         .slave          = &omap36xx_uart4_hwmod,
2382         .clk            = "uart4_ick",
2383         .addr           = omap36xx_uart4_addr_space,
2384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2385 };
2386
2387 /* AM35xx: L4 CORE -> UART4 interface */
2388 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2389         {
2390                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2391                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2392                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2393         },
2394         { }
2395 };
2396
2397 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2398         .master         = &omap3xxx_l4_core_hwmod,
2399         .slave          = &am35xx_uart4_hwmod,
2400         .clk            = "uart4_ick",
2401         .addr           = am35xx_uart4_addr_space,
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* L4 CORE -> I2C1 interface */
2406 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2407         .master         = &omap3xxx_l4_core_hwmod,
2408         .slave          = &omap3xxx_i2c1_hwmod,
2409         .clk            = "i2c1_ick",
2410         .addr           = omap2_i2c1_addr_space,
2411         .fw = {
2412                 .omap2 = {
2413                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2414                         .l4_prot_group = 7,
2415                         .flags  = OMAP_FIREWALL_L4,
2416                 }
2417         },
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420
2421 /* L4 CORE -> I2C2 interface */
2422 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2423         .master         = &omap3xxx_l4_core_hwmod,
2424         .slave          = &omap3xxx_i2c2_hwmod,
2425         .clk            = "i2c2_ick",
2426         .addr           = omap2_i2c2_addr_space,
2427         .fw = {
2428                 .omap2 = {
2429                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2430                         .l4_prot_group = 7,
2431                         .flags = OMAP_FIREWALL_L4,
2432                 }
2433         },
2434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436
2437 /* L4 CORE -> I2C3 interface */
2438 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2439         {
2440                 .pa_start       = 0x48060000,
2441                 .pa_end         = 0x48060000 + SZ_128 - 1,
2442                 .flags          = ADDR_TYPE_RT,
2443         },
2444         { }
2445 };
2446
2447 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2448         .master         = &omap3xxx_l4_core_hwmod,
2449         .slave          = &omap3xxx_i2c3_hwmod,
2450         .clk            = "i2c3_ick",
2451         .addr           = omap3xxx_i2c3_addr_space,
2452         .fw = {
2453                 .omap2 = {
2454                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2455                         .l4_prot_group = 7,
2456                         .flags = OMAP_FIREWALL_L4,
2457                 }
2458         },
2459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2460 };
2461
2462 /* L4 CORE -> SR1 interface */
2463 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2464         {
2465                 .pa_start       = OMAP34XX_SR1_BASE,
2466                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2467                 .flags          = ADDR_TYPE_RT,
2468         },
2469         { }
2470 };
2471
2472 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2473         .master         = &omap3xxx_l4_core_hwmod,
2474         .slave          = &omap34xx_sr1_hwmod,
2475         .clk            = "sr_l4_ick",
2476         .addr           = omap3_sr1_addr_space,
2477         .user           = OCP_USER_MPU,
2478 };
2479
2480 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2481         .master         = &omap3xxx_l4_core_hwmod,
2482         .slave          = &omap36xx_sr1_hwmod,
2483         .clk            = "sr_l4_ick",
2484         .addr           = omap3_sr1_addr_space,
2485         .user           = OCP_USER_MPU,
2486 };
2487
2488 /* L4 CORE -> SR1 interface */
2489 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2490         {
2491                 .pa_start       = OMAP34XX_SR2_BASE,
2492                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2493                 .flags          = ADDR_TYPE_RT,
2494         },
2495         { }
2496 };
2497
2498 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2499         .master         = &omap3xxx_l4_core_hwmod,
2500         .slave          = &omap34xx_sr2_hwmod,
2501         .clk            = "sr_l4_ick",
2502         .addr           = omap3_sr2_addr_space,
2503         .user           = OCP_USER_MPU,
2504 };
2505
2506 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2507         .master         = &omap3xxx_l4_core_hwmod,
2508         .slave          = &omap36xx_sr2_hwmod,
2509         .clk            = "sr_l4_ick",
2510         .addr           = omap3_sr2_addr_space,
2511         .user           = OCP_USER_MPU,
2512 };
2513
2514 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2515         {
2516                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2517                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2518                 .flags          = ADDR_TYPE_RT
2519         },
2520         { }
2521 };
2522
2523 /* l4_core -> usbhsotg  */
2524 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2525         .master         = &omap3xxx_l4_core_hwmod,
2526         .slave          = &omap3xxx_usbhsotg_hwmod,
2527         .clk            = "l4_ick",
2528         .addr           = omap3xxx_usbhsotg_addrs,
2529         .user           = OCP_USER_MPU,
2530 };
2531
2532 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2533         {
2534                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2535                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2536                 .flags          = ADDR_TYPE_RT
2537         },
2538         { }
2539 };
2540
2541 /* l4_core -> usbhsotg  */
2542 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2543         .master         = &omap3xxx_l4_core_hwmod,
2544         .slave          = &am35xx_usbhsotg_hwmod,
2545         .clk            = "hsotgusb_ick",
2546         .addr           = am35xx_usbhsotg_addrs,
2547         .user           = OCP_USER_MPU,
2548 };
2549
2550 /* L4_WKUP -> L4_SEC interface */
2551 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2552         .master = &omap3xxx_l4_wkup_hwmod,
2553         .slave  = &omap3xxx_l4_sec_hwmod,
2554         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2555 };
2556
2557 /* IVA2 <- L3 interface */
2558 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2559         .master         = &omap3xxx_l3_main_hwmod,
2560         .slave          = &omap3xxx_iva_hwmod,
2561         .clk            = "core_l3_ick",
2562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2563 };
2564
2565 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2566         {
2567                 .pa_start       = 0x48318000,
2568                 .pa_end         = 0x48318000 + SZ_1K - 1,
2569                 .flags          = ADDR_TYPE_RT
2570         },
2571         { }
2572 };
2573
2574 /* l4_wkup -> timer1 */
2575 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2576         .master         = &omap3xxx_l4_wkup_hwmod,
2577         .slave          = &omap3xxx_timer1_hwmod,
2578         .clk            = "gpt1_ick",
2579         .addr           = omap3xxx_timer1_addrs,
2580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2584         {
2585                 .pa_start       = 0x49032000,
2586                 .pa_end         = 0x49032000 + SZ_1K - 1,
2587                 .flags          = ADDR_TYPE_RT
2588         },
2589         { }
2590 };
2591
2592 /* l4_per -> timer2 */
2593 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2594         .master         = &omap3xxx_l4_per_hwmod,
2595         .slave          = &omap3xxx_timer2_hwmod,
2596         .clk            = "gpt2_ick",
2597         .addr           = omap3xxx_timer2_addrs,
2598         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2599 };
2600
2601 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2602         {
2603                 .pa_start       = 0x49034000,
2604                 .pa_end         = 0x49034000 + SZ_1K - 1,
2605                 .flags          = ADDR_TYPE_RT
2606         },
2607         { }
2608 };
2609
2610 /* l4_per -> timer3 */
2611 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2612         .master         = &omap3xxx_l4_per_hwmod,
2613         .slave          = &omap3xxx_timer3_hwmod,
2614         .clk            = "gpt3_ick",
2615         .addr           = omap3xxx_timer3_addrs,
2616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2617 };
2618
2619 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2620         {
2621                 .pa_start       = 0x49036000,
2622                 .pa_end         = 0x49036000 + SZ_1K - 1,
2623                 .flags          = ADDR_TYPE_RT
2624         },
2625         { }
2626 };
2627
2628 /* l4_per -> timer4 */
2629 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2630         .master         = &omap3xxx_l4_per_hwmod,
2631         .slave          = &omap3xxx_timer4_hwmod,
2632         .clk            = "gpt4_ick",
2633         .addr           = omap3xxx_timer4_addrs,
2634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2635 };
2636
2637 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2638         {
2639                 .pa_start       = 0x49038000,
2640                 .pa_end         = 0x49038000 + SZ_1K - 1,
2641                 .flags          = ADDR_TYPE_RT
2642         },
2643         { }
2644 };
2645
2646 /* l4_per -> timer5 */
2647 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2648         .master         = &omap3xxx_l4_per_hwmod,
2649         .slave          = &omap3xxx_timer5_hwmod,
2650         .clk            = "gpt5_ick",
2651         .addr           = omap3xxx_timer5_addrs,
2652         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2656         {
2657                 .pa_start       = 0x4903A000,
2658                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2659                 .flags          = ADDR_TYPE_RT
2660         },
2661         { }
2662 };
2663
2664 /* l4_per -> timer6 */
2665 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2666         .master         = &omap3xxx_l4_per_hwmod,
2667         .slave          = &omap3xxx_timer6_hwmod,
2668         .clk            = "gpt6_ick",
2669         .addr           = omap3xxx_timer6_addrs,
2670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2671 };
2672
2673 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2674         {
2675                 .pa_start       = 0x4903C000,
2676                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2677                 .flags          = ADDR_TYPE_RT
2678         },
2679         { }
2680 };
2681
2682 /* l4_per -> timer7 */
2683 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2684         .master         = &omap3xxx_l4_per_hwmod,
2685         .slave          = &omap3xxx_timer7_hwmod,
2686         .clk            = "gpt7_ick",
2687         .addr           = omap3xxx_timer7_addrs,
2688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2689 };
2690
2691 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2692         {
2693                 .pa_start       = 0x4903E000,
2694                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2695                 .flags          = ADDR_TYPE_RT
2696         },
2697         { }
2698 };
2699
2700 /* l4_per -> timer8 */
2701 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2702         .master         = &omap3xxx_l4_per_hwmod,
2703         .slave          = &omap3xxx_timer8_hwmod,
2704         .clk            = "gpt8_ick",
2705         .addr           = omap3xxx_timer8_addrs,
2706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2707 };
2708
2709 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2710         {
2711                 .pa_start       = 0x49040000,
2712                 .pa_end         = 0x49040000 + SZ_1K - 1,
2713                 .flags          = ADDR_TYPE_RT
2714         },
2715         { }
2716 };
2717
2718 /* l4_per -> timer9 */
2719 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2720         .master         = &omap3xxx_l4_per_hwmod,
2721         .slave          = &omap3xxx_timer9_hwmod,
2722         .clk            = "gpt9_ick",
2723         .addr           = omap3xxx_timer9_addrs,
2724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* l4_core -> timer10 */
2728 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2729         .master         = &omap3xxx_l4_core_hwmod,
2730         .slave          = &omap3xxx_timer10_hwmod,
2731         .clk            = "gpt10_ick",
2732         .addr           = omap2_timer10_addrs,
2733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 /* l4_core -> timer11 */
2737 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2738         .master         = &omap3xxx_l4_core_hwmod,
2739         .slave          = &omap3xxx_timer11_hwmod,
2740         .clk            = "gpt11_ick",
2741         .addr           = omap2_timer11_addrs,
2742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2743 };
2744
2745 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2746         {
2747                 .pa_start       = 0x48304000,
2748                 .pa_end         = 0x48304000 + SZ_1K - 1,
2749                 .flags          = ADDR_TYPE_RT
2750         },
2751         { }
2752 };
2753
2754 /* l4_core -> timer12 */
2755 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2756         .master         = &omap3xxx_l4_sec_hwmod,
2757         .slave          = &omap3xxx_timer12_hwmod,
2758         .clk            = "gpt12_ick",
2759         .addr           = omap3xxx_timer12_addrs,
2760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2761 };
2762
2763 /* l4_wkup -> wd_timer2 */
2764 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2765         {
2766                 .pa_start       = 0x48314000,
2767                 .pa_end         = 0x4831407f,
2768                 .flags          = ADDR_TYPE_RT
2769         },
2770         { }
2771 };
2772
2773 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2774         .master         = &omap3xxx_l4_wkup_hwmod,
2775         .slave          = &omap3xxx_wd_timer2_hwmod,
2776         .clk            = "wdt2_ick",
2777         .addr           = omap3xxx_wd_timer2_addrs,
2778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2779 };
2780
2781 /* l4_core -> dss */
2782 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2783         .master         = &omap3xxx_l4_core_hwmod,
2784         .slave          = &omap3430es1_dss_core_hwmod,
2785         .clk            = "dss_ick",
2786         .addr           = omap2_dss_addrs,
2787         .fw = {
2788                 .omap2 = {
2789                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2790                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2791                         .flags  = OMAP_FIREWALL_L4,
2792                 }
2793         },
2794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2795 };
2796
2797 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2798         .master         = &omap3xxx_l4_core_hwmod,
2799         .slave          = &omap3xxx_dss_core_hwmod,
2800         .clk            = "dss_ick",
2801         .addr           = omap2_dss_addrs,
2802         .fw = {
2803                 .omap2 = {
2804                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2805                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2806                         .flags  = OMAP_FIREWALL_L4,
2807                 }
2808         },
2809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2810 };
2811
2812 /* l4_core -> dss_dispc */
2813 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2814         .master         = &omap3xxx_l4_core_hwmod,
2815         .slave          = &omap3xxx_dss_dispc_hwmod,
2816         .clk            = "dss_ick",
2817         .addr           = omap2_dss_dispc_addrs,
2818         .fw = {
2819                 .omap2 = {
2820                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2821                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2822                         .flags  = OMAP_FIREWALL_L4,
2823                 }
2824         },
2825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2826 };
2827
2828 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2829         {
2830                 .pa_start       = 0x4804FC00,
2831                 .pa_end         = 0x4804FFFF,
2832                 .flags          = ADDR_TYPE_RT
2833         },
2834         { }
2835 };
2836
2837 /* l4_core -> dss_dsi1 */
2838 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2839         .master         = &omap3xxx_l4_core_hwmod,
2840         .slave          = &omap3xxx_dss_dsi1_hwmod,
2841         .clk            = "dss_ick",
2842         .addr           = omap3xxx_dss_dsi1_addrs,
2843         .fw = {
2844                 .omap2 = {
2845                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2846                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2847                         .flags  = OMAP_FIREWALL_L4,
2848                 }
2849         },
2850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2851 };
2852
2853 /* l4_core -> dss_rfbi */
2854 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2855         .master         = &omap3xxx_l4_core_hwmod,
2856         .slave          = &omap3xxx_dss_rfbi_hwmod,
2857         .clk            = "dss_ick",
2858         .addr           = omap2_dss_rfbi_addrs,
2859         .fw = {
2860                 .omap2 = {
2861                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2862                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2863                         .flags  = OMAP_FIREWALL_L4,
2864                 }
2865         },
2866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2867 };
2868
2869 /* l4_core -> dss_venc */
2870 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2871         .master         = &omap3xxx_l4_core_hwmod,
2872         .slave          = &omap3xxx_dss_venc_hwmod,
2873         .clk            = "dss_ick",
2874         .addr           = omap2_dss_venc_addrs,
2875         .fw = {
2876                 .omap2 = {
2877                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2878                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2879                         .flags  = OMAP_FIREWALL_L4,
2880                 }
2881         },
2882         .flags          = OCPIF_SWSUP_IDLE,
2883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2884 };
2885
2886 /* l4_wkup -> gpio1 */
2887 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2888         {
2889                 .pa_start       = 0x48310000,
2890                 .pa_end         = 0x483101ff,
2891                 .flags          = ADDR_TYPE_RT
2892         },
2893         { }
2894 };
2895
2896 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2897         .master         = &omap3xxx_l4_wkup_hwmod,
2898         .slave          = &omap3xxx_gpio1_hwmod,
2899         .addr           = omap3xxx_gpio1_addrs,
2900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* l4_per -> gpio2 */
2904 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2905         {
2906                 .pa_start       = 0x49050000,
2907                 .pa_end         = 0x490501ff,
2908                 .flags          = ADDR_TYPE_RT
2909         },
2910         { }
2911 };
2912
2913 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2914         .master         = &omap3xxx_l4_per_hwmod,
2915         .slave          = &omap3xxx_gpio2_hwmod,
2916         .addr           = omap3xxx_gpio2_addrs,
2917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2918 };
2919
2920 /* l4_per -> gpio3 */
2921 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2922         {
2923                 .pa_start       = 0x49052000,
2924                 .pa_end         = 0x490521ff,
2925                 .flags          = ADDR_TYPE_RT
2926         },
2927         { }
2928 };
2929
2930 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2931         .master         = &omap3xxx_l4_per_hwmod,
2932         .slave          = &omap3xxx_gpio3_hwmod,
2933         .addr           = omap3xxx_gpio3_addrs,
2934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2935 };
2936
2937 /*
2938  * 'mmu' class
2939  * The memory management unit performs virtual to physical address translation
2940  * for its requestors.
2941  */
2942
2943 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2944         .rev_offs       = 0x000,
2945         .sysc_offs      = 0x010,
2946         .syss_offs      = 0x014,
2947         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2948                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2949         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2950         .sysc_fields    = &omap_hwmod_sysc_type1,
2951 };
2952
2953 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2954         .name = "mmu",
2955         .sysc = &mmu_sysc,
2956 };
2957
2958 /* mmu isp */
2959 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2960
2961 /* l4_core -> mmu isp */
2962 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2963         .master         = &omap3xxx_l4_core_hwmod,
2964         .slave          = &omap3xxx_mmu_isp_hwmod,
2965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2966 };
2967
2968 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2969         .name           = "mmu_isp",
2970         .class          = &omap3xxx_mmu_hwmod_class,
2971         .main_clk       = "cam_ick",
2972         .flags          = HWMOD_NO_IDLEST,
2973 };
2974
2975 /* mmu iva */
2976
2977 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2978
2979 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2980         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2981 };
2982
2983 /* l3_main -> iva mmu */
2984 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2985         .master         = &omap3xxx_l3_main_hwmod,
2986         .slave          = &omap3xxx_mmu_iva_hwmod,
2987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2988 };
2989
2990 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2991         .name           = "mmu_iva",
2992         .class          = &omap3xxx_mmu_hwmod_class,
2993         .clkdm_name     = "iva2_clkdm",
2994         .rst_lines      = omap3xxx_mmu_iva_resets,
2995         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2996         .main_clk       = "iva2_ck",
2997         .prcm = {
2998                 .omap2 = {
2999                         .module_offs = OMAP3430_IVA2_MOD,
3000                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
3001                         .idlest_reg_id = 1,
3002                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
3003                 },
3004         },
3005         .flags          = HWMOD_NO_IDLEST,
3006 };
3007
3008 /* l4_per -> gpio4 */
3009 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3010         {
3011                 .pa_start       = 0x49054000,
3012                 .pa_end         = 0x490541ff,
3013                 .flags          = ADDR_TYPE_RT
3014         },
3015         { }
3016 };
3017
3018 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3019         .master         = &omap3xxx_l4_per_hwmod,
3020         .slave          = &omap3xxx_gpio4_hwmod,
3021         .addr           = omap3xxx_gpio4_addrs,
3022         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3023 };
3024
3025 /* l4_per -> gpio5 */
3026 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3027         {
3028                 .pa_start       = 0x49056000,
3029                 .pa_end         = 0x490561ff,
3030                 .flags          = ADDR_TYPE_RT
3031         },
3032         { }
3033 };
3034
3035 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3036         .master         = &omap3xxx_l4_per_hwmod,
3037         .slave          = &omap3xxx_gpio5_hwmod,
3038         .addr           = omap3xxx_gpio5_addrs,
3039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3040 };
3041
3042 /* l4_per -> gpio6 */
3043 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3044         {
3045                 .pa_start       = 0x49058000,
3046                 .pa_end         = 0x490581ff,
3047                 .flags          = ADDR_TYPE_RT
3048         },
3049         { }
3050 };
3051
3052 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3053         .master         = &omap3xxx_l4_per_hwmod,
3054         .slave          = &omap3xxx_gpio6_hwmod,
3055         .addr           = omap3xxx_gpio6_addrs,
3056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3057 };
3058
3059 /* dma_system -> L3 */
3060 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3061         .master         = &omap3xxx_dma_system_hwmod,
3062         .slave          = &omap3xxx_l3_main_hwmod,
3063         .clk            = "core_l3_ick",
3064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3065 };
3066
3067 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3068         {
3069                 .pa_start       = 0x48056000,
3070                 .pa_end         = 0x48056fff,
3071                 .flags          = ADDR_TYPE_RT
3072         },
3073         { }
3074 };
3075
3076 /* l4_cfg -> dma_system */
3077 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3078         .master         = &omap3xxx_l4_core_hwmod,
3079         .slave          = &omap3xxx_dma_system_hwmod,
3080         .clk            = "core_l4_ick",
3081         .addr           = omap3xxx_dma_system_addrs,
3082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3083 };
3084
3085 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3086         {
3087                 .name           = "mpu",
3088                 .pa_start       = 0x48074000,
3089                 .pa_end         = 0x480740ff,
3090                 .flags          = ADDR_TYPE_RT
3091         },
3092         { }
3093 };
3094
3095 /* l4_core -> mcbsp1 */
3096 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3097         .master         = &omap3xxx_l4_core_hwmod,
3098         .slave          = &omap3xxx_mcbsp1_hwmod,
3099         .clk            = "mcbsp1_ick",
3100         .addr           = omap3xxx_mcbsp1_addrs,
3101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3102 };
3103
3104 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3105         {
3106                 .name           = "mpu",
3107                 .pa_start       = 0x49022000,
3108                 .pa_end         = 0x490220ff,
3109                 .flags          = ADDR_TYPE_RT
3110         },
3111         { }
3112 };
3113
3114 /* l4_per -> mcbsp2 */
3115 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3116         .master         = &omap3xxx_l4_per_hwmod,
3117         .slave          = &omap3xxx_mcbsp2_hwmod,
3118         .clk            = "mcbsp2_ick",
3119         .addr           = omap3xxx_mcbsp2_addrs,
3120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3124         {
3125                 .name           = "mpu",
3126                 .pa_start       = 0x49024000,
3127                 .pa_end         = 0x490240ff,
3128                 .flags          = ADDR_TYPE_RT
3129         },
3130         { }
3131 };
3132
3133 /* l4_per -> mcbsp3 */
3134 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3135         .master         = &omap3xxx_l4_per_hwmod,
3136         .slave          = &omap3xxx_mcbsp3_hwmod,
3137         .clk            = "mcbsp3_ick",
3138         .addr           = omap3xxx_mcbsp3_addrs,
3139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3140 };
3141
3142 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3143         {
3144                 .name           = "mpu",
3145                 .pa_start       = 0x49026000,
3146                 .pa_end         = 0x490260ff,
3147                 .flags          = ADDR_TYPE_RT
3148         },
3149         { }
3150 };
3151
3152 /* l4_per -> mcbsp4 */
3153 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3154         .master         = &omap3xxx_l4_per_hwmod,
3155         .slave          = &omap3xxx_mcbsp4_hwmod,
3156         .clk            = "mcbsp4_ick",
3157         .addr           = omap3xxx_mcbsp4_addrs,
3158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3159 };
3160
3161 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3162         {
3163                 .name           = "mpu",
3164                 .pa_start       = 0x48096000,
3165                 .pa_end         = 0x480960ff,
3166                 .flags          = ADDR_TYPE_RT
3167         },
3168         { }
3169 };
3170
3171 /* l4_core -> mcbsp5 */
3172 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3173         .master         = &omap3xxx_l4_core_hwmod,
3174         .slave          = &omap3xxx_mcbsp5_hwmod,
3175         .clk            = "mcbsp5_ick",
3176         .addr           = omap3xxx_mcbsp5_addrs,
3177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3178 };
3179
3180 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3181         {
3182                 .name           = "sidetone",
3183                 .pa_start       = 0x49028000,
3184                 .pa_end         = 0x490280ff,
3185                 .flags          = ADDR_TYPE_RT
3186         },
3187         { }
3188 };
3189
3190 /* l4_per -> mcbsp2_sidetone */
3191 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3192         .master         = &omap3xxx_l4_per_hwmod,
3193         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3194         .clk            = "mcbsp2_ick",
3195         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3196         .user           = OCP_USER_MPU,
3197 };
3198
3199 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3200         {
3201                 .name           = "sidetone",
3202                 .pa_start       = 0x4902A000,
3203                 .pa_end         = 0x4902A0ff,
3204                 .flags          = ADDR_TYPE_RT
3205         },
3206         { }
3207 };
3208
3209 /* l4_per -> mcbsp3_sidetone */
3210 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3211         .master         = &omap3xxx_l4_per_hwmod,
3212         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3213         .clk            = "mcbsp3_ick",
3214         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3215         .user           = OCP_USER_MPU,
3216 };
3217
3218 /* l4_core -> mailbox */
3219 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3220         .master         = &omap3xxx_l4_core_hwmod,
3221         .slave          = &omap3xxx_mailbox_hwmod,
3222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3224
3225 /* l4 core -> mcspi1 interface */
3226 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3227         .master         = &omap3xxx_l4_core_hwmod,
3228         .slave          = &omap34xx_mcspi1,
3229         .clk            = "mcspi1_ick",
3230         .addr           = omap2_mcspi1_addr_space,
3231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3232 };
3233
3234 /* l4 core -> mcspi2 interface */
3235 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3236         .master         = &omap3xxx_l4_core_hwmod,
3237         .slave          = &omap34xx_mcspi2,
3238         .clk            = "mcspi2_ick",
3239         .addr           = omap2_mcspi2_addr_space,
3240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* l4 core -> mcspi3 interface */
3244 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3245         .master         = &omap3xxx_l4_core_hwmod,
3246         .slave          = &omap34xx_mcspi3,
3247         .clk            = "mcspi3_ick",
3248         .addr           = omap2430_mcspi3_addr_space,
3249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 /* l4 core -> mcspi4 interface */
3253 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3254         {
3255                 .pa_start       = 0x480ba000,
3256                 .pa_end         = 0x480ba0ff,
3257                 .flags          = ADDR_TYPE_RT,
3258         },
3259         { }
3260 };
3261
3262 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3263         .master         = &omap3xxx_l4_core_hwmod,
3264         .slave          = &omap34xx_mcspi4,
3265         .clk            = "mcspi4_ick",
3266         .addr           = omap34xx_mcspi4_addr_space,
3267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3268 };
3269
3270 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3271         .master         = &omap3xxx_usb_host_hs_hwmod,
3272         .slave          = &omap3xxx_l3_main_hwmod,
3273         .clk            = "core_l3_ick",
3274         .user           = OCP_USER_MPU,
3275 };
3276
3277 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3278         {
3279                 .name           = "uhh",
3280                 .pa_start       = 0x48064000,
3281                 .pa_end         = 0x480643ff,
3282                 .flags          = ADDR_TYPE_RT
3283         },
3284         {
3285                 .name           = "ohci",
3286                 .pa_start       = 0x48064400,
3287                 .pa_end         = 0x480647ff,
3288         },
3289         {
3290                 .name           = "ehci",
3291                 .pa_start       = 0x48064800,
3292                 .pa_end         = 0x48064cff,
3293         },
3294         {}
3295 };
3296
3297 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3298         .master         = &omap3xxx_l4_core_hwmod,
3299         .slave          = &omap3xxx_usb_host_hs_hwmod,
3300         .clk            = "usbhost_ick",
3301         .addr           = omap3xxx_usb_host_hs_addrs,
3302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3303 };
3304
3305 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3306         {
3307                 .name           = "tll",
3308                 .pa_start       = 0x48062000,
3309                 .pa_end         = 0x48062fff,
3310                 .flags          = ADDR_TYPE_RT
3311         },
3312         {}
3313 };
3314
3315 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3316         .master         = &omap3xxx_l4_core_hwmod,
3317         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3318         .clk            = "usbtll_ick",
3319         .addr           = omap3xxx_usb_tll_hs_addrs,
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* l4_core -> hdq1w interface */
3324 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3325         .master         = &omap3xxx_l4_core_hwmod,
3326         .slave          = &omap3xxx_hdq1w_hwmod,
3327         .clk            = "hdq_ick",
3328         .addr           = omap2_hdq1w_addr_space,
3329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3330         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3331 };
3332
3333 /* l4_wkup -> 32ksync_counter */
3334 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3335         {
3336                 .pa_start       = 0x48320000,
3337                 .pa_end         = 0x4832001f,
3338                 .flags          = ADDR_TYPE_RT
3339         },
3340         { }
3341 };
3342
3343 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3344         {
3345                 .pa_start       = 0x6e000000,
3346                 .pa_end         = 0x6e000fff,
3347                 .flags          = ADDR_TYPE_RT
3348         },
3349         { }
3350 };
3351
3352 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3353         .master         = &omap3xxx_l4_wkup_hwmod,
3354         .slave          = &omap3xxx_counter_32k_hwmod,
3355         .clk            = "omap_32ksync_ick",
3356         .addr           = omap3xxx_counter_32k_addrs,
3357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3358 };
3359
3360 /* am35xx has Davinci MDIO & EMAC */
3361 static struct omap_hwmod_class am35xx_mdio_class = {
3362         .name = "davinci_mdio",
3363 };
3364
3365 static struct omap_hwmod am35xx_mdio_hwmod = {
3366         .name           = "davinci_mdio",
3367         .class          = &am35xx_mdio_class,
3368         .flags          = HWMOD_NO_IDLEST,
3369 };
3370
3371 /*
3372  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3373  * but this will probably require some additional hwmod core support,
3374  * so is left as a future to-do item.
3375  */
3376 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3377         .master         = &am35xx_mdio_hwmod,
3378         .slave          = &omap3xxx_l3_main_hwmod,
3379         .clk            = "emac_fck",
3380         .user           = OCP_USER_MPU,
3381 };
3382
3383 /* l4_core -> davinci mdio  */
3384 /*
3385  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3386  * but this will probably require some additional hwmod core support,
3387  * so is left as a future to-do item.
3388  */
3389 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3390         .master         = &omap3xxx_l4_core_hwmod,
3391         .slave          = &am35xx_mdio_hwmod,
3392         .clk            = "emac_fck",
3393         .user           = OCP_USER_MPU,
3394 };
3395
3396 static struct omap_hwmod_class am35xx_emac_class = {
3397         .name = "davinci_emac",
3398 };
3399
3400 static struct omap_hwmod am35xx_emac_hwmod = {
3401         .name           = "davinci_emac",
3402         .class          = &am35xx_emac_class,
3403         /*
3404          * According to Mark Greer, the MPU will not return from WFI
3405          * when the EMAC signals an interrupt.
3406          * http://www.spinics.net/lists/arm-kernel/msg174734.html
3407          */
3408         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3409 };
3410
3411 /* l3_core -> davinci emac interface */
3412 /*
3413  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3414  * but this will probably require some additional hwmod core support,
3415  * so is left as a future to-do item.
3416  */
3417 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3418         .master         = &am35xx_emac_hwmod,
3419         .slave          = &omap3xxx_l3_main_hwmod,
3420         .clk            = "emac_ick",
3421         .user           = OCP_USER_MPU,
3422 };
3423
3424 /* l4_core -> davinci emac  */
3425 /*
3426  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3427  * but this will probably require some additional hwmod core support,
3428  * so is left as a future to-do item.
3429  */
3430 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3431         .master         = &omap3xxx_l4_core_hwmod,
3432         .slave          = &am35xx_emac_hwmod,
3433         .clk            = "emac_ick",
3434         .user           = OCP_USER_MPU,
3435 };
3436
3437 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3438         .master         = &omap3xxx_l3_main_hwmod,
3439         .slave          = &omap3xxx_gpmc_hwmod,
3440         .clk            = "core_l3_ick",
3441         .addr           = omap3xxx_gpmc_addrs,
3442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3443 };
3444
3445 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3446 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3447         .sidle_shift    = 4,
3448         .srst_shift     = 1,
3449         .autoidle_shift = 0,
3450 };
3451
3452 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3453         .rev_offs       = 0x5c,
3454         .sysc_offs      = 0x60,
3455         .syss_offs      = 0x64,
3456         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3457                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3458         .sysc_fields    = &omap3_sham_sysc_fields,
3459 };
3460
3461 static struct omap_hwmod_class omap3xxx_sham_class = {
3462         .name   = "sham",
3463         .sysc   = &omap3_sham_sysc,
3464 };
3465
3466 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3467         { .irq = 49 + OMAP_INTC_START, },
3468         { .irq = -1 }
3469 };
3470
3471 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3472         { .name = "rx", .dma_req = 69, },
3473         { .dma_req = -1 }
3474 };
3475
3476 static struct omap_hwmod omap3xxx_sham_hwmod = {
3477         .name           = "sham",
3478         .mpu_irqs       = omap3_sham_mpu_irqs,
3479         .sdma_reqs      = omap3_sham_sdma_reqs,
3480         .main_clk       = "sha12_ick",
3481         .prcm           = {
3482                 .omap2 = {
3483                         .module_offs = CORE_MOD,
3484                         .prcm_reg_id = 1,
3485                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
3486                         .idlest_reg_id = 1,
3487                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3488                 },
3489         },
3490         .class          = &omap3xxx_sham_class,
3491 };
3492
3493 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3494         {
3495                 .pa_start       = 0x480c3000,
3496                 .pa_end         = 0x480c3000 + 0x64 - 1,
3497                 .flags          = ADDR_TYPE_RT
3498         },
3499         { }
3500 };
3501
3502 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3503         .master         = &omap3xxx_l4_core_hwmod,
3504         .slave          = &omap3xxx_sham_hwmod,
3505         .clk            = "sha12_ick",
3506         .addr           = omap3xxx_sham_addrs,
3507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3508 };
3509
3510 /* l4_core -> AES */
3511 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3512         .sidle_shift    = 6,
3513         .srst_shift     = 1,
3514         .autoidle_shift = 0,
3515 };
3516
3517 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3518         .rev_offs       = 0x44,
3519         .sysc_offs      = 0x48,
3520         .syss_offs      = 0x4c,
3521         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3522                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3523         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3524         .sysc_fields    = &omap3xxx_aes_sysc_fields,
3525 };
3526
3527 static struct omap_hwmod_class omap3xxx_aes_class = {
3528         .name   = "aes",
3529         .sysc   = &omap3_aes_sysc,
3530 };
3531
3532 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3533         { .name = "tx", .dma_req = 65, },
3534         { .name = "rx", .dma_req = 66, },
3535         { .dma_req = -1 }
3536 };
3537
3538 static struct omap_hwmod omap3xxx_aes_hwmod = {
3539         .name           = "aes",
3540         .sdma_reqs      = omap3_aes_sdma_reqs,
3541         .main_clk       = "aes2_ick",
3542         .prcm           = {
3543                 .omap2 = {
3544                         .module_offs = CORE_MOD,
3545                         .prcm_reg_id = 1,
3546                         .module_bit = OMAP3430_EN_AES2_SHIFT,
3547                         .idlest_reg_id = 1,
3548                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3549                 },
3550         },
3551         .class          = &omap3xxx_aes_class,
3552 };
3553
3554 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3555         {
3556                 .pa_start       = 0x480c5000,
3557                 .pa_end         = 0x480c5000 + 0x50 - 1,
3558                 .flags          = ADDR_TYPE_RT
3559         },
3560         { }
3561 };
3562
3563 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3564         .master         = &omap3xxx_l4_core_hwmod,
3565         .slave          = &omap3xxx_aes_hwmod,
3566         .clk            = "aes2_ick",
3567         .addr           = omap3xxx_aes_addrs,
3568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3569 };
3570
3571 /*
3572  * 'ssi' class
3573  * synchronous serial interface (multichannel and full-duplex serial if)
3574  */
3575
3576 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3577         .rev_offs       = 0x0000,
3578         .sysc_offs      = 0x0010,
3579         .syss_offs      = 0x0014,
3580         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3581                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3582         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3583         .sysc_fields    = &omap_hwmod_sysc_type1,
3584 };
3585
3586 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
3587         .name   = "ssi",
3588         .sysc   = &omap34xx_ssi_sysc,
3589 };
3590
3591 static struct omap_hwmod omap3xxx_ssi_hwmod = {
3592         .name           = "ssi",
3593         .class          = &omap3xxx_ssi_hwmod_class,
3594         .clkdm_name     = "core_l4_clkdm",
3595         .main_clk       = "ssi_ssr_fck",
3596         .prcm           = {
3597                 .omap2 = {
3598                         .prcm_reg_id            = 1,
3599                         .module_bit             = OMAP3430_EN_SSI_SHIFT,
3600                         .module_offs            = CORE_MOD,
3601                         .idlest_reg_id          = 1,
3602                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3603                 },
3604         },
3605 };
3606
3607 /* L4 CORE -> SSI */
3608 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
3609         .master         = &omap3xxx_l4_core_hwmod,
3610         .slave          = &omap3xxx_ssi_hwmod,
3611         .clk            = "ssi_ick",
3612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3613 };
3614
3615 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3616         &omap3xxx_l3_main__l4_core,
3617         &omap3xxx_l3_main__l4_per,
3618         &omap3xxx_mpu__l3_main,
3619         &omap3xxx_l3_main__l4_debugss,
3620         &omap3xxx_l4_core__l4_wkup,
3621         &omap3xxx_l4_core__mmc3,
3622         &omap3_l4_core__uart1,
3623         &omap3_l4_core__uart2,
3624         &omap3_l4_per__uart3,
3625         &omap3_l4_core__i2c1,
3626         &omap3_l4_core__i2c2,
3627         &omap3_l4_core__i2c3,
3628         &omap3xxx_l4_wkup__l4_sec,
3629         &omap3xxx_l4_wkup__timer1,
3630         &omap3xxx_l4_per__timer2,
3631         &omap3xxx_l4_per__timer3,
3632         &omap3xxx_l4_per__timer4,
3633         &omap3xxx_l4_per__timer5,
3634         &omap3xxx_l4_per__timer6,
3635         &omap3xxx_l4_per__timer7,
3636         &omap3xxx_l4_per__timer8,
3637         &omap3xxx_l4_per__timer9,
3638         &omap3xxx_l4_core__timer10,
3639         &omap3xxx_l4_core__timer11,
3640         &omap3xxx_l4_wkup__wd_timer2,
3641         &omap3xxx_l4_wkup__gpio1,
3642         &omap3xxx_l4_per__gpio2,
3643         &omap3xxx_l4_per__gpio3,
3644         &omap3xxx_l4_per__gpio4,
3645         &omap3xxx_l4_per__gpio5,
3646         &omap3xxx_l4_per__gpio6,
3647         &omap3xxx_dma_system__l3,
3648         &omap3xxx_l4_core__dma_system,
3649         &omap3xxx_l4_core__mcbsp1,
3650         &omap3xxx_l4_per__mcbsp2,
3651         &omap3xxx_l4_per__mcbsp3,
3652         &omap3xxx_l4_per__mcbsp4,
3653         &omap3xxx_l4_core__mcbsp5,
3654         &omap3xxx_l4_per__mcbsp2_sidetone,
3655         &omap3xxx_l4_per__mcbsp3_sidetone,
3656         &omap34xx_l4_core__mcspi1,
3657         &omap34xx_l4_core__mcspi2,
3658         &omap34xx_l4_core__mcspi3,
3659         &omap34xx_l4_core__mcspi4,
3660         &omap3xxx_l4_wkup__counter_32k,
3661         &omap3xxx_l3_main__gpmc,
3662         NULL,
3663 };
3664
3665 /* GP-only hwmod links */
3666 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3667         &omap3xxx_l4_sec__timer12,
3668         NULL
3669 };
3670
3671 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3672         &omap3xxx_l4_sec__timer12,
3673         NULL
3674 };
3675
3676 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3677         &omap3xxx_l4_sec__timer12,
3678         NULL
3679 };
3680
3681 /* crypto hwmod links */
3682 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3683         &omap3xxx_l4_core__sham,
3684         NULL
3685 };
3686
3687 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3688         &omap3xxx_l4_core__aes,
3689         NULL
3690 };
3691
3692 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
3693         &omap3xxx_l4_core__sham,
3694         NULL
3695 };
3696
3697 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
3698         &omap3xxx_l4_core__aes,
3699         NULL
3700 };
3701
3702 /*
3703  * Apparently the SHA/MD5 and AES accelerator IP blocks are
3704  * only present on some AM35xx chips, and no one knows which
3705  * ones.  See
3706  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3707  * if you need these IP blocks on an AM35xx, try uncommenting
3708  * the following lines.
3709  */
3710 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3711         /* &omap3xxx_l4_core__sham, */
3712         NULL
3713 };
3714
3715 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3716         /* &omap3xxx_l4_core__aes, */
3717         NULL
3718 };
3719
3720 /* 3430ES1-only hwmod links */
3721 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3722         &omap3430es1_dss__l3,
3723         &omap3430es1_l4_core__dss,
3724         NULL
3725 };
3726
3727 /* 3430ES2+-only hwmod links */
3728 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3729         &omap3xxx_dss__l3,
3730         &omap3xxx_l4_core__dss,
3731         &omap3xxx_usbhsotg__l3,
3732         &omap3xxx_l4_core__usbhsotg,
3733         &omap3xxx_usb_host_hs__l3_main_2,
3734         &omap3xxx_l4_core__usb_host_hs,
3735         &omap3xxx_l4_core__usb_tll_hs,
3736         NULL
3737 };
3738
3739 /* <= 3430ES3-only hwmod links */
3740 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3741         &omap3xxx_l4_core__pre_es3_mmc1,
3742         &omap3xxx_l4_core__pre_es3_mmc2,
3743         NULL
3744 };
3745
3746 /* 3430ES3+-only hwmod links */
3747 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3748         &omap3xxx_l4_core__es3plus_mmc1,
3749         &omap3xxx_l4_core__es3plus_mmc2,
3750         NULL
3751 };
3752
3753 /* 34xx-only hwmod links (all ES revisions) */
3754 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3755         &omap3xxx_l3__iva,
3756         &omap34xx_l4_core__sr1,
3757         &omap34xx_l4_core__sr2,
3758         &omap3xxx_l4_core__mailbox,
3759         &omap3xxx_l4_core__hdq1w,
3760         &omap3xxx_sad2d__l3,
3761         &omap3xxx_l4_core__mmu_isp,
3762         &omap3xxx_l3_main__mmu_iva,
3763         &omap3xxx_l4_core__ssi,
3764         NULL
3765 };
3766
3767 /* 36xx-only hwmod links (all ES revisions) */
3768 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3769         &omap3xxx_l3__iva,
3770         &omap36xx_l4_per__uart4,
3771         &omap3xxx_dss__l3,
3772         &omap3xxx_l4_core__dss,
3773         &omap36xx_l4_core__sr1,
3774         &omap36xx_l4_core__sr2,
3775         &omap3xxx_usbhsotg__l3,
3776         &omap3xxx_l4_core__usbhsotg,
3777         &omap3xxx_l4_core__mailbox,
3778         &omap3xxx_usb_host_hs__l3_main_2,
3779         &omap3xxx_l4_core__usb_host_hs,
3780         &omap3xxx_l4_core__usb_tll_hs,
3781         &omap3xxx_l4_core__es3plus_mmc1,
3782         &omap3xxx_l4_core__es3plus_mmc2,
3783         &omap3xxx_l4_core__hdq1w,
3784         &omap3xxx_sad2d__l3,
3785         &omap3xxx_l4_core__mmu_isp,
3786         &omap3xxx_l3_main__mmu_iva,
3787         &omap3xxx_l4_core__ssi,
3788         NULL
3789 };
3790
3791 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3792         &omap3xxx_dss__l3,
3793         &omap3xxx_l4_core__dss,
3794         &am35xx_usbhsotg__l3,
3795         &am35xx_l4_core__usbhsotg,
3796         &am35xx_l4_core__uart4,
3797         &omap3xxx_usb_host_hs__l3_main_2,
3798         &omap3xxx_l4_core__usb_host_hs,
3799         &omap3xxx_l4_core__usb_tll_hs,
3800         &omap3xxx_l4_core__es3plus_mmc1,
3801         &omap3xxx_l4_core__es3plus_mmc2,
3802         &omap3xxx_l4_core__hdq1w,
3803         &am35xx_mdio__l3,
3804         &am35xx_l4_core__mdio,
3805         &am35xx_emac__l3,
3806         &am35xx_l4_core__emac,
3807         NULL
3808 };
3809
3810 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3811         &omap3xxx_l4_core__dss_dispc,
3812         &omap3xxx_l4_core__dss_dsi1,
3813         &omap3xxx_l4_core__dss_rfbi,
3814         &omap3xxx_l4_core__dss_venc,
3815         NULL
3816 };
3817
3818 /**
3819  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3820  * @bus: struct device_node * for the top-level OMAP DT data
3821  * @dev_name: device name used in the DT file
3822  *
3823  * Determine whether a "secure" IP block @dev_name is usable by Linux.
3824  * There doesn't appear to be a 100% reliable way to determine this,
3825  * so we rely on heuristics.  If @bus is null, meaning there's no DT
3826  * data, then we only assume the IP block is accessible if the OMAP is
3827  * fused as a 'general-purpose' SoC.  If however DT data is present,
3828  * test to see if the IP block is described in the DT data and set to
3829  * 'status = "okay"'.  If so then we assume the ODM has configured the
3830  * OMAP firewalls to allow access to the IP block.
3831  *
3832  * Return: 0 if device named @dev_name is not likely to be accessible,
3833  * or 1 if it is likely to be accessible.
3834  */
3835 static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3836                                                        const char *dev_name)
3837 {
3838         if (!bus)
3839                 return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
3840
3841         if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
3842                 return 1;
3843
3844         return 0;
3845 }
3846
3847 int __init omap3xxx_hwmod_init(void)
3848 {
3849         int r;
3850         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3851         struct omap_hwmod_ocp_if **h_aes = NULL;
3852         struct device_node *bus = NULL;
3853         unsigned int rev;
3854
3855         omap_hwmod_init();
3856
3857         /* Register hwmod links common to all OMAP3 */
3858         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3859         if (r < 0)
3860                 return r;
3861
3862         rev = omap_rev();
3863
3864         /*
3865          * Register hwmod links common to individual OMAP3 families, all
3866          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3867          * All possible revisions should be included in this conditional.
3868          */
3869         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3870             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3871             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3872                 h = omap34xx_hwmod_ocp_ifs;
3873                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3874                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3875                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3876         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3877                 h = am35xx_hwmod_ocp_ifs;
3878                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3879                 h_sham = am35xx_sham_hwmod_ocp_ifs;
3880                 h_aes = am35xx_aes_hwmod_ocp_ifs;
3881         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3882                    rev == OMAP3630_REV_ES1_2) {
3883                 h = omap36xx_hwmod_ocp_ifs;
3884                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3885                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3886                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3887         } else {
3888                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3889                 return -EINVAL;
3890         }
3891
3892         r = omap_hwmod_register_links(h);
3893         if (r < 0)
3894                 return r;
3895
3896         /* Register GP-only hwmod links. */
3897         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3898                 r = omap_hwmod_register_links(h_gp);
3899                 if (r < 0)
3900                         return r;
3901         }
3902
3903         /*
3904          * Register crypto hwmod links only if they are not disabled in DT.
3905          * If DT information is missing, enable them only for GP devices.
3906          */
3907
3908         if (of_have_populated_dt())
3909                 bus = of_find_node_by_name(NULL, "ocp");
3910
3911         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3912                 r = omap_hwmod_register_links(h_sham);
3913                 if (r < 0)
3914                         return r;
3915         }
3916
3917         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3918                 r = omap_hwmod_register_links(h_aes);
3919                 if (r < 0)
3920                         return r;
3921         }
3922
3923         /*
3924          * Register hwmod links specific to certain ES levels of a
3925          * particular family of silicon (e.g., 34xx ES1.0)
3926          */
3927         h = NULL;
3928         if (rev == OMAP3430_REV_ES1_0) {
3929                 h = omap3430es1_hwmod_ocp_ifs;
3930         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3931                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3932                    rev == OMAP3430_REV_ES3_1_2) {
3933                 h = omap3430es2plus_hwmod_ocp_ifs;
3934         }
3935
3936         if (h) {
3937                 r = omap_hwmod_register_links(h);
3938                 if (r < 0)
3939                         return r;
3940         }
3941
3942         h = NULL;
3943         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3944             rev == OMAP3430_REV_ES2_1) {
3945                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3946         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3947                    rev == OMAP3430_REV_ES3_1_2) {
3948                 h = omap3430_es3plus_hwmod_ocp_ifs;
3949         }
3950
3951         if (h)
3952                 r = omap_hwmod_register_links(h);
3953         if (r < 0)
3954                 return r;
3955
3956         /*
3957          * DSS code presumes that dss_core hwmod is handled first,
3958          * _before_ any other DSS related hwmods so register common
3959          * DSS hwmod links last to ensure that dss_core is already
3960          * registered.  Otherwise some change things may happen, for
3961          * ex. if dispc is handled before dss_core and DSS is enabled
3962          * in bootloader DISPC will be reset with outputs enabled
3963          * which sometimes leads to unrecoverable L3 error.  XXX The
3964          * long-term fix to this is to ensure hwmods are set up in
3965          * dependency order in the hwmod core code.
3966          */
3967         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3968
3969         return r;
3970 }