3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/types.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include "omap_hwmod.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
36 * instance(s): l3_main, l3_s, l3_instr
38 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
42 struct omap_hwmod am33xx_l3_main_hwmod = {
44 .class = &am33xx_l3_hwmod_class,
45 .clkdm_name = "l3_clkdm",
46 .flags = HWMOD_INIT_NO_IDLE,
47 .main_clk = "l3_gclk",
50 .modulemode = MODULEMODE_SWCTRL,
56 struct omap_hwmod am33xx_l3_s_hwmod = {
58 .class = &am33xx_l3_hwmod_class,
59 .clkdm_name = "l3s_clkdm",
63 struct omap_hwmod am33xx_l3_instr_hwmod = {
65 .class = &am33xx_l3_hwmod_class,
66 .clkdm_name = "l3_clkdm",
67 .flags = HWMOD_INIT_NO_IDLE,
68 .main_clk = "l3_gclk",
71 .modulemode = MODULEMODE_SWCTRL,
78 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
80 struct omap_hwmod_class am33xx_l4_hwmod_class = {
85 struct omap_hwmod am33xx_l4_ls_hwmod = {
87 .class = &am33xx_l4_hwmod_class,
88 .clkdm_name = "l4ls_clkdm",
89 .flags = HWMOD_INIT_NO_IDLE,
90 .main_clk = "l4ls_gclk",
93 .modulemode = MODULEMODE_SWCTRL,
99 struct omap_hwmod am33xx_l4_wkup_hwmod = {
101 .class = &am33xx_l4_hwmod_class,
102 .clkdm_name = "l4_wkup_clkdm",
103 .flags = HWMOD_INIT_NO_IDLE,
106 .modulemode = MODULEMODE_SWCTRL,
114 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
118 struct omap_hwmod am33xx_mpu_hwmod = {
120 .class = &am33xx_mpu_hwmod_class,
121 .clkdm_name = "mpu_clkdm",
122 .flags = HWMOD_INIT_NO_IDLE,
123 .main_clk = "dpll_mpu_m2_ck",
126 .modulemode = MODULEMODE_SWCTRL,
133 * Wakeup controller sub-system under wakeup domain
135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
141 * Programmable Real-Time Unit and Industrial Communication Subsystem
143 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
147 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
148 { .name = "pruss", .rst_shift = 1 },
152 /* Pseudo hwmod for reset control purpose only */
153 struct omap_hwmod am33xx_pruss_hwmod = {
155 .class = &am33xx_pruss_hwmod_class,
156 .clkdm_name = "pruss_ocp_clkdm",
157 .main_clk = "pruss_ocp_gclk",
160 .modulemode = MODULEMODE_SWCTRL,
163 .rst_lines = am33xx_pruss_resets,
164 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
168 /* Pseudo hwmod for reset control purpose only */
169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
174 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
177 struct omap_hwmod am33xx_gfx_hwmod = {
179 .class = &am33xx_gfx_hwmod_class,
180 .clkdm_name = "gfx_l3_clkdm",
181 .main_clk = "gfx_fck_div_ck",
184 .modulemode = MODULEMODE_SWCTRL,
187 .rst_lines = am33xx_gfx_resets,
188 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
193 * power and reset manager (whole prcm infrastructure)
195 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
200 struct omap_hwmod am33xx_prcm_hwmod = {
202 .class = &am33xx_prcm_hwmod_class,
203 .clkdm_name = "l4_wkup_clkdm",
210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
214 struct omap_hwmod_class am33xx_emif_hwmod_class = {
216 .sysc = &am33xx_emif_sysc,
222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
226 .sysc_flags = SYSS_HAS_RESET_STATUS,
229 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
231 .sysc = &am33xx_aes0_sysc,
234 struct omap_hwmod am33xx_aes0_hwmod = {
236 .class = &am33xx_aes0_hwmod_class,
237 .clkdm_name = "l3_clkdm",
238 .main_clk = "aes0_fck",
241 .modulemode = MODULEMODE_SWCTRL,
246 /* sha0 HIB2 (the 'P' (public) device) */
247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
251 .sysc_flags = SYSS_HAS_RESET_STATUS,
254 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
256 .sysc = &am33xx_sha0_sysc,
259 struct omap_hwmod am33xx_sha0_hwmod = {
261 .class = &am33xx_sha0_hwmod_class,
262 .clkdm_name = "l3_clkdm",
263 .main_clk = "l3_gclk",
266 .modulemode = MODULEMODE_SWCTRL,
272 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
275 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
276 .idlemodes = SIDLE_FORCE | SIDLE_NO,
277 .sysc_fields = &omap_hwmod_sysc_type1,
280 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
282 .sysc = &am33xx_rng_sysc,
285 struct omap_hwmod am33xx_rng_hwmod = {
287 .class = &am33xx_rng_hwmod_class,
288 .clkdm_name = "l4ls_clkdm",
289 .flags = HWMOD_SWSUP_SIDLE,
290 .main_clk = "rng_fck",
293 .modulemode = MODULEMODE_SWCTRL,
299 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
303 struct omap_hwmod am33xx_ocmcram_hwmod = {
305 .class = &am33xx_ocmcram_hwmod_class,
306 .clkdm_name = "l3_clkdm",
307 .flags = HWMOD_INIT_NO_IDLE,
308 .main_clk = "l3_gclk",
311 .modulemode = MODULEMODE_SWCTRL,
316 /* 'smartreflex' class */
317 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
318 .name = "smartreflex",
322 struct omap_hwmod am33xx_smartreflex0_hwmod = {
323 .name = "smartreflex0",
324 .class = &am33xx_smartreflex_hwmod_class,
325 .clkdm_name = "l4_wkup_clkdm",
326 .main_clk = "smartreflex0_fck",
329 .modulemode = MODULEMODE_SWCTRL,
335 struct omap_hwmod am33xx_smartreflex1_hwmod = {
336 .name = "smartreflex1",
337 .class = &am33xx_smartreflex_hwmod_class,
338 .clkdm_name = "l4_wkup_clkdm",
339 .main_clk = "smartreflex1_fck",
342 .modulemode = MODULEMODE_SWCTRL,
348 * 'control' module class
350 struct omap_hwmod_class am33xx_control_hwmod_class = {
356 * cpsw/cpgmac sub system
358 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
362 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
363 SYSS_HAS_RESET_STATUS),
364 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
366 .sysc_fields = &omap_hwmod_sysc_type3,
369 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
371 .sysc = &am33xx_cpgmac_sysc,
374 struct omap_hwmod am33xx_cpgmac0_hwmod = {
376 .class = &am33xx_cpgmac0_hwmod_class,
377 .clkdm_name = "cpsw_125mhz_clkdm",
378 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
379 .main_clk = "cpsw_125mhz_gclk",
383 .modulemode = MODULEMODE_SWCTRL,
391 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
392 .name = "davinci_mdio",
395 struct omap_hwmod am33xx_mdio_hwmod = {
396 .name = "davinci_mdio",
397 .class = &am33xx_mdio_hwmod_class,
398 .clkdm_name = "cpsw_125mhz_clkdm",
399 .main_clk = "cpsw_125mhz_gclk",
405 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
410 struct omap_hwmod am33xx_dcan0_hwmod = {
412 .class = &am33xx_dcan_hwmod_class,
413 .clkdm_name = "l4ls_clkdm",
414 .main_clk = "dcan0_fck",
417 .modulemode = MODULEMODE_SWCTRL,
423 struct omap_hwmod am33xx_dcan1_hwmod = {
425 .class = &am33xx_dcan_hwmod_class,
426 .clkdm_name = "l4ls_clkdm",
427 .main_clk = "dcan1_fck",
430 .modulemode = MODULEMODE_SWCTRL,
436 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
440 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
441 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
447 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
449 .sysc = &am33xx_elm_sysc,
452 struct omap_hwmod am33xx_elm_hwmod = {
454 .class = &am33xx_elm_hwmod_class,
455 .clkdm_name = "l4ls_clkdm",
456 .main_clk = "l4ls_gclk",
459 .modulemode = MODULEMODE_SWCTRL,
465 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
468 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
469 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
470 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
471 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
472 .sysc_fields = &omap_hwmod_sysc_type2,
475 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
477 .sysc = &am33xx_epwmss_sysc,
481 struct omap_hwmod am33xx_epwmss0_hwmod = {
483 .class = &am33xx_epwmss_hwmod_class,
484 .clkdm_name = "l4ls_clkdm",
485 .main_clk = "l4ls_gclk",
488 .modulemode = MODULEMODE_SWCTRL,
494 struct omap_hwmod am33xx_epwmss1_hwmod = {
496 .class = &am33xx_epwmss_hwmod_class,
497 .clkdm_name = "l4ls_clkdm",
498 .main_clk = "l4ls_gclk",
501 .modulemode = MODULEMODE_SWCTRL,
507 struct omap_hwmod am33xx_epwmss2_hwmod = {
509 .class = &am33xx_epwmss_hwmod_class,
510 .clkdm_name = "l4ls_clkdm",
511 .main_clk = "l4ls_gclk",
514 .modulemode = MODULEMODE_SWCTRL,
520 * 'gpio' class: for gpio 0,1,2,3
522 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
526 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
527 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
528 SYSS_HAS_RESET_STATUS),
529 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
531 .sysc_fields = &omap_hwmod_sysc_type1,
534 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
536 .sysc = &am33xx_gpio_sysc,
541 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
542 { .role = "dbclk", .clk = "gpio1_dbclk" },
545 struct omap_hwmod am33xx_gpio1_hwmod = {
547 .class = &am33xx_gpio_hwmod_class,
548 .clkdm_name = "l4ls_clkdm",
549 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
550 .main_clk = "l4ls_gclk",
553 .modulemode = MODULEMODE_SWCTRL,
556 .opt_clks = gpio1_opt_clks,
557 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
561 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
562 { .role = "dbclk", .clk = "gpio2_dbclk" },
565 struct omap_hwmod am33xx_gpio2_hwmod = {
567 .class = &am33xx_gpio_hwmod_class,
568 .clkdm_name = "l4ls_clkdm",
569 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
570 .main_clk = "l4ls_gclk",
573 .modulemode = MODULEMODE_SWCTRL,
576 .opt_clks = gpio2_opt_clks,
577 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
581 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
582 { .role = "dbclk", .clk = "gpio3_dbclk" },
585 struct omap_hwmod am33xx_gpio3_hwmod = {
587 .class = &am33xx_gpio_hwmod_class,
588 .clkdm_name = "l4ls_clkdm",
589 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
590 .main_clk = "l4ls_gclk",
593 .modulemode = MODULEMODE_SWCTRL,
596 .opt_clks = gpio3_opt_clks,
597 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
601 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
605 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
606 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
607 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
608 .sysc_fields = &omap_hwmod_sysc_type1,
611 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
616 struct omap_hwmod am33xx_gpmc_hwmod = {
618 .class = &am33xx_gpmc_hwmod_class,
619 .clkdm_name = "l3s_clkdm",
620 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
621 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
622 .main_clk = "l3s_gclk",
625 .modulemode = MODULEMODE_SWCTRL,
631 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
634 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
635 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
636 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
637 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
639 .sysc_fields = &omap_hwmod_sysc_type1,
642 static struct omap_hwmod_class i2c_class = {
644 .sysc = &am33xx_i2c_sysc,
645 .rev = OMAP_I2C_IP_VERSION_2,
646 .reset = &omap_i2c_reset,
650 struct omap_hwmod am33xx_i2c1_hwmod = {
653 .clkdm_name = "l4_wkup_clkdm",
654 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
655 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
658 .modulemode = MODULEMODE_SWCTRL,
664 struct omap_hwmod am33xx_i2c2_hwmod = {
667 .clkdm_name = "l4ls_clkdm",
668 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
669 .main_clk = "dpll_per_m2_div4_ck",
672 .modulemode = MODULEMODE_SWCTRL,
678 struct omap_hwmod am33xx_i2c3_hwmod = {
681 .clkdm_name = "l4ls_clkdm",
682 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
683 .main_clk = "dpll_per_m2_div4_ck",
686 .modulemode = MODULEMODE_SWCTRL,
693 * mailbox module allowing communication between the on-chip processors using a
694 * queued mailbox-interrupt mechanism.
696 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
699 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
701 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
702 .sysc_fields = &omap_hwmod_sysc_type2,
705 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
707 .sysc = &am33xx_mailbox_sysc,
710 struct omap_hwmod am33xx_mailbox_hwmod = {
712 .class = &am33xx_mailbox_hwmod_class,
713 .clkdm_name = "l4ls_clkdm",
714 .main_clk = "l4ls_gclk",
717 .modulemode = MODULEMODE_SWCTRL,
725 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
728 .sysc_flags = SYSC_HAS_SIDLEMODE,
729 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
730 .sysc_fields = &omap_hwmod_sysc_type3,
733 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
735 .sysc = &am33xx_mcasp_sysc,
739 struct omap_hwmod am33xx_mcasp0_hwmod = {
741 .class = &am33xx_mcasp_hwmod_class,
742 .clkdm_name = "l3s_clkdm",
743 .main_clk = "mcasp0_fck",
746 .modulemode = MODULEMODE_SWCTRL,
752 struct omap_hwmod am33xx_mcasp1_hwmod = {
754 .class = &am33xx_mcasp_hwmod_class,
755 .clkdm_name = "l3s_clkdm",
756 .main_clk = "mcasp1_fck",
759 .modulemode = MODULEMODE_SWCTRL,
765 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
769 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
770 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
771 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
772 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
773 .sysc_fields = &omap_hwmod_sysc_type1,
776 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
778 .sysc = &am33xx_mmc_sysc,
782 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
783 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
786 struct omap_hwmod am33xx_mmc0_hwmod = {
788 .class = &am33xx_mmc_hwmod_class,
789 .clkdm_name = "l4ls_clkdm",
790 .main_clk = "mmc_clk",
793 .modulemode = MODULEMODE_SWCTRL,
796 .dev_attr = &am33xx_mmc0_dev_attr,
800 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
801 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
804 struct omap_hwmod am33xx_mmc1_hwmod = {
806 .class = &am33xx_mmc_hwmod_class,
807 .clkdm_name = "l4ls_clkdm",
808 .main_clk = "mmc_clk",
811 .modulemode = MODULEMODE_SWCTRL,
814 .dev_attr = &am33xx_mmc1_dev_attr,
818 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
819 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
821 struct omap_hwmod am33xx_mmc2_hwmod = {
823 .class = &am33xx_mmc_hwmod_class,
824 .clkdm_name = "l3s_clkdm",
825 .main_clk = "mmc_clk",
828 .modulemode = MODULEMODE_SWCTRL,
831 .dev_attr = &am33xx_mmc2_dev_attr,
838 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
841 .sysc_flags = SYSC_HAS_SIDLEMODE,
842 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
843 SIDLE_SMART | SIDLE_SMART_WKUP),
844 .sysc_fields = &omap_hwmod_sysc_type3,
847 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
849 .sysc = &am33xx_rtc_sysc,
850 .unlock = &omap_hwmod_rtc_unlock,
851 .lock = &omap_hwmod_rtc_lock,
854 struct omap_hwmod am33xx_rtc_hwmod = {
856 .class = &am33xx_rtc_hwmod_class,
857 .clkdm_name = "l4_rtc_clkdm",
858 .main_clk = "clk_32768_ck",
861 .modulemode = MODULEMODE_SWCTRL,
867 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
871 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
872 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
873 SYSS_HAS_RESET_STATUS),
874 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
875 .sysc_fields = &omap_hwmod_sysc_type1,
878 struct omap_hwmod_class am33xx_spi_hwmod_class = {
880 .sysc = &am33xx_mcspi_sysc,
884 struct omap_hwmod am33xx_spi0_hwmod = {
886 .class = &am33xx_spi_hwmod_class,
887 .clkdm_name = "l4ls_clkdm",
888 .main_clk = "dpll_per_m2_div4_ck",
891 .modulemode = MODULEMODE_SWCTRL,
897 struct omap_hwmod am33xx_spi1_hwmod = {
899 .class = &am33xx_spi_hwmod_class,
900 .clkdm_name = "l4ls_clkdm",
901 .main_clk = "dpll_per_m2_div4_ck",
904 .modulemode = MODULEMODE_SWCTRL,
911 * spinlock provides hardware assistance for synchronizing the
912 * processes running on multiple processors
915 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
919 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
920 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
921 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
922 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
923 .sysc_fields = &omap_hwmod_sysc_type1,
926 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
928 .sysc = &am33xx_spinlock_sysc,
931 struct omap_hwmod am33xx_spinlock_hwmod = {
933 .class = &am33xx_spinlock_hwmod_class,
934 .clkdm_name = "l4ls_clkdm",
935 .main_clk = "l4ls_gclk",
938 .modulemode = MODULEMODE_SWCTRL,
943 /* 'timer 2-7' class */
944 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
948 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
949 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
951 .sysc_fields = &omap_hwmod_sysc_type2,
954 struct omap_hwmod_class am33xx_timer_hwmod_class = {
956 .sysc = &am33xx_timer_sysc,
960 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
964 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
965 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
966 SYSS_HAS_RESET_STATUS),
967 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
968 .sysc_fields = &omap_hwmod_sysc_type1,
971 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
973 .sysc = &am33xx_timer1ms_sysc,
976 struct omap_hwmod am33xx_timer1_hwmod = {
978 .class = &am33xx_timer1ms_hwmod_class,
979 .clkdm_name = "l4_wkup_clkdm",
980 .main_clk = "timer1_fck",
983 .modulemode = MODULEMODE_SWCTRL,
988 struct omap_hwmod am33xx_timer2_hwmod = {
990 .class = &am33xx_timer_hwmod_class,
991 .clkdm_name = "l4ls_clkdm",
992 .main_clk = "timer2_fck",
995 .modulemode = MODULEMODE_SWCTRL,
1000 struct omap_hwmod am33xx_timer3_hwmod = {
1002 .class = &am33xx_timer_hwmod_class,
1003 .clkdm_name = "l4ls_clkdm",
1004 .main_clk = "timer3_fck",
1007 .modulemode = MODULEMODE_SWCTRL,
1012 struct omap_hwmod am33xx_timer4_hwmod = {
1014 .class = &am33xx_timer_hwmod_class,
1015 .clkdm_name = "l4ls_clkdm",
1016 .main_clk = "timer4_fck",
1019 .modulemode = MODULEMODE_SWCTRL,
1024 struct omap_hwmod am33xx_timer5_hwmod = {
1026 .class = &am33xx_timer_hwmod_class,
1027 .clkdm_name = "l4ls_clkdm",
1028 .main_clk = "timer5_fck",
1031 .modulemode = MODULEMODE_SWCTRL,
1036 struct omap_hwmod am33xx_timer6_hwmod = {
1038 .class = &am33xx_timer_hwmod_class,
1039 .clkdm_name = "l4ls_clkdm",
1040 .main_clk = "timer6_fck",
1043 .modulemode = MODULEMODE_SWCTRL,
1048 struct omap_hwmod am33xx_timer7_hwmod = {
1050 .class = &am33xx_timer_hwmod_class,
1051 .clkdm_name = "l4ls_clkdm",
1052 .main_clk = "timer7_fck",
1055 .modulemode = MODULEMODE_SWCTRL,
1061 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1065 struct omap_hwmod am33xx_tpcc_hwmod = {
1067 .class = &am33xx_tpcc_hwmod_class,
1068 .clkdm_name = "l3_clkdm",
1069 .main_clk = "l3_gclk",
1072 .modulemode = MODULEMODE_SWCTRL,
1077 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1080 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1081 SYSC_HAS_MIDLEMODE),
1082 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1083 .sysc_fields = &omap_hwmod_sysc_type2,
1087 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1089 .sysc = &am33xx_tptc_sysc,
1093 struct omap_hwmod am33xx_tptc0_hwmod = {
1095 .class = &am33xx_tptc_hwmod_class,
1096 .clkdm_name = "l3_clkdm",
1097 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1098 .main_clk = "l3_gclk",
1101 .modulemode = MODULEMODE_SWCTRL,
1107 struct omap_hwmod am33xx_tptc1_hwmod = {
1109 .class = &am33xx_tptc_hwmod_class,
1110 .clkdm_name = "l3_clkdm",
1111 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1112 .main_clk = "l3_gclk",
1115 .modulemode = MODULEMODE_SWCTRL,
1121 struct omap_hwmod am33xx_tptc2_hwmod = {
1123 .class = &am33xx_tptc_hwmod_class,
1124 .clkdm_name = "l3_clkdm",
1125 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1126 .main_clk = "l3_gclk",
1129 .modulemode = MODULEMODE_SWCTRL,
1135 static struct omap_hwmod_class_sysconfig uart_sysc = {
1139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1140 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1143 .sysc_fields = &omap_hwmod_sysc_type1,
1146 static struct omap_hwmod_class uart_class = {
1151 struct omap_hwmod am33xx_uart1_hwmod = {
1153 .class = &uart_class,
1154 .clkdm_name = "l4_wkup_clkdm",
1155 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1156 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1159 .modulemode = MODULEMODE_SWCTRL,
1164 struct omap_hwmod am33xx_uart2_hwmod = {
1166 .class = &uart_class,
1167 .clkdm_name = "l4ls_clkdm",
1168 .flags = HWMOD_SWSUP_SIDLE_ACT,
1169 .main_clk = "dpll_per_m2_div4_ck",
1172 .modulemode = MODULEMODE_SWCTRL,
1178 struct omap_hwmod am33xx_uart3_hwmod = {
1180 .class = &uart_class,
1181 .clkdm_name = "l4ls_clkdm",
1182 .flags = HWMOD_SWSUP_SIDLE_ACT,
1183 .main_clk = "dpll_per_m2_div4_ck",
1186 .modulemode = MODULEMODE_SWCTRL,
1191 struct omap_hwmod am33xx_uart4_hwmod = {
1193 .class = &uart_class,
1194 .clkdm_name = "l4ls_clkdm",
1195 .flags = HWMOD_SWSUP_SIDLE_ACT,
1196 .main_clk = "dpll_per_m2_div4_ck",
1199 .modulemode = MODULEMODE_SWCTRL,
1204 struct omap_hwmod am33xx_uart5_hwmod = {
1206 .class = &uart_class,
1207 .clkdm_name = "l4ls_clkdm",
1208 .flags = HWMOD_SWSUP_SIDLE_ACT,
1209 .main_clk = "dpll_per_m2_div4_ck",
1212 .modulemode = MODULEMODE_SWCTRL,
1217 struct omap_hwmod am33xx_uart6_hwmod = {
1219 .class = &uart_class,
1220 .clkdm_name = "l4ls_clkdm",
1221 .flags = HWMOD_SWSUP_SIDLE_ACT,
1222 .main_clk = "dpll_per_m2_div4_ck",
1225 .modulemode = MODULEMODE_SWCTRL,
1230 /* 'wd_timer' class */
1231 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1235 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1236 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1237 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1239 .sysc_fields = &omap_hwmod_sysc_type1,
1242 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1245 .pre_shutdown = &omap2_wd_timer_disable,
1249 * XXX: device.c file uses hardcoded name for watchdog timer
1250 * driver "wd_timer2, so we are also using same name as of now...
1252 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1253 .name = "wd_timer2",
1254 .class = &am33xx_wd_timer_hwmod_class,
1255 .clkdm_name = "l4_wkup_clkdm",
1256 .flags = HWMOD_SWSUP_SIDLE,
1257 .main_clk = "wdt1_fck",
1260 .modulemode = MODULEMODE_SWCTRL,
1265 static void omap_hwmod_am33xx_clkctrl(void)
1267 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1268 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1269 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1270 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1271 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1272 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1273 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1274 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1275 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1276 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1277 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1278 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1279 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1280 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1281 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1282 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1283 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1284 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1285 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1286 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1287 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1288 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1289 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1290 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1291 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1292 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1293 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1294 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1295 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1296 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1297 CLKCTRL(am33xx_smartreflex0_hwmod,
1298 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1299 CLKCTRL(am33xx_smartreflex1_hwmod,
1300 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1301 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1302 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1303 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1304 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1305 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1306 PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1307 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1308 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1309 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1310 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1311 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1312 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1313 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1314 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1315 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1316 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1317 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1318 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1319 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1320 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1321 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1322 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1323 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1324 CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1327 static void omap_hwmod_am33xx_rst(void)
1329 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1330 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1331 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1334 void omap_hwmod_am33xx_reg(void)
1336 omap_hwmod_am33xx_clkctrl();
1337 omap_hwmod_am33xx_rst();
1340 static void omap_hwmod_am43xx_clkctrl(void)
1342 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1343 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1344 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1346 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1347 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1358 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1359 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1360 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1361 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1366 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1368 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_smartreflex0_hwmod,
1373 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1374 CLKCTRL(am33xx_smartreflex1_hwmod,
1375 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1376 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1378 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1380 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1383 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1384 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1385 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1386 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1387 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1388 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1389 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1390 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1391 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1392 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1393 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1394 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1395 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1396 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1397 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1398 CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1401 static void omap_hwmod_am43xx_rst(void)
1403 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1404 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1405 RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1406 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1409 void omap_hwmod_am43xx_reg(void)
1411 omap_hwmod_am43xx_clkctrl();
1412 omap_hwmod_am43xx_rst();