arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include <linux/platform_data/hsmmc-omap.h>
  20 #include "omap_hwmod.h"
  21 #include "i2c.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27 #include "common.h"
  28
  29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  33
  34 /*
  35  * 'l3' class
  36  * instance(s): l3_main, l3_s, l3_instr
  37  */
  38 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  39         .name           = "l3",
  40 };
  41
  42 struct omap_hwmod am33xx_l3_main_hwmod = {
  43         .name           = "l3_main",
  44         .class          = &am33xx_l3_hwmod_class,
  45         .clkdm_name     = "l3_clkdm",
  46         .flags          = HWMOD_INIT_NO_IDLE,
  47         .main_clk       = "l3_gclk",
  48         .prcm           = {
  49                 .omap4  = {
  50                         .modulemode     = MODULEMODE_SWCTRL,
  51                 },
  52         },
  53 };
  54
  55 /* l3_s */
  56 struct omap_hwmod am33xx_l3_s_hwmod = {
  57         .name           = "l3_s",
  58         .class          = &am33xx_l3_hwmod_class,
  59         .clkdm_name     = "l3s_clkdm",
  60 };
  61
  62 /* l3_instr */
  63 struct omap_hwmod am33xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &am33xx_l3_hwmod_class,
  66         .clkdm_name     = "l3_clkdm",
  67         .flags          = HWMOD_INIT_NO_IDLE,
  68         .main_clk       = "l3_gclk",
  69         .prcm           = {
  70                 .omap4  = {
  71                         .modulemode     = MODULEMODE_SWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /*
  77  * 'l4' class
  78  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  79  */
  80 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  81         .name           = "l4",
  82 };
  83
  84 /* l4_ls */
  85 struct omap_hwmod am33xx_l4_ls_hwmod = {
  86         .name           = "l4_ls",
  87         .class          = &am33xx_l4_hwmod_class,
  88         .clkdm_name     = "l4ls_clkdm",
  89         .flags          = HWMOD_INIT_NO_IDLE,
  90         .main_clk       = "l4ls_gclk",
  91         .prcm           = {
  92                 .omap4  = {
  93                         .modulemode     = MODULEMODE_SWCTRL,
  94                 },
  95         },
  96 };
  97
  98 /* l4_wkup */
  99 struct omap_hwmod am33xx_l4_wkup_hwmod = {
 100         .name           = "l4_wkup",
 101         .class          = &am33xx_l4_hwmod_class,
 102         .clkdm_name     = "l4_wkup_clkdm",
 103         .flags          = HWMOD_INIT_NO_IDLE,
 104         .prcm           = {
 105                 .omap4  = {
 106                         .modulemode     = MODULEMODE_SWCTRL,
 107                 },
 108         },
 109 };
 110
 111 /*
 112  * 'mpu' class
 113  */
 114 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 115         .name   = "mpu",
 116 };
 117
 118 struct omap_hwmod am33xx_mpu_hwmod = {
 119         .name           = "mpu",
 120         .class          = &am33xx_mpu_hwmod_class,
 121         .clkdm_name     = "mpu_clkdm",
 122         .flags          = HWMOD_INIT_NO_IDLE,
 123         .main_clk       = "dpll_mpu_m2_ck",
 124         .prcm           = {
 125                 .omap4  = {
 126                         .modulemode     = MODULEMODE_SWCTRL,
 127                 },
 128         },
 129 };
 130
 131 /*
 132  * 'wakeup m3' class
 133  * Wakeup controller sub-system under wakeup domain
 134  */
 135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 136         .name           = "wkup_m3",
 137 };
 138
 139 /*
 140  * 'pru-icss' class
 141  * Programmable Real-Time Unit and Industrial Communication Subsystem
 142  */
 143 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 144         .name   = "pruss",
 145 };
 146
 147 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 148         { .name = "pruss", .rst_shift = 1 },
 149 };
 150
 151 /* pru-icss */
 152 /* Pseudo hwmod for reset control purpose only */
 153 struct omap_hwmod am33xx_pruss_hwmod = {
 154         .name           = "pruss",
 155         .class          = &am33xx_pruss_hwmod_class,
 156         .clkdm_name     = "pruss_ocp_clkdm",
 157         .main_clk       = "pruss_ocp_gclk",
 158         .prcm           = {
 159                 .omap4  = {
 160                         .modulemode     = MODULEMODE_SWCTRL,
 161                 },
 162         },
 163         .rst_lines      = am33xx_pruss_resets,
 164         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 165 };
 166
 167 /* gfx */
 168 /* Pseudo hwmod for reset control purpose only */
 169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 170         .name   = "gfx",
 171 };
 172
 173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 174         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 175 };
 176
 177 struct omap_hwmod am33xx_gfx_hwmod = {
 178         .name           = "gfx",
 179         .class          = &am33xx_gfx_hwmod_class,
 180         .clkdm_name     = "gfx_l3_clkdm",
 181         .main_clk       = "gfx_fck_div_ck",
 182         .prcm           = {
 183                 .omap4  = {
 184                         .modulemode     = MODULEMODE_SWCTRL,
 185                 },
 186         },
 187         .rst_lines      = am33xx_gfx_resets,
 188         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 189 };
 190
 191 /*
 192  * 'prcm' class
 193  * power and reset manager (whole prcm infrastructure)
 194  */
 195 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 196         .name   = "prcm",
 197 };
 198
 199 /* prcm */
 200 struct omap_hwmod am33xx_prcm_hwmod = {
 201         .name           = "prcm",
 202         .class          = &am33xx_prcm_hwmod_class,
 203         .clkdm_name     = "l4_wkup_clkdm",
 204 };
 205
 206 /*
 207  * 'emif' class
 208  * instance(s): emif
 209  */
 210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 211         .rev_offs       = 0x0000,
 212 };
 213
 214 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 215         .name           = "emif",
 216         .sysc           = &am33xx_emif_sysc,
 217 };
 218
 219 /*
 220  * 'aes0' class
 221  */
 222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 223         .rev_offs       = 0x80,
 224         .sysc_offs      = 0x84,
 225         .syss_offs      = 0x88,
 226         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 227 };
 228
 229 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 230         .name           = "aes0",
 231         .sysc           = &am33xx_aes0_sysc,
 232 };
 233
 234 struct omap_hwmod am33xx_aes0_hwmod = {
 235         .name           = "aes",
 236         .class          = &am33xx_aes0_hwmod_class,
 237         .clkdm_name     = "l3_clkdm",
 238         .main_clk       = "aes0_fck",
 239         .prcm           = {
 240                 .omap4  = {
 241                         .modulemode     = MODULEMODE_SWCTRL,
 242                 },
 243         },
 244 };
 245
 246 /* sha0 HIB2 (the 'P' (public) device) */
 247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 248         .rev_offs       = 0x100,
 249         .sysc_offs      = 0x110,
 250         .syss_offs      = 0x114,
 251         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 252 };
 253
 254 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 255         .name           = "sha0",
 256         .sysc           = &am33xx_sha0_sysc,
 257 };
 258
 259 struct omap_hwmod am33xx_sha0_hwmod = {
 260         .name           = "sham",
 261         .class          = &am33xx_sha0_hwmod_class,
 262         .clkdm_name     = "l3_clkdm",
 263         .main_clk       = "l3_gclk",
 264         .prcm           = {
 265                 .omap4  = {
 266                         .modulemode     = MODULEMODE_SWCTRL,
 267                 },
 268         },
 269 };
 270
 271 /* rng */
 272 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
 273         .rev_offs       = 0x1fe0,
 274         .sysc_offs      = 0x1fe4,
 275         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
 276         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
 277         .sysc_fields    = &omap_hwmod_sysc_type1,
 278 };
 279
 280 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
 281         .name           = "rng",
 282         .sysc           = &am33xx_rng_sysc,
 283 };
 284
 285 struct omap_hwmod am33xx_rng_hwmod = {
 286         .name           = "rng",
 287         .class          = &am33xx_rng_hwmod_class,
 288         .clkdm_name     = "l4ls_clkdm",
 289         .flags          = HWMOD_SWSUP_SIDLE,
 290         .main_clk       = "rng_fck",
 291         .prcm           = {
 292                 .omap4  = {
 293                         .modulemode     = MODULEMODE_SWCTRL,
 294                 },
 295         },
 296 };
 297
 298 /* ocmcram */
 299 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 300         .name = "ocmcram",
 301 };
 302
 303 struct omap_hwmod am33xx_ocmcram_hwmod = {
 304         .name           = "ocmcram",
 305         .class          = &am33xx_ocmcram_hwmod_class,
 306         .clkdm_name     = "l3_clkdm",
 307         .flags          = HWMOD_INIT_NO_IDLE,
 308         .main_clk       = "l3_gclk",
 309         .prcm           = {
 310                 .omap4  = {
 311                         .modulemode     = MODULEMODE_SWCTRL,
 312                 },
 313         },
 314 };
 315
 316 /* 'smartreflex' class */
 317 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 318         .name           = "smartreflex",
 319 };
 320
 321 /* smartreflex0 */
 322 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 323         .name           = "smartreflex0",
 324         .class          = &am33xx_smartreflex_hwmod_class,
 325         .clkdm_name     = "l4_wkup_clkdm",
 326         .main_clk       = "smartreflex0_fck",
 327         .prcm           = {
 328                 .omap4  = {
 329                         .modulemode     = MODULEMODE_SWCTRL,
 330                 },
 331         },
 332 };
 333
 334 /* smartreflex1 */
 335 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 336         .name           = "smartreflex1",
 337         .class          = &am33xx_smartreflex_hwmod_class,
 338         .clkdm_name     = "l4_wkup_clkdm",
 339         .main_clk       = "smartreflex1_fck",
 340         .prcm           = {
 341                 .omap4  = {
 342                         .modulemode     = MODULEMODE_SWCTRL,
 343                 },
 344         },
 345 };
 346
 347 /*
 348  * 'control' module class
 349  */
 350 struct omap_hwmod_class am33xx_control_hwmod_class = {
 351         .name           = "control",
 352 };
 353
 354 /*
 355  * 'cpgmac' class
 356  * cpsw/cpgmac sub system
 357  */
 358 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 359         .rev_offs       = 0x0,
 360         .sysc_offs      = 0x8,
 361         .syss_offs      = 0x4,
 362         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 363                            SYSS_HAS_RESET_STATUS),
 364         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 365                            MSTANDBY_NO),
 366         .sysc_fields    = &omap_hwmod_sysc_type3,
 367 };
 368
 369 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 370         .name           = "cpgmac0",
 371         .sysc           = &am33xx_cpgmac_sysc,
 372 };
 373
 374 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 375         .name           = "cpgmac0",
 376         .class          = &am33xx_cpgmac0_hwmod_class,
 377         .clkdm_name     = "cpsw_125mhz_clkdm",
 378         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 379         .main_clk       = "cpsw_125mhz_gclk",
 380         .mpu_rt_idx     = 1,
 381         .prcm           = {
 382                 .omap4  = {
 383                         .modulemode     = MODULEMODE_SWCTRL,
 384                 },
 385         },
 386 };
 387
 388 /*
 389  * mdio class
 390  */
 391 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 392         .name           = "davinci_mdio",
 393 };
 394
 395 struct omap_hwmod am33xx_mdio_hwmod = {
 396         .name           = "davinci_mdio",
 397         .class          = &am33xx_mdio_hwmod_class,
 398         .clkdm_name     = "cpsw_125mhz_clkdm",
 399         .main_clk       = "cpsw_125mhz_gclk",
 400 };
 401
 402 /*
 403  * dcan class
 404  */
 405 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 406         .name = "d_can",
 407 };
 408
 409 /* dcan0 */
 410 struct omap_hwmod am33xx_dcan0_hwmod = {
 411         .name           = "d_can0",
 412         .class          = &am33xx_dcan_hwmod_class,
 413         .clkdm_name     = "l4ls_clkdm",
 414         .main_clk       = "dcan0_fck",
 415         .prcm           = {
 416                 .omap4  = {
 417                         .modulemode     = MODULEMODE_SWCTRL,
 418                 },
 419         },
 420 };
 421
 422 /* dcan1 */
 423 struct omap_hwmod am33xx_dcan1_hwmod = {
 424         .name           = "d_can1",
 425         .class          = &am33xx_dcan_hwmod_class,
 426         .clkdm_name     = "l4ls_clkdm",
 427         .main_clk       = "dcan1_fck",
 428         .prcm           = {
 429                 .omap4  = {
 430                         .modulemode     = MODULEMODE_SWCTRL,
 431                 },
 432         },
 433 };
 434
 435 /* elm */
 436 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 437         .rev_offs       = 0x0000,
 438         .sysc_offs      = 0x0010,
 439         .syss_offs      = 0x0014,
 440         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 441                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 442                         SYSS_HAS_RESET_STATUS),
 443         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 444         .sysc_fields    = &omap_hwmod_sysc_type1,
 445 };
 446
 447 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 448         .name           = "elm",
 449         .sysc           = &am33xx_elm_sysc,
 450 };
 451
 452 struct omap_hwmod am33xx_elm_hwmod = {
 453         .name           = "elm",
 454         .class          = &am33xx_elm_hwmod_class,
 455         .clkdm_name     = "l4ls_clkdm",
 456         .main_clk       = "l4ls_gclk",
 457         .prcm           = {
 458                 .omap4  = {
 459                         .modulemode     = MODULEMODE_SWCTRL,
 460                 },
 461         },
 462 };
 463
 464 /* pwmss  */
 465 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 466         .rev_offs       = 0x0,
 467         .sysc_offs      = 0x4,
 468         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 469         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 470                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 471                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 472         .sysc_fields    = &omap_hwmod_sysc_type2,
 473 };
 474
 475 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 476         .name           = "epwmss",
 477         .sysc           = &am33xx_epwmss_sysc,
 478 };
 479
 480 /* epwmss0 */
 481 struct omap_hwmod am33xx_epwmss0_hwmod = {
 482         .name           = "epwmss0",
 483         .class          = &am33xx_epwmss_hwmod_class,
 484         .clkdm_name     = "l4ls_clkdm",
 485         .main_clk       = "l4ls_gclk",
 486         .prcm           = {
 487                 .omap4  = {
 488                         .modulemode     = MODULEMODE_SWCTRL,
 489                 },
 490         },
 491 };
 492
 493 /* epwmss1 */
 494 struct omap_hwmod am33xx_epwmss1_hwmod = {
 495         .name           = "epwmss1",
 496         .class          = &am33xx_epwmss_hwmod_class,
 497         .clkdm_name     = "l4ls_clkdm",
 498         .main_clk       = "l4ls_gclk",
 499         .prcm           = {
 500                 .omap4  = {
 501                         .modulemode     = MODULEMODE_SWCTRL,
 502                 },
 503         },
 504 };
 505
 506 /* epwmss2 */
 507 struct omap_hwmod am33xx_epwmss2_hwmod = {
 508         .name           = "epwmss2",
 509         .class          = &am33xx_epwmss_hwmod_class,
 510         .clkdm_name     = "l4ls_clkdm",
 511         .main_clk       = "l4ls_gclk",
 512         .prcm           = {
 513                 .omap4  = {
 514                         .modulemode     = MODULEMODE_SWCTRL,
 515                 },
 516         },
 517 };
 518
 519 /*
 520  * 'gpio' class: for gpio 0,1,2,3
 521  */
 522 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 523         .rev_offs       = 0x0000,
 524         .sysc_offs      = 0x0010,
 525         .syss_offs      = 0x0114,
 526         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 527                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 528                           SYSS_HAS_RESET_STATUS),
 529         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 530                           SIDLE_SMART_WKUP),
 531         .sysc_fields    = &omap_hwmod_sysc_type1,
 532 };
 533
 534 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 535         .name           = "gpio",
 536         .sysc           = &am33xx_gpio_sysc,
 537         .rev            = 2,
 538 };
 539
 540 /* gpio1 */
 541 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 542         { .role = "dbclk", .clk = "gpio1_dbclk" },
 543 };
 544
 545 struct omap_hwmod am33xx_gpio1_hwmod = {
 546         .name           = "gpio2",
 547         .class          = &am33xx_gpio_hwmod_class,
 548         .clkdm_name     = "l4ls_clkdm",
 549         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 550         .main_clk       = "l4ls_gclk",
 551         .prcm           = {
 552                 .omap4  = {
 553                         .modulemode     = MODULEMODE_SWCTRL,
 554                 },
 555         },
 556         .opt_clks       = gpio1_opt_clks,
 557         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 558 };
 559
 560 /* gpio2 */
 561 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 562         { .role = "dbclk", .clk = "gpio2_dbclk" },
 563 };
 564
 565 struct omap_hwmod am33xx_gpio2_hwmod = {
 566         .name           = "gpio3",
 567         .class          = &am33xx_gpio_hwmod_class,
 568         .clkdm_name     = "l4ls_clkdm",
 569         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 570         .main_clk       = "l4ls_gclk",
 571         .prcm           = {
 572                 .omap4  = {
 573                         .modulemode     = MODULEMODE_SWCTRL,
 574                 },
 575         },
 576         .opt_clks       = gpio2_opt_clks,
 577         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 578 };
 579
 580 /* gpio3 */
 581 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 582         { .role = "dbclk", .clk = "gpio3_dbclk" },
 583 };
 584
 585 struct omap_hwmod am33xx_gpio3_hwmod = {
 586         .name           = "gpio4",
 587         .class          = &am33xx_gpio_hwmod_class,
 588         .clkdm_name     = "l4ls_clkdm",
 589         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 590         .main_clk       = "l4ls_gclk",
 591         .prcm           = {
 592                 .omap4  = {
 593                         .modulemode     = MODULEMODE_SWCTRL,
 594                 },
 595         },
 596         .opt_clks       = gpio3_opt_clks,
 597         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 598 };
 599
 600 /* gpmc */
 601 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 602         .rev_offs       = 0x0,
 603         .sysc_offs      = 0x10,
 604         .syss_offs      = 0x14,
 605         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 606                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 607         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 608         .sysc_fields    = &omap_hwmod_sysc_type1,
 609 };
 610
 611 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 612         .name           = "gpmc",
 613         .sysc           = &gpmc_sysc,
 614 };
 615
 616 struct omap_hwmod am33xx_gpmc_hwmod = {
 617         .name           = "gpmc",
 618         .class          = &am33xx_gpmc_hwmod_class,
 619         .clkdm_name     = "l3s_clkdm",
 620         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 621         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 622         .main_clk       = "l3s_gclk",
 623         .prcm           = {
 624                 .omap4  = {
 625                         .modulemode     = MODULEMODE_SWCTRL,
 626                 },
 627         },
 628 };
 629
 630 /* 'i2c' class */
 631 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 632         .sysc_offs      = 0x0010,
 633         .syss_offs      = 0x0090,
 634         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 635                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 636                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 637         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 638                           SIDLE_SMART_WKUP),
 639         .sysc_fields    = &omap_hwmod_sysc_type1,
 640 };
 641
 642 static struct omap_hwmod_class i2c_class = {
 643         .name           = "i2c",
 644         .sysc           = &am33xx_i2c_sysc,
 645         .rev            = OMAP_I2C_IP_VERSION_2,
 646         .reset          = &omap_i2c_reset,
 647 };
 648
 649 /* i2c1 */
 650 struct omap_hwmod am33xx_i2c1_hwmod = {
 651         .name           = "i2c1",
 652         .class          = &i2c_class,
 653         .clkdm_name     = "l4_wkup_clkdm",
 654         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 655         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 656         .prcm           = {
 657                 .omap4  = {
 658                         .modulemode     = MODULEMODE_SWCTRL,
 659                 },
 660         },
 661 };
 662
 663 /* i2c1 */
 664 struct omap_hwmod am33xx_i2c2_hwmod = {
 665         .name           = "i2c2",
 666         .class          = &i2c_class,
 667         .clkdm_name     = "l4ls_clkdm",
 668         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 669         .main_clk       = "dpll_per_m2_div4_ck",
 670         .prcm           = {
 671                 .omap4 = {
 672                         .modulemode     = MODULEMODE_SWCTRL,
 673                 },
 674         },
 675 };
 676
 677 /* i2c3 */
 678 struct omap_hwmod am33xx_i2c3_hwmod = {
 679         .name           = "i2c3",
 680         .class          = &i2c_class,
 681         .clkdm_name     = "l4ls_clkdm",
 682         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 683         .main_clk       = "dpll_per_m2_div4_ck",
 684         .prcm           = {
 685                 .omap4  = {
 686                         .modulemode     = MODULEMODE_SWCTRL,
 687                 },
 688         },
 689 };
 690
 691 /*
 692  * 'mailbox' class
 693  * mailbox module allowing communication between the on-chip processors using a
 694  * queued mailbox-interrupt mechanism.
 695  */
 696 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 697         .rev_offs       = 0x0000,
 698         .sysc_offs      = 0x0010,
 699         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 700                           SYSC_HAS_SOFTRESET),
 701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 702         .sysc_fields    = &omap_hwmod_sysc_type2,
 703 };
 704
 705 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 706         .name   = "mailbox",
 707         .sysc   = &am33xx_mailbox_sysc,
 708 };
 709
 710 struct omap_hwmod am33xx_mailbox_hwmod = {
 711         .name           = "mailbox",
 712         .class          = &am33xx_mailbox_hwmod_class,
 713         .clkdm_name     = "l4ls_clkdm",
 714         .main_clk       = "l4ls_gclk",
 715         .prcm = {
 716                 .omap4 = {
 717                         .modulemode     = MODULEMODE_SWCTRL,
 718                 },
 719         },
 720 };
 721
 722 /*
 723  * 'mcasp' class
 724  */
 725 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 726         .rev_offs       = 0x0,
 727         .sysc_offs      = 0x4,
 728         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 729         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 730         .sysc_fields    = &omap_hwmod_sysc_type3,
 731 };
 732
 733 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 734         .name           = "mcasp",
 735         .sysc           = &am33xx_mcasp_sysc,
 736 };
 737
 738 /* mcasp0 */
 739 struct omap_hwmod am33xx_mcasp0_hwmod = {
 740         .name           = "mcasp0",
 741         .class          = &am33xx_mcasp_hwmod_class,
 742         .clkdm_name     = "l3s_clkdm",
 743         .main_clk       = "mcasp0_fck",
 744         .prcm           = {
 745                 .omap4  = {
 746                         .modulemode     = MODULEMODE_SWCTRL,
 747                 },
 748         },
 749 };
 750
 751 /* mcasp1 */
 752 struct omap_hwmod am33xx_mcasp1_hwmod = {
 753         .name           = "mcasp1",
 754         .class          = &am33xx_mcasp_hwmod_class,
 755         .clkdm_name     = "l3s_clkdm",
 756         .main_clk       = "mcasp1_fck",
 757         .prcm           = {
 758                 .omap4  = {
 759                         .modulemode     = MODULEMODE_SWCTRL,
 760                 },
 761         },
 762 };
 763
 764 /* 'mmc' class */
 765 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 766         .rev_offs       = 0x2fc,
 767         .sysc_offs      = 0x110,
 768         .syss_offs      = 0x114,
 769         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 770                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 771                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 773         .sysc_fields    = &omap_hwmod_sysc_type1,
 774 };
 775
 776 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 777         .name           = "mmc",
 778         .sysc           = &am33xx_mmc_sysc,
 779 };
 780
 781 /* mmc0 */
 782 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
 783         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 784 };
 785
 786 struct omap_hwmod am33xx_mmc0_hwmod = {
 787         .name           = "mmc1",
 788         .class          = &am33xx_mmc_hwmod_class,
 789         .clkdm_name     = "l4ls_clkdm",
 790         .main_clk       = "mmc_clk",
 791         .prcm           = {
 792                 .omap4  = {
 793                         .modulemode     = MODULEMODE_SWCTRL,
 794                 },
 795         },
 796         .dev_attr       = &am33xx_mmc0_dev_attr,
 797 };
 798
 799 /* mmc1 */
 800 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
 801         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 802 };
 803
 804 struct omap_hwmod am33xx_mmc1_hwmod = {
 805         .name           = "mmc2",
 806         .class          = &am33xx_mmc_hwmod_class,
 807         .clkdm_name     = "l4ls_clkdm",
 808         .main_clk       = "mmc_clk",
 809         .prcm           = {
 810                 .omap4  = {
 811                         .modulemode     = MODULEMODE_SWCTRL,
 812                 },
 813         },
 814         .dev_attr       = &am33xx_mmc1_dev_attr,
 815 };
 816
 817 /* mmc2 */
 818 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
 819         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 820 };
 821 struct omap_hwmod am33xx_mmc2_hwmod = {
 822         .name           = "mmc3",
 823         .class          = &am33xx_mmc_hwmod_class,
 824         .clkdm_name     = "l3s_clkdm",
 825         .main_clk       = "mmc_clk",
 826         .prcm           = {
 827                 .omap4  = {
 828                         .modulemode     = MODULEMODE_SWCTRL,
 829                 },
 830         },
 831         .dev_attr       = &am33xx_mmc2_dev_attr,
 832 };
 833
 834 /*
 835  * 'rtc' class
 836  * rtc subsystem
 837  */
 838 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 839         .rev_offs       = 0x0074,
 840         .sysc_offs      = 0x0078,
 841         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 842         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 843                           SIDLE_SMART | SIDLE_SMART_WKUP),
 844         .sysc_fields    = &omap_hwmod_sysc_type3,
 845 };
 846
 847 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 848         .name           = "rtc",
 849         .sysc           = &am33xx_rtc_sysc,
 850         .unlock         = &omap_hwmod_rtc_unlock,
 851         .lock           = &omap_hwmod_rtc_lock,
 852 };
 853
 854 struct omap_hwmod am33xx_rtc_hwmod = {
 855         .name           = "rtc",
 856         .class          = &am33xx_rtc_hwmod_class,
 857         .clkdm_name     = "l4_rtc_clkdm",
 858         .main_clk       = "clk_32768_ck",
 859         .prcm           = {
 860                 .omap4  = {
 861                         .modulemode     = MODULEMODE_SWCTRL,
 862                 },
 863         },
 864 };
 865
 866 /* 'spi' class */
 867 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 868         .rev_offs       = 0x0000,
 869         .sysc_offs      = 0x0110,
 870         .syss_offs      = 0x0114,
 871         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 872                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 873                           SYSS_HAS_RESET_STATUS),
 874         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 875         .sysc_fields    = &omap_hwmod_sysc_type1,
 876 };
 877
 878 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 879         .name           = "mcspi",
 880         .sysc           = &am33xx_mcspi_sysc,
 881 };
 882
 883 /* spi0 */
 884 struct omap_hwmod am33xx_spi0_hwmod = {
 885         .name           = "spi0",
 886         .class          = &am33xx_spi_hwmod_class,
 887         .clkdm_name     = "l4ls_clkdm",
 888         .main_clk       = "dpll_per_m2_div4_ck",
 889         .prcm           = {
 890                 .omap4  = {
 891                         .modulemode     = MODULEMODE_SWCTRL,
 892                 },
 893         },
 894 };
 895
 896 /* spi1 */
 897 struct omap_hwmod am33xx_spi1_hwmod = {
 898         .name           = "spi1",
 899         .class          = &am33xx_spi_hwmod_class,
 900         .clkdm_name     = "l4ls_clkdm",
 901         .main_clk       = "dpll_per_m2_div4_ck",
 902         .prcm           = {
 903                 .omap4  = {
 904                         .modulemode     = MODULEMODE_SWCTRL,
 905                 },
 906         },
 907 };
 908
 909 /*
 910  * 'spinlock' class
 911  * spinlock provides hardware assistance for synchronizing the
 912  * processes running on multiple processors
 913  */
 914
 915 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 916         .rev_offs       = 0x0000,
 917         .sysc_offs      = 0x0010,
 918         .syss_offs      = 0x0014,
 919         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 920                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 921                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 922         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 923         .sysc_fields    = &omap_hwmod_sysc_type1,
 924 };
 925
 926 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 927         .name           = "spinlock",
 928         .sysc           = &am33xx_spinlock_sysc,
 929 };
 930
 931 struct omap_hwmod am33xx_spinlock_hwmod = {
 932         .name           = "spinlock",
 933         .class          = &am33xx_spinlock_hwmod_class,
 934         .clkdm_name     = "l4ls_clkdm",
 935         .main_clk       = "l4ls_gclk",
 936         .prcm           = {
 937                 .omap4  = {
 938                         .modulemode     = MODULEMODE_SWCTRL,
 939                 },
 940         },
 941 };
 942
 943 /* 'timer 2-7' class */
 944 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 945         .rev_offs       = 0x0000,
 946         .sysc_offs      = 0x0010,
 947         .syss_offs      = 0x0014,
 948         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 949         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 950                           SIDLE_SMART_WKUP),
 951         .sysc_fields    = &omap_hwmod_sysc_type2,
 952 };
 953
 954 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 955         .name           = "timer",
 956         .sysc           = &am33xx_timer_sysc,
 957 };
 958
 959 /* timer1 1ms */
 960 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 961         .rev_offs       = 0x0000,
 962         .sysc_offs      = 0x0010,
 963         .syss_offs      = 0x0014,
 964         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 965                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 966                         SYSS_HAS_RESET_STATUS),
 967         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 968         .sysc_fields    = &omap_hwmod_sysc_type1,
 969 };
 970
 971 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 972         .name           = "timer",
 973         .sysc           = &am33xx_timer1ms_sysc,
 974 };
 975
 976 struct omap_hwmod am33xx_timer1_hwmod = {
 977         .name           = "timer1",
 978         .class          = &am33xx_timer1ms_hwmod_class,
 979         .clkdm_name     = "l4_wkup_clkdm",
 980         .main_clk       = "timer1_fck",
 981         .prcm           = {
 982                 .omap4  = {
 983                         .modulemode     = MODULEMODE_SWCTRL,
 984                 },
 985         },
 986 };
 987
 988 struct omap_hwmod am33xx_timer2_hwmod = {
 989         .name           = "timer2",
 990         .class          = &am33xx_timer_hwmod_class,
 991         .clkdm_name     = "l4ls_clkdm",
 992         .main_clk       = "timer2_fck",
 993         .prcm           = {
 994                 .omap4  = {
 995                         .modulemode     = MODULEMODE_SWCTRL,
 996                 },
 997         },
 998 };
 999
1000 struct omap_hwmod am33xx_timer3_hwmod = {
1001         .name           = "timer3",
1002         .class          = &am33xx_timer_hwmod_class,
1003         .clkdm_name     = "l4ls_clkdm",
1004         .main_clk       = "timer3_fck",
1005         .prcm           = {
1006                 .omap4  = {
1007                         .modulemode     = MODULEMODE_SWCTRL,
1008                 },
1009         },
1010 };
1011
1012 struct omap_hwmod am33xx_timer4_hwmod = {
1013         .name           = "timer4",
1014         .class          = &am33xx_timer_hwmod_class,
1015         .clkdm_name     = "l4ls_clkdm",
1016         .main_clk       = "timer4_fck",
1017         .prcm           = {
1018                 .omap4  = {
1019                         .modulemode     = MODULEMODE_SWCTRL,
1020                 },
1021         },
1022 };
1023
1024 struct omap_hwmod am33xx_timer5_hwmod = {
1025         .name           = "timer5",
1026         .class          = &am33xx_timer_hwmod_class,
1027         .clkdm_name     = "l4ls_clkdm",
1028         .main_clk       = "timer5_fck",
1029         .prcm           = {
1030                 .omap4  = {
1031                         .modulemode     = MODULEMODE_SWCTRL,
1032                 },
1033         },
1034 };
1035
1036 struct omap_hwmod am33xx_timer6_hwmod = {
1037         .name           = "timer6",
1038         .class          = &am33xx_timer_hwmod_class,
1039         .clkdm_name     = "l4ls_clkdm",
1040         .main_clk       = "timer6_fck",
1041         .prcm           = {
1042                 .omap4  = {
1043                         .modulemode     = MODULEMODE_SWCTRL,
1044                 },
1045         },
1046 };
1047
1048 struct omap_hwmod am33xx_timer7_hwmod = {
1049         .name           = "timer7",
1050         .class          = &am33xx_timer_hwmod_class,
1051         .clkdm_name     = "l4ls_clkdm",
1052         .main_clk       = "timer7_fck",
1053         .prcm           = {
1054                 .omap4  = {
1055                         .modulemode     = MODULEMODE_SWCTRL,
1056                 },
1057         },
1058 };
1059
1060 /* tpcc */
1061 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1062         .name           = "tpcc",
1063 };
1064
1065 struct omap_hwmod am33xx_tpcc_hwmod = {
1066         .name           = "tpcc",
1067         .class          = &am33xx_tpcc_hwmod_class,
1068         .clkdm_name     = "l3_clkdm",
1069         .main_clk       = "l3_gclk",
1070         .prcm           = {
1071                 .omap4  = {
1072                         .modulemode     = MODULEMODE_SWCTRL,
1073                 },
1074         },
1075 };
1076
1077 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1078         .rev_offs       = 0x0,
1079         .sysc_offs      = 0x10,
1080         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1081                           SYSC_HAS_MIDLEMODE),
1082         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1083         .sysc_fields    = &omap_hwmod_sysc_type2,
1084 };
1085
1086 /* 'tptc' class */
1087 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1088         .name           = "tptc",
1089         .sysc           = &am33xx_tptc_sysc,
1090 };
1091
1092 /* tptc0 */
1093 struct omap_hwmod am33xx_tptc0_hwmod = {
1094         .name           = "tptc0",
1095         .class          = &am33xx_tptc_hwmod_class,
1096         .clkdm_name     = "l3_clkdm",
1097         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1098         .main_clk       = "l3_gclk",
1099         .prcm           = {
1100                 .omap4  = {
1101                         .modulemode     = MODULEMODE_SWCTRL,
1102                 },
1103         },
1104 };
1105
1106 /* tptc1 */
1107 struct omap_hwmod am33xx_tptc1_hwmod = {
1108         .name           = "tptc1",
1109         .class          = &am33xx_tptc_hwmod_class,
1110         .clkdm_name     = "l3_clkdm",
1111         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1112         .main_clk       = "l3_gclk",
1113         .prcm           = {
1114                 .omap4  = {
1115                         .modulemode     = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /* tptc2 */
1121 struct omap_hwmod am33xx_tptc2_hwmod = {
1122         .name           = "tptc2",
1123         .class          = &am33xx_tptc_hwmod_class,
1124         .clkdm_name     = "l3_clkdm",
1125         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1126         .main_clk       = "l3_gclk",
1127         .prcm           = {
1128                 .omap4  = {
1129                         .modulemode     = MODULEMODE_SWCTRL,
1130                 },
1131         },
1132 };
1133
1134 /* 'uart' class */
1135 static struct omap_hwmod_class_sysconfig uart_sysc = {
1136         .rev_offs       = 0x50,
1137         .sysc_offs      = 0x54,
1138         .syss_offs      = 0x58,
1139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1140                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1141         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1142                           SIDLE_SMART_WKUP),
1143         .sysc_fields    = &omap_hwmod_sysc_type1,
1144 };
1145
1146 static struct omap_hwmod_class uart_class = {
1147         .name           = "uart",
1148         .sysc           = &uart_sysc,
1149 };
1150
1151 struct omap_hwmod am33xx_uart1_hwmod = {
1152         .name           = "uart1",
1153         .class          = &uart_class,
1154         .clkdm_name     = "l4_wkup_clkdm",
1155         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1156         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1157         .prcm           = {
1158                 .omap4  = {
1159                         .modulemode     = MODULEMODE_SWCTRL,
1160                 },
1161         },
1162 };
1163
1164 struct omap_hwmod am33xx_uart2_hwmod = {
1165         .name           = "uart2",
1166         .class          = &uart_class,
1167         .clkdm_name     = "l4ls_clkdm",
1168         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1169         .main_clk       = "dpll_per_m2_div4_ck",
1170         .prcm           = {
1171                 .omap4  = {
1172                         .modulemode     = MODULEMODE_SWCTRL,
1173                 },
1174         },
1175 };
1176
1177 /* uart3 */
1178 struct omap_hwmod am33xx_uart3_hwmod = {
1179         .name           = "uart3",
1180         .class          = &uart_class,
1181         .clkdm_name     = "l4ls_clkdm",
1182         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1183         .main_clk       = "dpll_per_m2_div4_ck",
1184         .prcm           = {
1185                 .omap4  = {
1186                         .modulemode     = MODULEMODE_SWCTRL,
1187                 },
1188         },
1189 };
1190
1191 struct omap_hwmod am33xx_uart4_hwmod = {
1192         .name           = "uart4",
1193         .class          = &uart_class,
1194         .clkdm_name     = "l4ls_clkdm",
1195         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1196         .main_clk       = "dpll_per_m2_div4_ck",
1197         .prcm           = {
1198                 .omap4  = {
1199                         .modulemode     = MODULEMODE_SWCTRL,
1200                 },
1201         },
1202 };
1203
1204 struct omap_hwmod am33xx_uart5_hwmod = {
1205         .name           = "uart5",
1206         .class          = &uart_class,
1207         .clkdm_name     = "l4ls_clkdm",
1208         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1209         .main_clk       = "dpll_per_m2_div4_ck",
1210         .prcm           = {
1211                 .omap4  = {
1212                         .modulemode     = MODULEMODE_SWCTRL,
1213                 },
1214         },
1215 };
1216
1217 struct omap_hwmod am33xx_uart6_hwmod = {
1218         .name           = "uart6",
1219         .class          = &uart_class,
1220         .clkdm_name     = "l4ls_clkdm",
1221         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1222         .main_clk       = "dpll_per_m2_div4_ck",
1223         .prcm           = {
1224                 .omap4  = {
1225                         .modulemode     = MODULEMODE_SWCTRL,
1226                 },
1227         },
1228 };
1229
1230 /* 'wd_timer' class */
1231 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1232         .rev_offs       = 0x0,
1233         .sysc_offs      = 0x10,
1234         .syss_offs      = 0x14,
1235         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1236                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1237         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1238                         SIDLE_SMART_WKUP),
1239         .sysc_fields    = &omap_hwmod_sysc_type1,
1240 };
1241
1242 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1243         .name           = "wd_timer",
1244         .sysc           = &wdt_sysc,
1245         .pre_shutdown   = &omap2_wd_timer_disable,
1246 };
1247
1248 /*
1249  * XXX: device.c file uses hardcoded name for watchdog timer
1250  * driver "wd_timer2, so we are also using same name as of now...
1251  */
1252 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1253         .name           = "wd_timer2",
1254         .class          = &am33xx_wd_timer_hwmod_class,
1255         .clkdm_name     = "l4_wkup_clkdm",
1256         .flags          = HWMOD_SWSUP_SIDLE,
1257         .main_clk       = "wdt1_fck",
1258         .prcm           = {
1259                 .omap4  = {
1260                         .modulemode     = MODULEMODE_SWCTRL,
1261                 },
1262         },
1263 };
1264
1265 static void omap_hwmod_am33xx_clkctrl(void)
1266 {
1267         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1268         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1269         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1270         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1271         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1272         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1273         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1274         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1275         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1276         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1277         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1278         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1279         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1280         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1281         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1282         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1283         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1284         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1285         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1286         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1287         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1288         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1289         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1290         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1291         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1292         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1293         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1294         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1295         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1296         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1297         CLKCTRL(am33xx_smartreflex0_hwmod,
1298                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1299         CLKCTRL(am33xx_smartreflex1_hwmod,
1300                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1301         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1302         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1303         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1304         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1305         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1306         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1307         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1308         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1309         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1310         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1311         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1312         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1313         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1314         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1315         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1316         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1317         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1318         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1319         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1320         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1321         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1322         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1323         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1324         CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1325 }
1326
1327 static void omap_hwmod_am33xx_rst(void)
1328 {
1329         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1330         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1331         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1332 }
1333
1334 void omap_hwmod_am33xx_reg(void)
1335 {
1336         omap_hwmod_am33xx_clkctrl();
1337         omap_hwmod_am33xx_rst();
1338 }
1339
1340 static void omap_hwmod_am43xx_clkctrl(void)
1341 {
1342         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1343         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1360         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1366         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_smartreflex0_hwmod,
1373                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_smartreflex1_hwmod,
1375                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1385         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1386         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1387         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1388         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1389         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1390         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1391         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1392         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1393         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1394         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1395         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1396         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1397         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1398         CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1399 }
1400
1401 static void omap_hwmod_am43xx_rst(void)
1402 {
1403         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1404         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1405         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1406         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1407 }
1408
1409 void omap_hwmod_am43xx_reg(void)
1410 {
1411         omap_hwmod_am43xx_clkctrl();
1412         omap_hwmod_am43xx_rst();
1413 }