1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
5 * Copyright (C) 2011 Nokia Corporation
9 #include <linux/types.h>
11 #include "omap_hwmod.h"
12 #include "omap_hwmod_common_data.h"
13 #include "cm-regbits-24xx.h"
14 #include "prm-regbits-24xx.h"
22 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
33 struct omap_hwmod_class omap2_dispc_hwmod_class = {
35 .sysc = &omap2_dispc_sysc,
38 /* OMAP2xxx Timer Common */
39 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
47 .sysc_fields = &omap_hwmod_sysc_type1,
50 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
52 .sysc = &omap2xxx_timer_sysc,
57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
61 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
67 .sysc_fields = &omap_hwmod_sysc_type1,
70 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
72 .sysc = &omap2xxx_wd_timer_sysc,
73 .pre_shutdown = &omap2_wd_timer_disable,
74 .reset = &omap2_wd_timer_reset,
79 * general purpose io module
81 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
87 SYSS_HAS_RESET_STATUS),
88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
89 .sysc_fields = &omap_hwmod_sysc_type1,
92 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
94 .sysc = &omap2xxx_gpio_sysc,
99 * mailbox module allowing communication between the on-chip processors
100 * using a queued mailbox-interrupt mechanism.
103 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
110 .sysc_fields = &omap_hwmod_sysc_type1,
113 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
115 .sysc = &omap2xxx_mailbox_sysc,
120 * multichannel serial port interface (mcspi) / master/slave synchronous serial
124 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
132 .sysc_fields = &omap_hwmod_sysc_type1,
135 struct omap_hwmod_class omap2xxx_mcspi_class = {
137 .sysc = &omap2xxx_mcspi_sysc,
142 * general purpose memory controller
145 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .sysc_fields = &omap_hwmod_sysc_type1,
155 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
157 .sysc = &omap2xxx_gpmc_sysc,
165 struct omap_hwmod omap2xxx_l3_main_hwmod = {
167 .class = &l3_hwmod_class,
168 .flags = HWMOD_NO_IDLEST,
172 struct omap_hwmod omap2xxx_l4_core_hwmod = {
174 .class = &l4_hwmod_class,
175 .flags = HWMOD_NO_IDLEST,
179 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
181 .class = &l4_hwmod_class,
182 .flags = HWMOD_NO_IDLEST,
186 struct omap_hwmod omap2xxx_mpu_hwmod = {
188 .class = &mpu_hwmod_class,
189 .main_clk = "mpu_ck",
193 struct omap_hwmod omap2xxx_iva_hwmod = {
195 .class = &iva_hwmod_class,
199 struct omap_hwmod omap2xxx_timer1_hwmod = {
201 .main_clk = "gpt1_fck",
204 .module_offs = WKUP_MOD,
206 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
209 .class = &omap2xxx_timer_hwmod_class,
210 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
214 struct omap_hwmod omap2xxx_timer2_hwmod = {
216 .main_clk = "gpt2_fck",
219 .module_offs = CORE_MOD,
221 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
224 .class = &omap2xxx_timer_hwmod_class,
225 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
229 struct omap_hwmod omap2xxx_timer3_hwmod = {
231 .main_clk = "gpt3_fck",
234 .module_offs = CORE_MOD,
236 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
239 .class = &omap2xxx_timer_hwmod_class,
240 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
244 struct omap_hwmod omap2xxx_timer4_hwmod = {
246 .main_clk = "gpt4_fck",
249 .module_offs = CORE_MOD,
251 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
254 .class = &omap2xxx_timer_hwmod_class,
255 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
259 struct omap_hwmod omap2xxx_timer5_hwmod = {
261 .main_clk = "gpt5_fck",
264 .module_offs = CORE_MOD,
266 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
269 .class = &omap2xxx_timer_hwmod_class,
270 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
274 struct omap_hwmod omap2xxx_timer6_hwmod = {
276 .main_clk = "gpt6_fck",
279 .module_offs = CORE_MOD,
281 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
284 .class = &omap2xxx_timer_hwmod_class,
285 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289 struct omap_hwmod omap2xxx_timer7_hwmod = {
291 .main_clk = "gpt7_fck",
294 .module_offs = CORE_MOD,
296 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
299 .class = &omap2xxx_timer_hwmod_class,
300 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
304 struct omap_hwmod omap2xxx_timer8_hwmod = {
306 .main_clk = "gpt8_fck",
309 .module_offs = CORE_MOD,
311 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
314 .class = &omap2xxx_timer_hwmod_class,
315 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
319 struct omap_hwmod omap2xxx_timer9_hwmod = {
321 .main_clk = "gpt9_fck",
324 .module_offs = CORE_MOD,
326 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
329 .class = &omap2xxx_timer_hwmod_class,
330 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
334 struct omap_hwmod omap2xxx_timer10_hwmod = {
336 .main_clk = "gpt10_fck",
339 .module_offs = CORE_MOD,
341 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
344 .class = &omap2xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
349 struct omap_hwmod omap2xxx_timer11_hwmod = {
351 .main_clk = "gpt11_fck",
354 .module_offs = CORE_MOD,
356 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
359 .class = &omap2xxx_timer_hwmod_class,
360 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
364 struct omap_hwmod omap2xxx_timer12_hwmod = {
366 .main_clk = "gpt12_fck",
369 .module_offs = CORE_MOD,
371 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
374 .class = &omap2xxx_timer_hwmod_class,
375 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
379 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
381 .class = &omap2xxx_wd_timer_hwmod_class,
382 .main_clk = "mpu_wdt_fck",
385 .module_offs = WKUP_MOD,
387 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
394 struct omap_hwmod omap2xxx_uart1_hwmod = {
396 .main_clk = "uart1_fck",
397 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
400 .module_offs = CORE_MOD,
402 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
405 .class = &omap2_uart_class,
410 struct omap_hwmod omap2xxx_uart2_hwmod = {
412 .main_clk = "uart2_fck",
413 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
416 .module_offs = CORE_MOD,
418 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
421 .class = &omap2_uart_class,
426 struct omap_hwmod omap2xxx_uart3_hwmod = {
428 .main_clk = "uart3_fck",
429 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
432 .module_offs = CORE_MOD,
434 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
437 .class = &omap2_uart_class,
442 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
444 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
445 * driver does not use these clocks.
447 { .role = "tv_clk", .clk = "dss_54m_fck" },
448 { .role = "sys_clk", .clk = "dss2_fck" },
451 struct omap_hwmod omap2xxx_dss_core_hwmod = {
453 .class = &omap2_dss_hwmod_class,
454 .main_clk = "dss1_fck", /* instead of dss_fck */
457 .module_offs = CORE_MOD,
461 .opt_clks = dss_opt_clks,
462 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
463 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
466 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
468 .class = &omap2_dispc_hwmod_class,
469 .main_clk = "dss1_fck",
472 .module_offs = CORE_MOD,
476 .flags = HWMOD_NO_IDLEST,
477 .dev_attr = &omap2_3_dss_dispc_dev_attr,
480 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
481 { .role = "ick", .clk = "dss_ick" },
484 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
486 .class = &omap2_rfbi_hwmod_class,
487 .main_clk = "dss1_fck",
490 .module_offs = CORE_MOD,
493 .opt_clks = dss_rfbi_opt_clks,
494 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
495 .flags = HWMOD_NO_IDLEST,
498 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
500 .class = &omap2_venc_hwmod_class,
501 .main_clk = "dss_54m_fck",
504 .module_offs = CORE_MOD,
507 .flags = HWMOD_NO_IDLEST,
511 struct omap_hwmod omap2xxx_gpio1_hwmod = {
513 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
514 .main_clk = "gpios_fck",
517 .module_offs = WKUP_MOD,
519 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
522 .class = &omap2xxx_gpio_hwmod_class,
526 struct omap_hwmod omap2xxx_gpio2_hwmod = {
528 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
529 .main_clk = "gpios_fck",
532 .module_offs = WKUP_MOD,
534 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
537 .class = &omap2xxx_gpio_hwmod_class,
541 struct omap_hwmod omap2xxx_gpio3_hwmod = {
543 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
544 .main_clk = "gpios_fck",
547 .module_offs = WKUP_MOD,
549 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
552 .class = &omap2xxx_gpio_hwmod_class,
556 struct omap_hwmod omap2xxx_gpio4_hwmod = {
558 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
559 .main_clk = "gpios_fck",
562 .module_offs = WKUP_MOD,
564 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
567 .class = &omap2xxx_gpio_hwmod_class,
571 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
573 .main_clk = "mcspi1_fck",
576 .module_offs = CORE_MOD,
578 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
581 .class = &omap2xxx_mcspi_class,
585 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
587 .main_clk = "mcspi2_fck",
590 .module_offs = CORE_MOD,
592 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
595 .class = &omap2xxx_mcspi_class,
598 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
602 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
603 .name = "counter_32k",
604 .main_clk = "func_32k_ck",
607 .module_offs = WKUP_MOD,
609 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
612 .class = &omap2xxx_counter_hwmod_class,
616 struct omap_hwmod omap2xxx_gpmc_hwmod = {
618 .class = &omap2xxx_gpmc_hwmod_class,
619 .main_clk = "gpmc_fck",
620 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
621 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
624 .module_offs = CORE_MOD,
631 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
635 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
636 SYSS_HAS_RESET_STATUS),
637 .sysc_fields = &omap_hwmod_sysc_type1,
640 static struct omap_hwmod_class omap2_rng_hwmod_class = {
642 .sysc = &omap2_rng_sysc,
645 struct omap_hwmod omap2xxx_rng_hwmod = {
650 .module_offs = CORE_MOD,
652 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
656 * XXX The first read from the SYSSTATUS register of the RNG
657 * after the SYSCONFIG SOFTRESET bit is set triggers an
658 * imprecise external abort. It's unclear why this happens.
659 * Until this is analyzed, skip the IP block reset.
661 .flags = HWMOD_INIT_NO_RESET,
662 .class = &omap2_rng_hwmod_class,
667 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
671 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
672 SYSS_HAS_RESET_STATUS),
673 .sysc_fields = &omap_hwmod_sysc_type1,
676 static struct omap_hwmod_class omap2xxx_sham_class = {
678 .sysc = &omap2_sham_sysc,
681 struct omap_hwmod omap2xxx_sham_hwmod = {
686 .module_offs = CORE_MOD,
688 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
691 .class = &omap2xxx_sham_class,
696 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
700 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
701 SYSS_HAS_RESET_STATUS),
702 .sysc_fields = &omap_hwmod_sysc_type1,
705 static struct omap_hwmod_class omap2xxx_aes_class = {
707 .sysc = &omap2_aes_sysc,
710 struct omap_hwmod omap2xxx_aes_hwmod = {
715 .module_offs = CORE_MOD,
717 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
720 .class = &omap2xxx_aes_class,