2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <plat/omap_hwmod.h>
12 #include <plat/serial.h>
13 #include <plat/gpio.h>
15 #include <plat/dmtimer.h>
16 #include <plat/mcspi.h>
18 #include <mach/irqs.h>
20 #include "omap_hwmod_common_data.h"
21 #include "cm-regbits-24xx.h"
22 #include "prm-regbits-24xx.h"
25 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
30 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
31 { .name = "dispc", .dma_req = 5 },
40 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
44 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
45 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
47 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
51 struct omap_hwmod_class omap2_dispc_hwmod_class = {
53 .sysc = &omap2_dispc_sysc,
56 /* OMAP2xxx Timer Common */
57 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
61 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
62 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
64 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
65 .sysc_fields = &omap_hwmod_sysc_type1,
68 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
70 .sysc = &omap2xxx_timer_sysc,
71 .rev = OMAP_TIMER_IP_VERSION_1,
76 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
80 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
84 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
85 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
86 .sysc_fields = &omap_hwmod_sysc_type1,
89 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
91 .sysc = &omap2xxx_wd_timer_sysc,
92 .pre_shutdown = &omap2_wd_timer_disable,
93 .reset = &omap2_wd_timer_reset,
98 * general purpose io module
100 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
104 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
105 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
106 SYSS_HAS_RESET_STATUS),
107 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
108 .sysc_fields = &omap_hwmod_sysc_type1,
111 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
113 .sysc = &omap2xxx_gpio_sysc,
118 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
122 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
123 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
124 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
125 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
129 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
131 .sysc = &omap2xxx_dma_sysc,
136 * mailbox module allowing communication between the on-chip processors
137 * using a queued mailbox-interrupt mechanism.
140 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
144 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
145 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
146 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
147 .sysc_fields = &omap_hwmod_sysc_type1,
150 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
152 .sysc = &omap2xxx_mailbox_sysc,
157 * multichannel serial port interface (mcspi) / master/slave synchronous serial
161 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
165 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
166 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
167 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
168 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
169 .sysc_fields = &omap_hwmod_sysc_type1,
172 struct omap_hwmod_class omap2xxx_mcspi_class = {
174 .sysc = &omap2xxx_mcspi_sysc,
175 .rev = OMAP2_MCSPI_REV,
183 struct omap_hwmod omap2xxx_l3_main_hwmod = {
185 .class = &l3_hwmod_class,
186 .flags = HWMOD_NO_IDLEST,
190 struct omap_hwmod omap2xxx_l4_core_hwmod = {
192 .class = &l4_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
197 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
204 struct omap_hwmod omap2xxx_mpu_hwmod = {
206 .class = &mpu_hwmod_class,
207 .main_clk = "mpu_ck",
211 struct omap_hwmod omap2xxx_iva_hwmod = {
213 .class = &iva_hwmod_class,
216 /* always-on timers dev attribute */
217 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
218 .timer_capability = OMAP_TIMER_ALWON,
221 /* pwm timers dev attribute */
222 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
223 .timer_capability = OMAP_TIMER_HAS_PWM,
228 struct omap_hwmod omap2xxx_timer1_hwmod = {
230 .mpu_irqs = omap2_timer1_mpu_irqs,
231 .main_clk = "gpt1_fck",
235 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
236 .module_offs = WKUP_MOD,
238 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
241 .dev_attr = &capability_alwon_dev_attr,
242 .class = &omap2xxx_timer_hwmod_class,
247 struct omap_hwmod omap2xxx_timer2_hwmod = {
249 .mpu_irqs = omap2_timer2_mpu_irqs,
250 .main_clk = "gpt2_fck",
254 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
255 .module_offs = CORE_MOD,
257 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
260 .dev_attr = &capability_alwon_dev_attr,
261 .class = &omap2xxx_timer_hwmod_class,
266 struct omap_hwmod omap2xxx_timer3_hwmod = {
268 .mpu_irqs = omap2_timer3_mpu_irqs,
269 .main_clk = "gpt3_fck",
273 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
274 .module_offs = CORE_MOD,
276 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
279 .dev_attr = &capability_alwon_dev_attr,
280 .class = &omap2xxx_timer_hwmod_class,
285 struct omap_hwmod omap2xxx_timer4_hwmod = {
287 .mpu_irqs = omap2_timer4_mpu_irqs,
288 .main_clk = "gpt4_fck",
292 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
293 .module_offs = CORE_MOD,
295 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
298 .dev_attr = &capability_alwon_dev_attr,
299 .class = &omap2xxx_timer_hwmod_class,
304 struct omap_hwmod omap2xxx_timer5_hwmod = {
306 .mpu_irqs = omap2_timer5_mpu_irqs,
307 .main_clk = "gpt5_fck",
311 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
312 .module_offs = CORE_MOD,
314 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
317 .dev_attr = &capability_alwon_dev_attr,
318 .class = &omap2xxx_timer_hwmod_class,
323 struct omap_hwmod omap2xxx_timer6_hwmod = {
325 .mpu_irqs = omap2_timer6_mpu_irqs,
326 .main_clk = "gpt6_fck",
330 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
331 .module_offs = CORE_MOD,
333 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
336 .dev_attr = &capability_alwon_dev_attr,
337 .class = &omap2xxx_timer_hwmod_class,
342 struct omap_hwmod omap2xxx_timer7_hwmod = {
344 .mpu_irqs = omap2_timer7_mpu_irqs,
345 .main_clk = "gpt7_fck",
349 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
350 .module_offs = CORE_MOD,
352 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
355 .dev_attr = &capability_alwon_dev_attr,
356 .class = &omap2xxx_timer_hwmod_class,
361 struct omap_hwmod omap2xxx_timer8_hwmod = {
363 .mpu_irqs = omap2_timer8_mpu_irqs,
364 .main_clk = "gpt8_fck",
368 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
369 .module_offs = CORE_MOD,
371 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
374 .dev_attr = &capability_alwon_dev_attr,
375 .class = &omap2xxx_timer_hwmod_class,
380 struct omap_hwmod omap2xxx_timer9_hwmod = {
382 .mpu_irqs = omap2_timer9_mpu_irqs,
383 .main_clk = "gpt9_fck",
387 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
388 .module_offs = CORE_MOD,
390 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
393 .dev_attr = &capability_pwm_dev_attr,
394 .class = &omap2xxx_timer_hwmod_class,
399 struct omap_hwmod omap2xxx_timer10_hwmod = {
401 .mpu_irqs = omap2_timer10_mpu_irqs,
402 .main_clk = "gpt10_fck",
406 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
407 .module_offs = CORE_MOD,
409 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
412 .dev_attr = &capability_pwm_dev_attr,
413 .class = &omap2xxx_timer_hwmod_class,
418 struct omap_hwmod omap2xxx_timer11_hwmod = {
420 .mpu_irqs = omap2_timer11_mpu_irqs,
421 .main_clk = "gpt11_fck",
425 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
426 .module_offs = CORE_MOD,
428 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
431 .dev_attr = &capability_pwm_dev_attr,
432 .class = &omap2xxx_timer_hwmod_class,
437 struct omap_hwmod omap2xxx_timer12_hwmod = {
439 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
440 .main_clk = "gpt12_fck",
444 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
445 .module_offs = CORE_MOD,
447 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
450 .dev_attr = &capability_pwm_dev_attr,
451 .class = &omap2xxx_timer_hwmod_class,
455 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
457 .class = &omap2xxx_wd_timer_hwmod_class,
458 .main_clk = "mpu_wdt_fck",
462 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
463 .module_offs = WKUP_MOD,
465 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
472 struct omap_hwmod omap2xxx_uart1_hwmod = {
474 .mpu_irqs = omap2_uart1_mpu_irqs,
475 .sdma_reqs = omap2_uart1_sdma_reqs,
476 .main_clk = "uart1_fck",
479 .module_offs = CORE_MOD,
481 .module_bit = OMAP24XX_EN_UART1_SHIFT,
483 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
486 .class = &omap2_uart_class,
491 struct omap_hwmod omap2xxx_uart2_hwmod = {
493 .mpu_irqs = omap2_uart2_mpu_irqs,
494 .sdma_reqs = omap2_uart2_sdma_reqs,
495 .main_clk = "uart2_fck",
498 .module_offs = CORE_MOD,
500 .module_bit = OMAP24XX_EN_UART2_SHIFT,
502 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
505 .class = &omap2_uart_class,
510 struct omap_hwmod omap2xxx_uart3_hwmod = {
512 .mpu_irqs = omap2_uart3_mpu_irqs,
513 .sdma_reqs = omap2_uart3_sdma_reqs,
514 .main_clk = "uart3_fck",
517 .module_offs = CORE_MOD,
519 .module_bit = OMAP24XX_EN_UART3_SHIFT,
521 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
524 .class = &omap2_uart_class,
529 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
531 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
532 * driver does not use these clocks.
534 { .role = "tv_clk", .clk = "dss_54m_fck" },
535 { .role = "sys_clk", .clk = "dss2_fck" },
538 struct omap_hwmod omap2xxx_dss_core_hwmod = {
540 .class = &omap2_dss_hwmod_class,
541 .main_clk = "dss1_fck", /* instead of dss_fck */
542 .sdma_reqs = omap2xxx_dss_sdma_chs,
546 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
547 .module_offs = CORE_MOD,
549 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
552 .opt_clks = dss_opt_clks,
553 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
554 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
557 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
559 .class = &omap2_dispc_hwmod_class,
560 .mpu_irqs = omap2_dispc_irqs,
561 .main_clk = "dss1_fck",
565 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
566 .module_offs = CORE_MOD,
568 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
571 .flags = HWMOD_NO_IDLEST,
572 .dev_attr = &omap2_3_dss_dispc_dev_attr
575 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
576 { .role = "ick", .clk = "dss_ick" },
579 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
581 .class = &omap2_rfbi_hwmod_class,
582 .main_clk = "dss1_fck",
586 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
587 .module_offs = CORE_MOD,
590 .opt_clks = dss_rfbi_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
592 .flags = HWMOD_NO_IDLEST,
595 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
597 .class = &omap2_venc_hwmod_class,
598 .main_clk = "dss_54m_fck",
602 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
603 .module_offs = CORE_MOD,
606 .flags = HWMOD_NO_IDLEST,
610 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
616 struct omap_hwmod omap2xxx_gpio1_hwmod = {
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .mpu_irqs = omap2_gpio1_irqs,
620 .main_clk = "gpios_fck",
624 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
625 .module_offs = WKUP_MOD,
627 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
630 .class = &omap2xxx_gpio_hwmod_class,
631 .dev_attr = &omap2xxx_gpio_dev_attr,
635 struct omap_hwmod omap2xxx_gpio2_hwmod = {
637 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
638 .mpu_irqs = omap2_gpio2_irqs,
639 .main_clk = "gpios_fck",
643 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
644 .module_offs = WKUP_MOD,
646 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
649 .class = &omap2xxx_gpio_hwmod_class,
650 .dev_attr = &omap2xxx_gpio_dev_attr,
654 struct omap_hwmod omap2xxx_gpio3_hwmod = {
656 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 .mpu_irqs = omap2_gpio3_irqs,
658 .main_clk = "gpios_fck",
662 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
663 .module_offs = WKUP_MOD,
665 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
668 .class = &omap2xxx_gpio_hwmod_class,
669 .dev_attr = &omap2xxx_gpio_dev_attr,
673 struct omap_hwmod omap2xxx_gpio4_hwmod = {
675 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
676 .mpu_irqs = omap2_gpio4_irqs,
677 .main_clk = "gpios_fck",
681 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682 .module_offs = WKUP_MOD,
684 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
687 .class = &omap2xxx_gpio_hwmod_class,
688 .dev_attr = &omap2xxx_gpio_dev_attr,
692 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
696 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
698 .mpu_irqs = omap2_mcspi1_mpu_irqs,
699 .sdma_reqs = omap2_mcspi1_sdma_reqs,
700 .main_clk = "mcspi1_fck",
703 .module_offs = CORE_MOD,
705 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
707 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
710 .class = &omap2xxx_mcspi_class,
711 .dev_attr = &omap_mcspi1_dev_attr,
715 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
719 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
721 .mpu_irqs = omap2_mcspi2_mpu_irqs,
722 .sdma_reqs = omap2_mcspi2_sdma_reqs,
723 .main_clk = "mcspi2_fck",
726 .module_offs = CORE_MOD,
728 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
730 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
733 .class = &omap2xxx_mcspi_class,
734 .dev_attr = &omap_mcspi2_dev_attr,
738 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
742 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
743 .name = "counter_32k",
744 .main_clk = "func_32k_ck",
747 .module_offs = WKUP_MOD,
749 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
751 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
754 .class = &omap2xxx_counter_hwmod_class,