arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
  12  *  Gordon McNutt and RidgeRun, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/bitops.h>
  30
  31 #include <mach/clock.h>
  32 #include <mach/sram.h>
  33 #include <asm/div64.h>
  34 #include <asm/clkdev.h>
  35
  36 #include "memory.h"
  37 #include "clock.h"
  38 #include "prm.h"
  39 #include "prm-regbits-24xx.h"
  40 #include "cm.h"
  41 #include "cm-regbits-24xx.h"
  42
  43 static const struct clkops clkops_oscck;
  44 static const struct clkops clkops_fixed;
  45
  46 #include "clock24xx.h"
  47
  48 struct omap_clk {
  49         u32             cpu;
  50         struct clk_lookup lk;
  51 };
  52
  53 #define CLK(dev, con, ck, cp)           \
  54         {                               \
  55                  .cpu = cp,             \
  56                 .lk = {                 \
  57                         .dev_id = dev,  \
  58                         .con_id = con,  \
  59                         .clk = ck,      \
  60                 },                      \
  61         }
  62
  63 #define CK_243X (1 << 0)
  64 #define CK_242X (1 << 1)
  65
  66 static struct omap_clk omap24xx_clks[] = {
  67         /* external root sources */
  68         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
  69         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
  70         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
  71         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
  72         /* internal analog sources */
  73         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
  74         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
  75         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
  76         /* internal prcm root sources */
  77         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
  78         CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
  79         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
  80         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
  81         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
  82         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
  83         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
  84         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
  85         CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
  86         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
  87         CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
  88         /* mpu domain clocks */
  89         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
  90         /* dsp domain clocks */
  91         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
  92         CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
  93         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
  94         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
  95         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
  96         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
  97         /* GFX domain clocks */
  98         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
  99         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
 100         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
 101         /* Modem domain clocks */
 102         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
 103         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
 104         /* DSS domain clocks */
 105         CLK(NULL,       "dss_ick",      &dss_ick,       CK_243X | CK_242X),
 106         CLK(NULL,       "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
 107         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
 108         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X | CK_242X),
 109         /* L3 domain clocks */
 110         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
 111         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
 112         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
 113         /* L4 domain clocks */
 114         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
 115         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
 116         /* virtual meta-group clock */
 117         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
 118         /* general l4 interface ck, multi-parent functional clk */
 119         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
 120         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
 121         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
 122         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
 123         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
 124         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
 125         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
 126         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
 127         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
 128         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
 129         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
 130         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
 131         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
 132         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
 133         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
 134         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
 135         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
 136         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
 137         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
 138         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
 139         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
 140         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
 141         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
 142         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
 143         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
 144         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
 145         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
 146         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
 147         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
 148         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
 149         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
 150         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
 151         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
 152         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
 153         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
 154         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
 155         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
 156         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
 157         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
 158         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
 159         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
 160         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
 161         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
 162         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
 163         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
 164         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
 165         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
 166         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
 167         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
 168         CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
 169         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
 170         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
 171         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
 172         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
 173         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
 174         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
 175         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
 176         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
 177         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
 178         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
 179         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
 180         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
 181         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
 182         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
 183         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
 184         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
 185         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
 186         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
 187         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
 188         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
 189         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
 190         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
 191         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
 192         CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
 193         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
 194         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
 195         CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
 196         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
 197         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
 198         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
 199         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
 200         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
 201         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
 202         CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
 203         CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
 204         CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
 205         CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
 206         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
 207         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
 208         CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
 209         CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
 210         CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
 211         CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
 212         CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
 213         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
 214         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
 215         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
 216         CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
 217         CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
 218 };
 219
 220 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
 221 #define EN_APLL_STOPPED                 0
 222 #define EN_APLL_LOCKED                  3
 223
 224 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
 225 #define APLLS_CLKIN_19_2MHZ             0
 226 #define APLLS_CLKIN_13MHZ               2
 227 #define APLLS_CLKIN_12MHZ               3
 228
 229 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
 230
 231 static struct prcm_config *curr_prcm_set;
 232 static struct clk *vclk;
 233 static struct clk *sclk;
 234
 235 /*-------------------------------------------------------------------------
 236  * Omap24xx specific clock functions
 237  *-------------------------------------------------------------------------*/
 238
 239 /* This actually returns the rate of core_ck, not dpll_ck. */
 240 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
 241 {
 242         long long dpll_clk;
 243         u8 amult;
 244
 245         dpll_clk = omap2_get_dpll_rate(tclk);
 246
 247         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 248         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
 249         dpll_clk *= amult;
 250
 251         return dpll_clk;
 252 }
 253
 254 static int omap2_enable_osc_ck(struct clk *clk)
 255 {
 256         u32 pcc;
 257
 258         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 259
 260         __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
 261                       OMAP24XX_PRCM_CLKSRC_CTRL);
 262
 263         return 0;
 264 }
 265
 266 static void omap2_disable_osc_ck(struct clk *clk)
 267 {
 268         u32 pcc;
 269
 270         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 271
 272         __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
 273                       OMAP24XX_PRCM_CLKSRC_CTRL);
 274 }
 275
 276 static const struct clkops clkops_oscck = {
 277         .enable         = &omap2_enable_osc_ck,
 278         .disable        = &omap2_disable_osc_ck,
 279 };
 280
 281 #ifdef OLD_CK
 282 /* Recalculate SYST_CLK */
 283 static void omap2_sys_clk_recalc(struct clk * clk)
 284 {
 285         u32 div = PRCM_CLKSRC_CTRL;
 286         div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
 287         div >>= clk->rate_offset;
 288         clk->rate = (clk->parent->rate / div);
 289         propagate_rate(clk);
 290 }
 291 #endif  /* OLD_CK */
 292
 293 /* Enable an APLL if off */
 294 static int omap2_clk_fixed_enable(struct clk *clk)
 295 {
 296         u32 cval, apll_mask;
 297
 298         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 299
 300         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 301
 302         if ((cval & apll_mask) == apll_mask)
 303                 return 0;   /* apll already enabled */
 304
 305         cval &= ~apll_mask;
 306         cval |= apll_mask;
 307         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 308
 309         if (clk == &apll96_ck)
 310                 cval = OMAP24XX_ST_96M_APLL;
 311         else if (clk == &apll54_ck)
 312                 cval = OMAP24XX_ST_54M_APLL;
 313
 314         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
 315                             clk->name);
 316
 317         /*
 318          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 319          * fails?
 320          */
 321         return 0;
 322 }
 323
 324 /* Stop APLL */
 325 static void omap2_clk_fixed_disable(struct clk *clk)
 326 {
 327         u32 cval;
 328
 329         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 330         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 331         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 332 }
 333
 334 static const struct clkops clkops_fixed = {
 335         .enable         = &omap2_clk_fixed_enable,
 336         .disable        = &omap2_clk_fixed_disable,
 337 };
 338
 339 /*
 340  * Uses the current prcm set to tell if a rate is valid.
 341  * You can go slower, but not faster within a given rate set.
 342  */
 343 static long omap2_dpllcore_round_rate(unsigned long target_rate)
 344 {
 345         u32 high, low, core_clk_src;
 346
 347         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 348         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 349
 350         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 351                 high = curr_prcm_set->dpll_speed * 2;
 352                 low = curr_prcm_set->dpll_speed;
 353         } else {                                /* DPLL clockout x 2 */
 354                 high = curr_prcm_set->dpll_speed;
 355                 low = curr_prcm_set->dpll_speed / 2;
 356         }
 357
 358 #ifdef DOWN_VARIABLE_DPLL
 359         if (target_rate > high)
 360                 return high;
 361         else
 362                 return target_rate;
 363 #else
 364         if (target_rate > low)
 365                 return high;
 366         else
 367                 return low;
 368 #endif
 369
 370 }
 371
 372 static void omap2_dpllcore_recalc(struct clk *clk)
 373 {
 374         clk->rate = omap2_get_dpll_rate_24xx(clk);
 375 }
 376
 377 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 378 {
 379         u32 cur_rate, low, mult, div, valid_rate, done_rate;
 380         u32 bypass = 0;
 381         struct prcm_config tmpset;
 382         const struct dpll_data *dd;
 383         unsigned long flags;
 384         int ret = -EINVAL;
 385
 386         local_irq_save(flags);
 387         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 388         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 389         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 390
 391         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 392                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 393         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 394                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 395         } else if (rate != cur_rate) {
 396                 valid_rate = omap2_dpllcore_round_rate(rate);
 397                 if (valid_rate != rate)
 398                         goto dpll_exit;
 399
 400                 if (mult == 1)
 401                         low = curr_prcm_set->dpll_speed;
 402                 else
 403                         low = curr_prcm_set->dpll_speed / 2;
 404
 405                 dd = clk->dpll_data;
 406                 if (!dd)
 407                         goto dpll_exit;
 408
 409                 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
 410                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 411                                            dd->div1_mask);
 412                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 413                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 414                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 415                 if (rate > low) {
 416                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 417                         mult = ((rate / 2) / 1000000);
 418                         done_rate = CORE_CLK_SRC_DPLL_X2;
 419                 } else {
 420                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 421                         mult = (rate / 1000000);
 422                         done_rate = CORE_CLK_SRC_DPLL;
 423                 }
 424                 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
 425                 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
 426
 427                 /* Worst case */
 428                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 429
 430                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 431                         bypass = 1;
 432
 433                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 434
 435                 /* Force dll lock mode */
 436                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 437                                bypass);
 438
 439                 /* Errata: ret dll entry state */
 440                 omap2_init_memory_params(omap2_dll_force_needed());
 441                 omap2_reprogram_sdrc(done_rate, 0);
 442         }
 443         omap2_dpllcore_recalc(&dpll_ck);
 444         ret = 0;
 445
 446 dpll_exit:
 447         local_irq_restore(flags);
 448         return(ret);
 449 }
 450
 451 /**
 452  * omap2_table_mpu_recalc - just return the MPU speed
 453  * @clk: virt_prcm_set struct clk
 454  *
 455  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 456  */
 457 static void omap2_table_mpu_recalc(struct clk *clk)
 458 {
 459         clk->rate = curr_prcm_set->mpu_speed;
 460 }
 461
 462 /*
 463  * Look for a rate equal or less than the target rate given a configuration set.
 464  *
 465  * What's not entirely clear is "which" field represents the key field.
 466  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 467  * just uses the ARM rates.
 468  */
 469 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 470 {
 471         struct prcm_config *ptr;
 472         long highest_rate;
 473
 474         if (clk != &virt_prcm_set)
 475                 return -EINVAL;
 476
 477         highest_rate = -EINVAL;
 478
 479         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 480                 if (!(ptr->flags & cpu_mask))
 481                         continue;
 482                 if (ptr->xtal_speed != sys_ck.rate)
 483                         continue;
 484
 485                 highest_rate = ptr->mpu_speed;
 486
 487                 /* Can check only after xtal frequency check */
 488                 if (ptr->mpu_speed <= rate)
 489                         break;
 490         }
 491         return highest_rate;
 492 }
 493
 494 /* Sets basic clocks based on the specified rate */
 495 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 496 {
 497         u32 cur_rate, done_rate, bypass = 0, tmp;
 498         struct prcm_config *prcm;
 499         unsigned long found_speed = 0;
 500         unsigned long flags;
 501
 502         if (clk != &virt_prcm_set)
 503                 return -EINVAL;
 504
 505         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 506                 if (!(prcm->flags & cpu_mask))
 507                         continue;
 508
 509                 if (prcm->xtal_speed != sys_ck.rate)
 510                         continue;
 511
 512                 if (prcm->mpu_speed <= rate) {
 513                         found_speed = prcm->mpu_speed;
 514                         break;
 515                 }
 516         }
 517
 518         if (!found_speed) {
 519                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 520                        rate / 1000000);
 521                 return -EINVAL;
 522         }
 523
 524         curr_prcm_set = prcm;
 525         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 526
 527         if (prcm->dpll_speed == cur_rate / 2) {
 528                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 529         } else if (prcm->dpll_speed == cur_rate * 2) {
 530                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 531         } else if (prcm->dpll_speed != cur_rate) {
 532                 local_irq_save(flags);
 533
 534                 if (prcm->dpll_speed == prcm->xtal_speed)
 535                         bypass = 1;
 536
 537                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 538                     CORE_CLK_SRC_DPLL_X2)
 539                         done_rate = CORE_CLK_SRC_DPLL_X2;
 540                 else
 541                         done_rate = CORE_CLK_SRC_DPLL;
 542
 543                 /* MPU divider */
 544                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 545
 546                 /* dsp + iva1 div(2420), iva2.1(2430) */
 547                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 548                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 549
 550                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 551
 552                 /* Major subsystem dividers */
 553                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 554                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
 555                                  CM_CLKSEL1);
 556
 557                 if (cpu_is_omap2430())
 558                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 559                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 560
 561                 /* x2 to enter init_mem */
 562                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 563
 564                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 565                                bypass);
 566
 567                 omap2_init_memory_params(omap2_dll_force_needed());
 568                 omap2_reprogram_sdrc(done_rate, 0);
 569
 570                 local_irq_restore(flags);
 571         }
 572         omap2_dpllcore_recalc(&dpll_ck);
 573
 574         return 0;
 575 }
 576
 577 static struct clk_functions omap2_clk_functions = {
 578         .clk_enable             = omap2_clk_enable,
 579         .clk_disable            = omap2_clk_disable,
 580         .clk_round_rate         = omap2_clk_round_rate,
 581         .clk_set_rate           = omap2_clk_set_rate,
 582         .clk_set_parent         = omap2_clk_set_parent,
 583         .clk_disable_unused     = omap2_clk_disable_unused,
 584 };
 585
 586 static u32 omap2_get_apll_clkin(void)
 587 {
 588         u32 aplls, srate = 0;
 589
 590         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 591         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 592         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 593
 594         if (aplls == APLLS_CLKIN_19_2MHZ)
 595                 srate = 19200000;
 596         else if (aplls == APLLS_CLKIN_13MHZ)
 597                 srate = 13000000;
 598         else if (aplls == APLLS_CLKIN_12MHZ)
 599                 srate = 12000000;
 600
 601         return srate;
 602 }
 603
 604 static u32 omap2_get_sysclkdiv(void)
 605 {
 606         u32 div;
 607
 608         div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 609         div &= OMAP_SYSCLKDIV_MASK;
 610         div >>= OMAP_SYSCLKDIV_SHIFT;
 611
 612         return div;
 613 }
 614
 615 static void omap2_osc_clk_recalc(struct clk *clk)
 616 {
 617         clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 618 }
 619
 620 static void omap2_sys_clk_recalc(struct clk *clk)
 621 {
 622         clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
 623 }
 624
 625 /*
 626  * Set clocks for bypass mode for reboot to work.
 627  */
 628 void omap2_clk_prepare_for_reboot(void)
 629 {
 630         u32 rate;
 631
 632         if (vclk == NULL || sclk == NULL)
 633                 return;
 634
 635         rate = clk_get_rate(sclk);
 636         clk_set_rate(vclk, rate);
 637 }
 638
 639 /*
 640  * Switch the MPU rate if specified on cmdline.
 641  * We cannot do this early until cmdline is parsed.
 642  */
 643 static int __init omap2_clk_arch_init(void)
 644 {
 645         if (!mpurate)
 646                 return -EINVAL;
 647
 648         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 649                 printk(KERN_ERR "Could not find matching MPU rate\n");
 650
 651         recalculate_root_clocks();
 652
 653         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 654                "%ld.%01ld/%ld/%ld MHz\n",
 655                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 656                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 657
 658         return 0;
 659 }
 660 arch_initcall(omap2_clk_arch_init);
 661
 662 int __init omap2_clk_init(void)
 663 {
 664         struct prcm_config *prcm;
 665         struct omap_clk *c;
 666         u32 clkrate, cpu_mask;
 667
 668         if (cpu_is_omap242x())
 669                 cpu_mask = RATE_IN_242X;
 670         else if (cpu_is_omap2430())
 671                 cpu_mask = RATE_IN_243X;
 672
 673         clk_init(&omap2_clk_functions);
 674
 675         omap2_osc_clk_recalc(&osc_ck);
 676         propagate_rate(&osc_ck);
 677         omap2_sys_clk_recalc(&sys_ck);
 678         propagate_rate(&sys_ck);
 679
 680         cpu_mask = 0;
 681         if (cpu_is_omap2420())
 682                 cpu_mask |= CK_242X;
 683         if (cpu_is_omap2430())
 684                 cpu_mask |= CK_243X;
 685
 686         for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
 687                 if (c->cpu & cpu_mask) {
 688                         clkdev_add(&c->lk);
 689                         clk_register(c->lk.clk);
 690                 }
 691
 692         /* Check the MPU rate set by bootloader */
 693         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 694         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 695                 if (!(prcm->flags & cpu_mask))
 696                         continue;
 697                 if (prcm->xtal_speed != sys_ck.rate)
 698                         continue;
 699                 if (prcm->dpll_speed <= clkrate)
 700                          break;
 701         }
 702         curr_prcm_set = prcm;
 703
 704         recalculate_root_clocks();
 705
 706         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 707                "%ld.%01ld/%ld/%ld MHz\n",
 708                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 709                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 710
 711         /*
 712          * Only enable those clocks we will need, let the drivers
 713          * enable other clocks as necessary
 714          */
 715         clk_enable_init_clocks();
 716
 717         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 718         vclk = clk_get(NULL, "virt_prcm_set");
 719         sclk = clk_get(NULL, "sys_ck");
 720
 721         return 0;
 722 }