arch/arm/mach-omap1/serial.c

   1 /*
   2  * linux/arch/arm/mach-omap1/serial.c
   3  *
   4  * OMAP1 serial support.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/serial.h>
  17 #include <linux/tty.h>
  18 #include <linux/serial_8250.h>
  19 #include <linux/serial_reg.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/mach-types.h>
  24
  25 #include <mach/board.h>
  26 #include <mach/mux.h>
  27 #include <mach/gpio.h>
  28 #include <mach/fpga.h>
  29
  30 static struct clk * uart1_ck;
  31 static struct clk * uart2_ck;
  32 static struct clk * uart3_ck;
  33
  34 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
  35                                           int offset)
  36 {
  37         offset <<= up->regshift;
  38         return (unsigned int)__raw_readb(up->membase + offset);
  39 }
  40
  41 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
  42                                     int value)
  43 {
  44         offset <<= p->regshift;
  45         __raw_writeb(value, p->membase + offset);
  46 }
  47
  48 /*
  49  * Internal UARTs need to be initialized for the 8250 autoconfig to work
  50  * properly. Note that the TX watermark initialization may not be needed
  51  * once the 8250.c watermark handling code is merged.
  52  */
  53 static void __init omap_serial_reset(struct plat_serial8250_port *p)
  54 {
  55         omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
  56         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
  57         omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
  58
  59         if (!cpu_is_omap15xx()) {
  60                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
  61                 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
  62         }
  63 }
  64
  65 static struct plat_serial8250_port serial_platform_data[] = {
  66         {
  67                 .membase        = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
  68                 .mapbase        = OMAP_UART1_BASE,
  69                 .irq            = INT_UART1,
  70                 .flags          = UPF_BOOT_AUTOCONF,
  71                 .iotype         = UPIO_MEM,
  72                 .regshift       = 2,
  73                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  74         },
  75         {
  76                 .membase        = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
  77                 .mapbase        = OMAP_UART2_BASE,
  78                 .irq            = INT_UART2,
  79                 .flags          = UPF_BOOT_AUTOCONF,
  80                 .iotype         = UPIO_MEM,
  81                 .regshift       = 2,
  82                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  83         },
  84         {
  85                 .membase        = OMAP1_IO_ADDRESS(OMAP_UART3_BASE),
  86                 .mapbase        = OMAP_UART3_BASE,
  87                 .irq            = INT_UART3,
  88                 .flags          = UPF_BOOT_AUTOCONF,
  89                 .iotype         = UPIO_MEM,
  90                 .regshift       = 2,
  91                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  92         },
  93         { },
  94 };
  95
  96 static struct platform_device serial_device = {
  97         .name                   = "serial8250",
  98         .id                     = PLAT8250_DEV_PLATFORM,
  99         .dev                    = {
 100                 .platform_data  = serial_platform_data,
 101         },
 102 };
 103
 104 /*
 105  * Note that on Innovator-1510 UART2 pins conflict with USB2.
 106  * By default UART2 does not work on Innovator-1510 if you have
 107  * USB OHCI enabled. To use UART2, you must disable USB2 first.
 108  */
 109 void __init omap_serial_init(void)
 110 {
 111         int i;
 112
 113         if (cpu_is_omap730()) {
 114                 serial_platform_data[0].regshift = 0;
 115                 serial_platform_data[1].regshift = 0;
 116                 serial_platform_data[0].irq = INT_730_UART_MODEM_1;
 117                 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
 118         }
 119
 120         if (cpu_is_omap850()) {
 121                 serial_platform_data[0].regshift = 0;
 122                 serial_platform_data[1].regshift = 0;
 123                 serial_platform_data[0].irq = INT_850_UART_MODEM_1;
 124                 serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
 125         }
 126
 127         if (cpu_is_omap15xx()) {
 128                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
 129                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
 130                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
 131         }
 132
 133         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
 134                 unsigned char reg;
 135
 136                 switch (i) {
 137                 case 0:
 138                         uart1_ck = clk_get(NULL, "uart1_ck");
 139                         if (IS_ERR(uart1_ck))
 140                                 printk("Could not get uart1_ck\n");
 141                         else {
 142                                 clk_enable(uart1_ck);
 143                                 if (cpu_is_omap15xx())
 144                                         clk_set_rate(uart1_ck, 12000000);
 145                         }
 146                         if (cpu_is_omap15xx()) {
 147                                 omap_cfg_reg(UART1_TX);
 148                                 omap_cfg_reg(UART1_RTS);
 149                                 if (machine_is_omap_innovator()) {
 150                                         reg = fpga_read(OMAP1510_FPGA_POWER);
 151                                         reg |= OMAP1510_FPGA_PCR_COM1_EN;
 152                                         fpga_write(reg, OMAP1510_FPGA_POWER);
 153                                         udelay(10);
 154                                 }
 155                         }
 156                         break;
 157                 case 1:
 158                         uart2_ck = clk_get(NULL, "uart2_ck");
 159                         if (IS_ERR(uart2_ck))
 160                                 printk("Could not get uart2_ck\n");
 161                         else {
 162                                 clk_enable(uart2_ck);
 163                                 if (cpu_is_omap15xx())
 164                                         clk_set_rate(uart2_ck, 12000000);
 165                                 else
 166                                         clk_set_rate(uart2_ck, 48000000);
 167                         }
 168                         if (cpu_is_omap15xx()) {
 169                                 omap_cfg_reg(UART2_TX);
 170                                 omap_cfg_reg(UART2_RTS);
 171                                 if (machine_is_omap_innovator()) {
 172                                         reg = fpga_read(OMAP1510_FPGA_POWER);
 173                                         reg |= OMAP1510_FPGA_PCR_COM2_EN;
 174                                         fpga_write(reg, OMAP1510_FPGA_POWER);
 175                                         udelay(10);
 176                                 }
 177                         }
 178                         break;
 179                 case 2:
 180                         uart3_ck = clk_get(NULL, "uart3_ck");
 181                         if (IS_ERR(uart3_ck))
 182                                 printk("Could not get uart3_ck\n");
 183                         else {
 184                                 clk_enable(uart3_ck);
 185                                 if (cpu_is_omap15xx())
 186                                         clk_set_rate(uart3_ck, 12000000);
 187                         }
 188                         if (cpu_is_omap15xx()) {
 189                                 omap_cfg_reg(UART3_TX);
 190                                 omap_cfg_reg(UART3_RX);
 191                         }
 192                         break;
 193                 }
 194                 omap_serial_reset(&serial_platform_data[i]);
 195         }
 196 }
 197
 198 #ifdef CONFIG_OMAP_SERIAL_WAKE
 199
 200 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
 201 {
 202         /* Need to do something with serial port right after wake-up? */
 203         return IRQ_HANDLED;
 204 }
 205
 206 /*
 207  * Reroutes serial RX lines to GPIO lines for the duration of
 208  * sleep to allow waking up the device from serial port even
 209  * in deep sleep.
 210  */
 211 void omap_serial_wake_trigger(int enable)
 212 {
 213         if (!cpu_is_omap16xx())
 214                 return;
 215
 216         if (uart1_ck != NULL) {
 217                 if (enable)
 218                         omap_cfg_reg(V14_16XX_GPIO37);
 219                 else
 220                         omap_cfg_reg(V14_16XX_UART1_RX);
 221         }
 222         if (uart2_ck != NULL) {
 223                 if (enable)
 224                         omap_cfg_reg(R9_16XX_GPIO18);
 225                 else
 226                         omap_cfg_reg(R9_16XX_UART2_RX);
 227         }
 228         if (uart3_ck != NULL) {
 229                 if (enable)
 230                         omap_cfg_reg(L14_16XX_GPIO49);
 231                 else
 232                         omap_cfg_reg(L14_16XX_UART3_RX);
 233         }
 234 }
 235
 236 static void __init omap_serial_set_port_wakeup(int gpio_nr)
 237 {
 238         int ret;
 239
 240         ret = gpio_request(gpio_nr, "UART wake");
 241         if (ret < 0) {
 242                 printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
 243                        gpio_nr);
 244                 return;
 245         }
 246         gpio_direction_input(gpio_nr);
 247         ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt,
 248                           IRQF_TRIGGER_RISING, "serial wakeup", NULL);
 249         if (ret) {
 250                 gpio_free(gpio_nr);
 251                 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
 252                        gpio_nr);
 253                 return;
 254         }
 255         enable_irq_wake(gpio_to_irq(gpio_nr));
 256 }
 257
 258 static int __init omap_serial_wakeup_init(void)
 259 {
 260         if (!cpu_is_omap16xx())
 261                 return 0;
 262
 263         if (uart1_ck != NULL)
 264                 omap_serial_set_port_wakeup(37);
 265         if (uart2_ck != NULL)
 266                 omap_serial_set_port_wakeup(18);
 267         if (uart3_ck != NULL)
 268                 omap_serial_set_port_wakeup(49);
 269
 270         return 0;
 271 }
 272 late_initcall(omap_serial_wakeup_init);
 273
 274 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
 275
 276 static int __init omap_init(void)
 277 {
 278         return platform_device_register(&serial_device);
 279 }
 280 arch_initcall(omap_init);