arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/atomic.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/cpu.h>
  54 #include <asm/arch/irqs.h>
  55 #include <asm/arch/clock.h>
  56 #include <asm/arch/sram.h>
  57 #include <asm/arch/tc.h>
  58 #include <asm/arch/pm.h>
  59 #include <asm/arch/mux.h>
  60 #include <asm/arch/dma.h>
  61 #include <asm/arch/dsp_common.h>
  62 #include <asm/arch/dmtimer.h>
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  66 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  69 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  70
  71 static unsigned short enable_dyn_sleep = 1;
  72
  73 static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf)
  74 {
  75         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  76 }
  77
  78 static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset,
  79                                               const char * buf,
  80                                               size_t n)
  81 {
  82         unsigned short value;
  83         if (sscanf(buf, "%hu", &value) != 1 ||
  84             (value != 0 && value != 1)) {
  85                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  86                 return -EINVAL;
  87         }
  88         enable_dyn_sleep = value;
  89         return n;
  90 }
  91
  92 static struct subsys_attribute sleep_while_idle_attr = {
  93         .attr   = {
  94                 .name = __stringify(sleep_while_idle),
  95                 .mode = 0644,
  96         },
  97         .show   = omap_pm_sleep_while_idle_show,
  98         .store  = omap_pm_sleep_while_idle_store,
  99 };
 100
 101 extern struct kset power_subsys;
 102 static void (*omap_sram_idle)(void) = NULL;
 103 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 104
 105 /*
 106  * Let's power down on idle, but only if we are really
 107  * idle, because once we start down the path of
 108  * going idle we continue to do idle even if we get
 109  * a clock tick interrupt . .
 110  */
 111 void omap_pm_idle(void)
 112 {
 113         extern __u32 arm_idlect1_mask;
 114         __u32 use_idlect1 = arm_idlect1_mask;
 115 #ifndef CONFIG_OMAP_MPU_TIMER
 116         int do_sleep;
 117 #endif
 118
 119         local_irq_disable();
 120         local_fiq_disable();
 121         if (need_resched()) {
 122                 local_fiq_enable();
 123                 local_irq_enable();
 124                 return;
 125         }
 126
 127         /*
 128          * Since an interrupt may set up a timer, we don't want to
 129          * reprogram the hardware timer with interrupts enabled.
 130          * Re-enable interrupts only after returning from idle.
 131          */
 132         timer_dyn_reprogram();
 133
 134 #ifdef CONFIG_OMAP_MPU_TIMER
 135 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 136         use_idlect1 = use_idlect1 & ~(1 << 9);
 137 #else
 138
 139         do_sleep = 0;
 140         while (enable_dyn_sleep) {
 141
 142 #ifdef CONFIG_CBUS_TAHVO_USB
 143                 extern int vbus_active;
 144                 /* Clock requirements? */
 145                 if (vbus_active)
 146                         break;
 147 #endif
 148                 do_sleep = 1;
 149                 break;
 150         }
 151
 152 #ifdef CONFIG_OMAP_DM_TIMER
 153         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 154 #endif
 155
 156         if (omap_dma_running())
 157                 use_idlect1 &= ~(1 << 6);
 158
 159         /* We should be able to remove the do_sleep variable and multiple
 160          * tests above as soon as drivers, timer and DMA code have been fixed.
 161          * Even the sleep block count should become obsolete. */
 162         if ((use_idlect1 != ~0) || !do_sleep) {
 163
 164                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 165                 if (cpu_is_omap15xx())
 166                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 167                 else
 168                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 169                 omap_writel(use_idlect1, ARM_IDLECT1);
 170                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 171                 omap_writel(saved_idlect1, ARM_IDLECT1);
 172
 173                 local_fiq_enable();
 174                 local_irq_enable();
 175                 return;
 176         }
 177         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 178                           omap_readl(ARM_IDLECT2));
 179 #endif
 180
 181         local_fiq_enable();
 182         local_irq_enable();
 183 }
 184
 185 /*
 186  * Configuration of the wakeup event is board specific. For the
 187  * moment we put it into this helper function. Later it may move
 188  * to board specific files.
 189  */
 190 static void omap_pm_wakeup_setup(void)
 191 {
 192         u32 level1_wake = 0;
 193         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 194
 195         /*
 196          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 197          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 198          * drivers must still separately call omap_set_gpio_wakeup() to
 199          * wake up to a GPIO interrupt.
 200          */
 201         if (cpu_is_omap730())
 202                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 203                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 204         else if (cpu_is_omap15xx())
 205                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 206                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 207         else if (cpu_is_omap16xx())
 208                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 209                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 210
 211         omap_writel(~level1_wake, OMAP_IH1_MIR);
 212
 213         if (cpu_is_omap730()) {
 214                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 215                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 216                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 217                                 OMAP_IH2_1_MIR);
 218         } else if (cpu_is_omap15xx()) {
 219                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 220                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 221         } else if (cpu_is_omap16xx()) {
 222                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 223                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 224
 225                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 226                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 227                             OMAP_IH2_1_MIR);
 228                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 229                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 230         }
 231
 232         /*  New IRQ agreement, recalculate in cascade order */
 233         omap_writel(1, OMAP_IH2_CONTROL);
 234         omap_writel(1, OMAP_IH1_CONTROL);
 235 }
 236
 237 #define EN_DSPCK        13      /* ARM_CKCTL */
 238 #define EN_APICK        6       /* ARM_IDLECT2 */
 239 #define DSP_EN          1       /* ARM_RSTCT1 */
 240
 241 void omap_pm_suspend(void)
 242 {
 243         unsigned long arg0 = 0, arg1 = 0;
 244
 245         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 246
 247         omap_serial_wake_trigger(1);
 248
 249         if (!cpu_is_omap15xx())
 250                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 251
 252         /*
 253          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 254          */
 255
 256         local_irq_disable();
 257         local_fiq_disable();
 258
 259         /*
 260          * Step 2: save registers
 261          *
 262          * The omap is a strange/beautiful device. The caches, memory
 263          * and register state are preserved across power saves.
 264          * We have to save and restore very little register state to
 265          * idle the omap.
 266          *
 267          * Save interrupt, MPUI, ARM and UPLD control registers.
 268          */
 269
 270         if (cpu_is_omap730()) {
 271                 MPUI730_SAVE(OMAP_IH1_MIR);
 272                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 273                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 274                 MPUI730_SAVE(MPUI_CTRL);
 275                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 276                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 277                 MPUI730_SAVE(EMIFS_CONFIG);
 278                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 279
 280         } else if (cpu_is_omap15xx()) {
 281                 MPUI1510_SAVE(OMAP_IH1_MIR);
 282                 MPUI1510_SAVE(OMAP_IH2_MIR);
 283                 MPUI1510_SAVE(MPUI_CTRL);
 284                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 285                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 286                 MPUI1510_SAVE(EMIFS_CONFIG);
 287                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 288         } else if (cpu_is_omap16xx()) {
 289                 MPUI1610_SAVE(OMAP_IH1_MIR);
 290                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 291                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 292                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 293                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 294                 MPUI1610_SAVE(MPUI_CTRL);
 295                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 296                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 297                 MPUI1610_SAVE(EMIFS_CONFIG);
 298                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 299         }
 300
 301         ARM_SAVE(ARM_CKCTL);
 302         ARM_SAVE(ARM_IDLECT1);
 303         ARM_SAVE(ARM_IDLECT2);
 304         if (!(cpu_is_omap15xx()))
 305                 ARM_SAVE(ARM_IDLECT3);
 306         ARM_SAVE(ARM_EWUPCT);
 307         ARM_SAVE(ARM_RSTCT1);
 308         ARM_SAVE(ARM_RSTCT2);
 309         ARM_SAVE(ARM_SYSST);
 310         ULPD_SAVE(ULPD_CLOCK_CTRL);
 311         ULPD_SAVE(ULPD_STATUS_REQ);
 312
 313         /* (Step 3 removed - we now allow deep sleep by default) */
 314
 315         /*
 316          * Step 4: OMAP DSP Shutdown
 317          */
 318
 319         /* stop DSP */
 320         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 321
 322                 /* shut down dsp_ck */
 323         if (!cpu_is_omap730())
 324                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 325
 326         /* temporarily enabling api_ck to access DSP registers */
 327         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 328
 329         /* save DSP registers */
 330         DSP_SAVE(DSP_IDLECT2);
 331
 332         /* Stop all DSP domain clocks */
 333         __raw_writew(0, DSP_IDLECT2);
 334
 335         /*
 336          * Step 5: Wakeup Event Setup
 337          */
 338
 339         omap_pm_wakeup_setup();
 340
 341         /*
 342          * Step 6: ARM and Traffic controller shutdown
 343          */
 344
 345         /* disable ARM watchdog */
 346         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 347         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 348
 349         /*
 350          * Step 6b: ARM and Traffic controller shutdown
 351          *
 352          * Step 6 continues here. Prepare jump to power management
 353          * assembly code in internal SRAM.
 354          *
 355          * Since the omap_cpu_suspend routine has been copied to
 356          * SRAM, we'll do an indirect procedure call to it and pass the
 357          * contents of arm_idlect1 and arm_idlect2 so it can restore
 358          * them when it wakes up and it will return.
 359          */
 360
 361         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 362         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 363
 364         /*
 365          * Step 6c: ARM and Traffic controller shutdown
 366          *
 367          * Jump to assembly code. The processor will stay there
 368          * until wake up.
 369          */
 370         omap_sram_suspend(arg0, arg1);
 371
 372         /*
 373          * If we are here, processor is woken up!
 374          */
 375
 376         /*
 377          * Restore DSP clocks
 378          */
 379
 380         /* again temporarily enabling api_ck to access DSP registers */
 381         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 382
 383         /* Restore DSP domain clocks */
 384         DSP_RESTORE(DSP_IDLECT2);
 385
 386         /*
 387          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 388          */
 389
 390         if (!(cpu_is_omap15xx()))
 391                 ARM_RESTORE(ARM_IDLECT3);
 392         ARM_RESTORE(ARM_CKCTL);
 393         ARM_RESTORE(ARM_EWUPCT);
 394         ARM_RESTORE(ARM_RSTCT1);
 395         ARM_RESTORE(ARM_RSTCT2);
 396         ARM_RESTORE(ARM_SYSST);
 397         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 398         ULPD_RESTORE(ULPD_STATUS_REQ);
 399
 400         if (cpu_is_omap730()) {
 401                 MPUI730_RESTORE(EMIFS_CONFIG);
 402                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 403                 MPUI730_RESTORE(OMAP_IH1_MIR);
 404                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 405                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 406         } else if (cpu_is_omap15xx()) {
 407                 MPUI1510_RESTORE(MPUI_CTRL);
 408                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 409                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 410                 MPUI1510_RESTORE(EMIFS_CONFIG);
 411                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 412                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 413                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 414         } else if (cpu_is_omap16xx()) {
 415                 MPUI1610_RESTORE(MPUI_CTRL);
 416                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 417                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 418                 MPUI1610_RESTORE(EMIFS_CONFIG);
 419                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 420
 421                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 422                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 423                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 424                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 425                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 426         }
 427
 428         if (!cpu_is_omap15xx())
 429                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 430
 431         /*
 432          * Re-enable interrupts
 433          */
 434
 435         local_irq_enable();
 436         local_fiq_enable();
 437
 438         omap_serial_wake_trigger(0);
 439
 440         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 441 }
 442
 443 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 444 static int g_read_completed;
 445
 446 /*
 447  * Read system PM registers for debugging
 448  */
 449 static int omap_pm_read_proc(
 450         char *page_buffer,
 451         char **my_first_byte,
 452         off_t virtual_start,
 453         int length,
 454         int *eof,
 455         void *data)
 456 {
 457         int my_buffer_offset = 0;
 458         char * const my_base = page_buffer;
 459
 460         ARM_SAVE(ARM_CKCTL);
 461         ARM_SAVE(ARM_IDLECT1);
 462         ARM_SAVE(ARM_IDLECT2);
 463         if (!(cpu_is_omap15xx()))
 464                 ARM_SAVE(ARM_IDLECT3);
 465         ARM_SAVE(ARM_EWUPCT);
 466         ARM_SAVE(ARM_RSTCT1);
 467         ARM_SAVE(ARM_RSTCT2);
 468         ARM_SAVE(ARM_SYSST);
 469
 470         ULPD_SAVE(ULPD_IT_STATUS);
 471         ULPD_SAVE(ULPD_CLOCK_CTRL);
 472         ULPD_SAVE(ULPD_SOFT_REQ);
 473         ULPD_SAVE(ULPD_STATUS_REQ);
 474         ULPD_SAVE(ULPD_DPLL_CTRL);
 475         ULPD_SAVE(ULPD_POWER_CTRL);
 476
 477         if (cpu_is_omap730()) {
 478                 MPUI730_SAVE(MPUI_CTRL);
 479                 MPUI730_SAVE(MPUI_DSP_STATUS);
 480                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 481                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 482                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 483                 MPUI730_SAVE(EMIFS_CONFIG);
 484         } else if (cpu_is_omap15xx()) {
 485                 MPUI1510_SAVE(MPUI_CTRL);
 486                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 487                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 488                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 489                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 490                 MPUI1510_SAVE(EMIFS_CONFIG);
 491         } else if (cpu_is_omap16xx()) {
 492                 MPUI1610_SAVE(MPUI_CTRL);
 493                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 494                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 495                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 496                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 497                 MPUI1610_SAVE(EMIFS_CONFIG);
 498         }
 499
 500         if (virtual_start == 0) {
 501                 g_read_completed = 0;
 502
 503                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 504                    "ARM_CKCTL_REG:            0x%-8x     \n"
 505                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 506                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 507                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 508                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 509                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 510                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 511                    "ARM_SYSST_REG:            0x%-8x     \n"
 512                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 513                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 514                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 515                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 516                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 517                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 518                    ARM_SHOW(ARM_CKCTL),
 519                    ARM_SHOW(ARM_IDLECT1),
 520                    ARM_SHOW(ARM_IDLECT2),
 521                    ARM_SHOW(ARM_IDLECT3),
 522                    ARM_SHOW(ARM_EWUPCT),
 523                    ARM_SHOW(ARM_RSTCT1),
 524                    ARM_SHOW(ARM_RSTCT2),
 525                    ARM_SHOW(ARM_SYSST),
 526                    ULPD_SHOW(ULPD_IT_STATUS),
 527                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 528                    ULPD_SHOW(ULPD_SOFT_REQ),
 529                    ULPD_SHOW(ULPD_DPLL_CTRL),
 530                    ULPD_SHOW(ULPD_STATUS_REQ),
 531                    ULPD_SHOW(ULPD_POWER_CTRL));
 532
 533                 if (cpu_is_omap730()) {
 534                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 535                            "MPUI730_CTRL_REG         0x%-8x \n"
 536                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 537                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 538                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 539                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 540                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 541                            MPUI730_SHOW(MPUI_CTRL),
 542                            MPUI730_SHOW(MPUI_DSP_STATUS),
 543                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 544                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 545                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 546                            MPUI730_SHOW(EMIFS_CONFIG));
 547                 } else if (cpu_is_omap15xx()) {
 548                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 549                            "MPUI1510_CTRL_REG             0x%-8x \n"
 550                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 551                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 552                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 553                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 554                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 555                            MPUI1510_SHOW(MPUI_CTRL),
 556                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 557                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 558                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 559                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 560                            MPUI1510_SHOW(EMIFS_CONFIG));
 561                 } else if (cpu_is_omap16xx()) {
 562                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 563                            "MPUI1610_CTRL_REG             0x%-8x \n"
 564                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 565                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 566                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 567                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 568                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 569                            MPUI1610_SHOW(MPUI_CTRL),
 570                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 571                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 572                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 573                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 574                            MPUI1610_SHOW(EMIFS_CONFIG));
 575                 }
 576
 577                 g_read_completed++;
 578         } else if (g_read_completed >= 1) {
 579                  *eof = 1;
 580                  return 0;
 581         }
 582         g_read_completed++;
 583
 584         *my_first_byte = page_buffer;
 585         return  my_buffer_offset;
 586 }
 587
 588 static void omap_pm_init_proc(void)
 589 {
 590         struct proc_dir_entry *entry;
 591
 592         entry = create_proc_read_entry("driver/omap_pm",
 593                                        S_IWUSR | S_IRUGO, NULL,
 594                                        omap_pm_read_proc, NULL);
 595 }
 596
 597 #endif /* DEBUG && CONFIG_PROC_FS */
 598
 599 static void (*saved_idle)(void) = NULL;
 600
 601 /*
 602  *      omap_pm_prepare - Do preliminary suspend work.
 603  *      @state:         suspend state we're entering.
 604  *
 605  */
 606 static int omap_pm_prepare(suspend_state_t state)
 607 {
 608         int error = 0;
 609
 610         /* We cannot sleep in idle until we have resumed */
 611         saved_idle = pm_idle;
 612         pm_idle = NULL;
 613
 614         switch (state)
 615         {
 616         case PM_SUSPEND_STANDBY:
 617         case PM_SUSPEND_MEM:
 618                 break;
 619         default:
 620                 return -EINVAL;
 621         }
 622
 623         return error;
 624 }
 625
 626
 627 /*
 628  *      omap_pm_enter - Actually enter a sleep state.
 629  *      @state:         State we're entering.
 630  *
 631  */
 632
 633 static int omap_pm_enter(suspend_state_t state)
 634 {
 635         switch (state)
 636         {
 637         case PM_SUSPEND_STANDBY:
 638         case PM_SUSPEND_MEM:
 639                 omap_pm_suspend();
 640                 break;
 641         default:
 642                 return -EINVAL;
 643         }
 644
 645         return 0;
 646 }
 647
 648
 649 /**
 650  *      omap_pm_finish - Finish up suspend sequence.
 651  *      @state:         State we're coming out of.
 652  *
 653  *      This is called after we wake back up (or if entering the sleep state
 654  *      failed).
 655  */
 656
 657 static int omap_pm_finish(suspend_state_t state)
 658 {
 659         pm_idle = saved_idle;
 660         return 0;
 661 }
 662
 663
 664 static irqreturn_t  omap_wakeup_interrupt(int irq, void *dev)
 665 {
 666         return IRQ_HANDLED;
 667 }
 668
 669 static struct irqaction omap_wakeup_irq = {
 670         .name           = "peripheral wakeup",
 671         .flags          = IRQF_DISABLED,
 672         .handler        = omap_wakeup_interrupt
 673 };
 674
 675
 676
 677 static struct pm_ops omap_pm_ops ={
 678         .prepare        = omap_pm_prepare,
 679         .enter          = omap_pm_enter,
 680         .finish         = omap_pm_finish,
 681         .valid          = pm_valid_only_mem,
 682 };
 683
 684 static int __init omap_pm_init(void)
 685 {
 686         int error;
 687
 688         printk("Power Management for TI OMAP.\n");
 689
 690         /*
 691          * We copy the assembler sleep/wakeup routines to SRAM.
 692          * These routines need to be in SRAM as that's the only
 693          * memory the MPU can see when it wakes up.
 694          */
 695         if (cpu_is_omap730()) {
 696                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 697                                                 omap730_idle_loop_suspend_sz);
 698                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 699                                                    omap730_cpu_suspend_sz);
 700         } else if (cpu_is_omap15xx()) {
 701                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 702                                                 omap1510_idle_loop_suspend_sz);
 703                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 704                                                    omap1510_cpu_suspend_sz);
 705         } else if (cpu_is_omap16xx()) {
 706                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 707                                                 omap1610_idle_loop_suspend_sz);
 708                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 709                                                    omap1610_cpu_suspend_sz);
 710         }
 711
 712         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 713                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 714                 return -ENODEV;
 715         }
 716
 717         pm_idle = omap_pm_idle;
 718
 719         if (cpu_is_omap730())
 720                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 721         else if (cpu_is_omap16xx())
 722                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 723
 724         /* Program new power ramp-up time
 725          * (0 for most boards since we don't lower voltage when in deep sleep)
 726          */
 727         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 728
 729         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 730         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 731
 732         /* Configure IDLECT3 */
 733         if (cpu_is_omap730())
 734                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 735         else if (cpu_is_omap16xx())
 736                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 737
 738         pm_set_ops(&omap_pm_ops);
 739
 740 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 741         omap_pm_init_proc();
 742 #endif
 743
 744         error = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 745         if (error)
 746                 printk(KERN_ERR "subsys_create_file failed: %d\n", error);
 747
 748         if (cpu_is_omap16xx()) {
 749                 /* configure LOW_PWR pin */
 750                 omap_cfg_reg(T20_1610_LOW_PWR);
 751         }
 752
 753         return 0;
 754 }
 755 __initcall(omap_pm_init);