arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static void omap1_ckctl_recalc(struct clk * clk);
  17 static void omap1_watchdog_recalc(struct clk * clk);
  18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  19 static void omap1_sossi_recalc(struct clk *clk);
  20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
  21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  23 static void omap1_uart_recalc(struct clk * clk);
  24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  26 static void omap1_init_ext_clk(struct clk * clk);
  27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  29
  30 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
  31 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
  32
  33 struct mpu_rate {
  34         unsigned long           rate;
  35         unsigned long           xtal;
  36         unsigned long           pll_rate;
  37         __u16                   ckctl_val;
  38         __u16                   dpllctl_val;
  39 };
  40
  41 struct uart_clk {
  42         struct clk      clk;
  43         unsigned long   sysc_addr;
  44 };
  45
  46 /* Provide a method for preventing idling some ARM IDLECT clocks */
  47 struct arm_idlect1_clk {
  48         struct clk      clk;
  49         unsigned long   no_idle_count;
  50         __u8            idlect_shift;
  51 };
  52
  53 /* ARM_CKCTL bit shifts */
  54 #define CKCTL_PERDIV_OFFSET     0
  55 #define CKCTL_LCDDIV_OFFSET     2
  56 #define CKCTL_ARMDIV_OFFSET     4
  57 #define CKCTL_DSPDIV_OFFSET     6
  58 #define CKCTL_TCDIV_OFFSET      8
  59 #define CKCTL_DSPMMUDIV_OFFSET  10
  60 /*#define ARM_TIMXO             12*/
  61 #define EN_DSPCK                13
  62 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  63 /* DSP_CKCTL bit shifts */
  64 #define CKCTL_DSPPERDIV_OFFSET  0
  65
  66 /* ARM_IDLECT2 bit shifts */
  67 #define EN_WDTCK        0
  68 #define EN_XORPCK       1
  69 #define EN_PERCK        2
  70 #define EN_LCDCK        3
  71 #define EN_LBCK         4 /* Not on 1610/1710 */
  72 /*#define EN_HSABCK     5*/
  73 #define EN_APICK        6
  74 #define EN_TIMCK        7
  75 #define DMACK_REQ       8
  76 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  77 /*#define EN_LBFREECK   10*/
  78 #define EN_CKOUT_ARM    11
  79
  80 /* ARM_IDLECT3 bit shifts */
  81 #define EN_OCPI_CK      0
  82 #define EN_TC1_CK       2
  83 #define EN_TC2_CK       4
  84
  85 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  86 #define EN_DSPTIMCK     5
  87
  88 /* Various register defines for clock controls scattered around OMAP chip */
  89 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
  90 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  91 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  92 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  93 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  94 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
  95 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
  96 #define SOFT_REQ_REG            0xfffe0834
  97 #define SOFT_REQ_REG2           0xfffe0880
  98
  99 /*-------------------------------------------------------------------------
 100  * Omap1 MPU rate table
 101  *-------------------------------------------------------------------------*/
 102 static struct mpu_rate rate_table[] = {
 103         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 104          * NOTE: Comment order here is different from bits in CKCTL value:
 105          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 106          */
 107 #if defined(CONFIG_OMAP_ARM_216MHZ)
 108         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 109 #endif
 110 #if defined(CONFIG_OMAP_ARM_195MHZ)
 111         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 112 #endif
 113 #if defined(CONFIG_OMAP_ARM_192MHZ)
 114         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 115         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 116         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 117         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 118         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 119 #endif
 120 #if defined(CONFIG_OMAP_ARM_182MHZ)
 121         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 122 #endif
 123 #if defined(CONFIG_OMAP_ARM_168MHZ)
 124         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 125 #endif
 126 #if defined(CONFIG_OMAP_ARM_150MHZ)
 127         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 128 #endif
 129 #if defined(CONFIG_OMAP_ARM_120MHZ)
 130         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 131 #endif
 132 #if defined(CONFIG_OMAP_ARM_96MHZ)
 133         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 134 #endif
 135 #if defined(CONFIG_OMAP_ARM_60MHZ)
 136         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 137 #endif
 138 #if defined(CONFIG_OMAP_ARM_30MHZ)
 139         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 140 #endif
 141         { 0, 0, 0, 0, 0 },
 142 };
 143
 144 /*-------------------------------------------------------------------------
 145  * Omap1 clocks
 146  *-------------------------------------------------------------------------*/
 147
 148 static struct clk ck_ref = {
 149         .name           = "ck_ref",
 150         .ops            = &clkops_null,
 151         .rate           = 12000000,
 152         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 153                           CLOCK_IN_OMAP310,
 154 };
 155
 156 static struct clk ck_dpll1 = {
 157         .name           = "ck_dpll1",
 158         .ops            = &clkops_null,
 159         .parent         = &ck_ref,
 160         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 161                           CLOCK_IN_OMAP310 | RATE_PROPAGATES,
 162 };
 163
 164 static struct arm_idlect1_clk ck_dpll1out = {
 165         .clk = {
 166                 .name           = "ck_dpll1out",
 167                 .ops            = &clkops_generic,
 168                 .parent         = &ck_dpll1,
 169                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
 170                                   ENABLE_REG_32BIT | RATE_PROPAGATES,
 171                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 172                 .enable_bit     = EN_CKOUT_ARM,
 173                 .recalc         = &followparent_recalc,
 174         },
 175         .idlect_shift   = 12,
 176 };
 177
 178 static struct clk sossi_ck = {
 179         .name           = "ck_sossi",
 180         .ops            = &clkops_generic,
 181         .parent         = &ck_dpll1out.clk,
 182         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 183                           ENABLE_REG_32BIT,
 184         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_1,
 185         .enable_bit     = 16,
 186         .recalc         = &omap1_sossi_recalc,
 187         .set_rate       = &omap1_set_sossi_rate,
 188 };
 189
 190 static struct clk arm_ck = {
 191         .name           = "arm_ck",
 192         .ops            = &clkops_null,
 193         .parent         = &ck_dpll1,
 194         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 195                           CLOCK_IN_OMAP310 | RATE_PROPAGATES,
 196         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 197         .recalc         = &omap1_ckctl_recalc,
 198         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 199         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 200 };
 201
 202 static struct arm_idlect1_clk armper_ck = {
 203         .clk = {
 204                 .name           = "armper_ck",
 205                 .ops            = &clkops_generic,
 206                 .parent         = &ck_dpll1,
 207                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 208                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 209                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 210                 .enable_bit     = EN_PERCK,
 211                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 212                 .recalc         = &omap1_ckctl_recalc,
 213                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 214                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 215         },
 216         .idlect_shift   = 2,
 217 };
 218
 219 static struct clk arm_gpio_ck = {
 220         .name           = "arm_gpio_ck",
 221         .ops            = &clkops_generic,
 222         .parent         = &ck_dpll1,
 223         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 224         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 225         .enable_bit     = EN_GPIOCK,
 226         .recalc         = &followparent_recalc,
 227 };
 228
 229 static struct arm_idlect1_clk armxor_ck = {
 230         .clk = {
 231                 .name           = "armxor_ck",
 232                 .ops            = &clkops_generic,
 233                 .parent         = &ck_ref,
 234                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 235                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 236                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 237                 .enable_bit     = EN_XORPCK,
 238                 .recalc         = &followparent_recalc,
 239         },
 240         .idlect_shift   = 1,
 241 };
 242
 243 static struct arm_idlect1_clk armtim_ck = {
 244         .clk = {
 245                 .name           = "armtim_ck",
 246                 .ops            = &clkops_generic,
 247                 .parent         = &ck_ref,
 248                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 249                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 250                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 251                 .enable_bit     = EN_TIMCK,
 252                 .recalc         = &followparent_recalc,
 253         },
 254         .idlect_shift   = 9,
 255 };
 256
 257 static struct arm_idlect1_clk armwdt_ck = {
 258         .clk = {
 259                 .name           = "armwdt_ck",
 260                 .ops            = &clkops_generic,
 261                 .parent         = &ck_ref,
 262                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 263                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 264                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 265                 .enable_bit     = EN_WDTCK,
 266                 .recalc         = &omap1_watchdog_recalc,
 267         },
 268         .idlect_shift   = 0,
 269 };
 270
 271 static struct clk arminth_ck16xx = {
 272         .name           = "arminth_ck",
 273         .ops            = &clkops_null,
 274         .parent         = &arm_ck,
 275         .flags          = CLOCK_IN_OMAP16XX,
 276         .recalc         = &followparent_recalc,
 277         /* Note: On 16xx the frequency can be divided by 2 by programming
 278          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 279          *
 280          * 1510 version is in TC clocks.
 281          */
 282 };
 283
 284 static struct clk dsp_ck = {
 285         .name           = "dsp_ck",
 286         .ops            = &clkops_generic,
 287         .parent         = &ck_dpll1,
 288         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 289         .enable_reg     = (void __iomem *)ARM_CKCTL,
 290         .enable_bit     = EN_DSPCK,
 291         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 292         .recalc         = &omap1_ckctl_recalc,
 293         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 294         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 295 };
 296
 297 static struct clk dspmmu_ck = {
 298         .name           = "dspmmu_ck",
 299         .ops            = &clkops_null,
 300         .parent         = &ck_dpll1,
 301         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 302         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 303         .recalc         = &omap1_ckctl_recalc,
 304         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 305         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 306 };
 307
 308 static struct clk dspper_ck = {
 309         .name           = "dspper_ck",
 310         .ops            = &clkops_dspck,
 311         .parent         = &ck_dpll1,
 312         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 313                           VIRTUAL_IO_ADDRESS,
 314         .enable_reg     = DSP_IDLECT2,
 315         .enable_bit     = EN_PERCK,
 316         .rate_offset    = CKCTL_PERDIV_OFFSET,
 317         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 318         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 319         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 320 };
 321
 322 static struct clk dspxor_ck = {
 323         .name           = "dspxor_ck",
 324         .ops            = &clkops_dspck,
 325         .parent         = &ck_ref,
 326         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 327                           VIRTUAL_IO_ADDRESS,
 328         .enable_reg     = DSP_IDLECT2,
 329         .enable_bit     = EN_XORPCK,
 330         .recalc         = &followparent_recalc,
 331 };
 332
 333 static struct clk dsptim_ck = {
 334         .name           = "dsptim_ck",
 335         .ops            = &clkops_dspck,
 336         .parent         = &ck_ref,
 337         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 338                           VIRTUAL_IO_ADDRESS,
 339         .enable_reg     = DSP_IDLECT2,
 340         .enable_bit     = EN_DSPTIMCK,
 341         .recalc         = &followparent_recalc,
 342 };
 343
 344 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 345 static struct arm_idlect1_clk tc_ck = {
 346         .clk = {
 347                 .name           = "tc_ck",
 348                 .ops            = &clkops_null,
 349                 .parent         = &ck_dpll1,
 350                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 351                                   CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 352                                   RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
 353                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 354                 .recalc         = &omap1_ckctl_recalc,
 355                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 356                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 357         },
 358         .idlect_shift   = 6,
 359 };
 360
 361 static struct clk arminth_ck1510 = {
 362         .name           = "arminth_ck",
 363         .ops            = &clkops_null,
 364         .parent         = &tc_ck.clk,
 365         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 366         .recalc         = &followparent_recalc,
 367         /* Note: On 1510 the frequency follows TC_CK
 368          *
 369          * 16xx version is in MPU clocks.
 370          */
 371 };
 372
 373 static struct clk tipb_ck = {
 374         /* No-idle controlled by "tc_ck" */
 375         .name           = "tipb_ck",
 376         .ops            = &clkops_null,
 377         .parent         = &tc_ck.clk,
 378         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 379         .recalc         = &followparent_recalc,
 380 };
 381
 382 static struct clk l3_ocpi_ck = {
 383         /* No-idle controlled by "tc_ck" */
 384         .name           = "l3_ocpi_ck",
 385         .ops            = &clkops_generic,
 386         .parent         = &tc_ck.clk,
 387         .flags          = CLOCK_IN_OMAP16XX,
 388         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 389         .enable_bit     = EN_OCPI_CK,
 390         .recalc         = &followparent_recalc,
 391 };
 392
 393 static struct clk tc1_ck = {
 394         .name           = "tc1_ck",
 395         .ops            = &clkops_generic,
 396         .parent         = &tc_ck.clk,
 397         .flags          = CLOCK_IN_OMAP16XX,
 398         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 399         .enable_bit     = EN_TC1_CK,
 400         .recalc         = &followparent_recalc,
 401 };
 402
 403 static struct clk tc2_ck = {
 404         .name           = "tc2_ck",
 405         .ops            = &clkops_generic,
 406         .parent         = &tc_ck.clk,
 407         .flags          = CLOCK_IN_OMAP16XX,
 408         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 409         .enable_bit     = EN_TC2_CK,
 410         .recalc         = &followparent_recalc,
 411 };
 412
 413 static struct clk dma_ck = {
 414         /* No-idle controlled by "tc_ck" */
 415         .name           = "dma_ck",
 416         .ops            = &clkops_null,
 417         .parent         = &tc_ck.clk,
 418         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 419                           CLOCK_IN_OMAP310,
 420         .recalc         = &followparent_recalc,
 421 };
 422
 423 static struct clk dma_lcdfree_ck = {
 424         .name           = "dma_lcdfree_ck",
 425         .ops            = &clkops_null,
 426         .parent         = &tc_ck.clk,
 427         .flags          = CLOCK_IN_OMAP16XX,
 428         .recalc         = &followparent_recalc,
 429 };
 430
 431 static struct arm_idlect1_clk api_ck = {
 432         .clk = {
 433                 .name           = "api_ck",
 434                 .ops            = &clkops_generic,
 435                 .parent         = &tc_ck.clk,
 436                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 437                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 438                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 439                 .enable_bit     = EN_APICK,
 440                 .recalc         = &followparent_recalc,
 441         },
 442         .idlect_shift   = 8,
 443 };
 444
 445 static struct arm_idlect1_clk lb_ck = {
 446         .clk = {
 447                 .name           = "lb_ck",
 448                 .ops            = &clkops_generic,
 449                 .parent         = &tc_ck.clk,
 450                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 451                                   CLOCK_IDLE_CONTROL,
 452                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 453                 .enable_bit     = EN_LBCK,
 454                 .recalc         = &followparent_recalc,
 455         },
 456         .idlect_shift   = 4,
 457 };
 458
 459 static struct clk rhea1_ck = {
 460         .name           = "rhea1_ck",
 461         .ops            = &clkops_null,
 462         .parent         = &tc_ck.clk,
 463         .flags          = CLOCK_IN_OMAP16XX,
 464         .recalc         = &followparent_recalc,
 465 };
 466
 467 static struct clk rhea2_ck = {
 468         .name           = "rhea2_ck",
 469         .ops            = &clkops_null,
 470         .parent         = &tc_ck.clk,
 471         .flags          = CLOCK_IN_OMAP16XX,
 472         .recalc         = &followparent_recalc,
 473 };
 474
 475 static struct clk lcd_ck_16xx = {
 476         .name           = "lcd_ck",
 477         .ops            = &clkops_generic,
 478         .parent         = &ck_dpll1,
 479         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
 480         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 481         .enable_bit     = EN_LCDCK,
 482         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 483         .recalc         = &omap1_ckctl_recalc,
 484         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 485         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 486 };
 487
 488 static struct arm_idlect1_clk lcd_ck_1510 = {
 489         .clk = {
 490                 .name           = "lcd_ck",
 491                 .ops            = &clkops_generic,
 492                 .parent         = &ck_dpll1,
 493                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 494                                   CLOCK_IDLE_CONTROL,
 495                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 496                 .enable_bit     = EN_LCDCK,
 497                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 498                 .recalc         = &omap1_ckctl_recalc,
 499                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 500                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 501         },
 502         .idlect_shift   = 3,
 503 };
 504
 505 static struct clk uart1_1510 = {
 506         .name           = "uart1_ck",
 507         .ops            = &clkops_null,
 508         /* Direct from ULPD, no real parent */
 509         .parent         = &armper_ck.clk,
 510         .rate           = 12000000,
 511         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 512                           ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 513         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 514         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 515         .set_rate       = &omap1_set_uart_rate,
 516         .recalc         = &omap1_uart_recalc,
 517 };
 518
 519 static struct uart_clk uart1_16xx = {
 520         .clk    = {
 521                 .name           = "uart1_ck",
 522                 .ops            = &clkops_uart,
 523                 /* Direct from ULPD, no real parent */
 524                 .parent         = &armper_ck.clk,
 525                 .rate           = 48000000,
 526                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 527                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 528                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 529                 .enable_bit     = 29,
 530         },
 531         .sysc_addr      = 0xfffb0054,
 532 };
 533
 534 static struct clk uart2_ck = {
 535         .name           = "uart2_ck",
 536         .ops            = &clkops_null,
 537         /* Direct from ULPD, no real parent */
 538         .parent         = &armper_ck.clk,
 539         .rate           = 12000000,
 540         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 541                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 542                           CLOCK_NO_IDLE_PARENT,
 543         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 544         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 545         .set_rate       = &omap1_set_uart_rate,
 546         .recalc         = &omap1_uart_recalc,
 547 };
 548
 549 static struct clk uart3_1510 = {
 550         .name           = "uart3_ck",
 551         .ops            = &clkops_null,
 552         /* Direct from ULPD, no real parent */
 553         .parent         = &armper_ck.clk,
 554         .rate           = 12000000,
 555         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 556                           ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 557         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 558         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 559         .set_rate       = &omap1_set_uart_rate,
 560         .recalc         = &omap1_uart_recalc,
 561 };
 562
 563 static struct uart_clk uart3_16xx = {
 564         .clk    = {
 565                 .name           = "uart3_ck",
 566                 .ops            = &clkops_uart,
 567                 /* Direct from ULPD, no real parent */
 568                 .parent         = &armper_ck.clk,
 569                 .rate           = 48000000,
 570                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 571                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 572                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 573                 .enable_bit     = 31,
 574         },
 575         .sysc_addr      = 0xfffb9854,
 576 };
 577
 578 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 579         .name           = "usb_clko",
 580         .ops            = &clkops_generic,
 581         /* Direct from ULPD, no parent */
 582         .rate           = 6000000,
 583         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 584                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
 585         .enable_reg     = (void __iomem *)ULPD_CLOCK_CTRL,
 586         .enable_bit     = USB_MCLK_EN_BIT,
 587 };
 588
 589 static struct clk usb_hhc_ck1510 = {
 590         .name           = "usb_hhc_ck",
 591         .ops            = &clkops_generic,
 592         /* Direct from ULPD, no parent */
 593         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 594         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 595                           RATE_FIXED | ENABLE_REG_32BIT,
 596         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 597         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 598 };
 599
 600 static struct clk usb_hhc_ck16xx = {
 601         .name           = "usb_hhc_ck",
 602         .ops            = &clkops_generic,
 603         /* Direct from ULPD, no parent */
 604         .rate           = 48000000,
 605         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 606         .flags          = CLOCK_IN_OMAP16XX |
 607                           RATE_FIXED | ENABLE_REG_32BIT,
 608         .enable_reg     = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
 609         .enable_bit     = 8 /* UHOST_EN */,
 610 };
 611
 612 static struct clk usb_dc_ck = {
 613         .name           = "usb_dc_ck",
 614         .ops            = &clkops_generic,
 615         /* Direct from ULPD, no parent */
 616         .rate           = 48000000,
 617         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
 618         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 619         .enable_bit     = 4,
 620 };
 621
 622 static struct clk mclk_1510 = {
 623         .name           = "mclk",
 624         .ops            = &clkops_generic,
 625         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 626         .rate           = 12000000,
 627         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 628         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 629         .enable_bit     = 6,
 630 };
 631
 632 static struct clk mclk_16xx = {
 633         .name           = "mclk",
 634         .ops            = &clkops_generic,
 635         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 636         .flags          = CLOCK_IN_OMAP16XX,
 637         .enable_reg     = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
 638         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 639         .set_rate       = &omap1_set_ext_clk_rate,
 640         .round_rate     = &omap1_round_ext_clk_rate,
 641         .init           = &omap1_init_ext_clk,
 642 };
 643
 644 static struct clk bclk_1510 = {
 645         .name           = "bclk",
 646         .ops            = &clkops_generic,
 647         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 648         .rate           = 12000000,
 649         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 650 };
 651
 652 static struct clk bclk_16xx = {
 653         .name           = "bclk",
 654         .ops            = &clkops_generic,
 655         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 656         .flags          = CLOCK_IN_OMAP16XX,
 657         .enable_reg     = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
 658         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 659         .set_rate       = &omap1_set_ext_clk_rate,
 660         .round_rate     = &omap1_round_ext_clk_rate,
 661         .init           = &omap1_init_ext_clk,
 662 };
 663
 664 static struct clk mmc1_ck = {
 665         .name           = "mmc_ck",
 666         .ops            = &clkops_generic,
 667         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 668         .parent         = &armper_ck.clk,
 669         .rate           = 48000000,
 670         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 671                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
 672                           CLOCK_NO_IDLE_PARENT,
 673         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 674         .enable_bit     = 23,
 675 };
 676
 677 static struct clk mmc2_ck = {
 678         .name           = "mmc_ck",
 679         .id             = 1,
 680         .ops            = &clkops_generic,
 681         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 682         .parent         = &armper_ck.clk,
 683         .rate           = 48000000,
 684         .flags          = CLOCK_IN_OMAP16XX |
 685                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 686         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 687         .enable_bit     = 20,
 688 };
 689
 690 static struct clk virtual_ck_mpu = {
 691         .name           = "mpu",
 692         .ops            = &clkops_null,
 693         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 694                           CLOCK_IN_OMAP310,
 695         .parent         = &arm_ck, /* Is smarter alias for */
 696         .recalc         = &followparent_recalc,
 697         .set_rate       = &omap1_select_table_rate,
 698         .round_rate     = &omap1_round_to_table_rate,
 699 };
 700
 701 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 702 remains active during MPU idle whenever this is enabled */
 703 static struct clk i2c_fck = {
 704         .name           = "i2c_fck",
 705         .id             = 1,
 706         .ops            = &clkops_null,
 707         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 708                           CLOCK_NO_IDLE_PARENT,
 709         .parent         = &armxor_ck.clk,
 710         .recalc         = &followparent_recalc,
 711 };
 712
 713 static struct clk i2c_ick = {
 714         .name           = "i2c_ick",
 715         .id             = 1,
 716         .ops            = &clkops_null,
 717         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT,
 718         .parent         = &armper_ck.clk,
 719         .recalc         = &followparent_recalc,
 720 };
 721
 722 static struct clk * onchip_clks[] = {
 723         /* non-ULPD clocks */
 724         &ck_ref,
 725         &ck_dpll1,
 726         /* CK_GEN1 clocks */
 727         &ck_dpll1out.clk,
 728         &sossi_ck,
 729         &arm_ck,
 730         &armper_ck.clk,
 731         &arm_gpio_ck,
 732         &armxor_ck.clk,
 733         &armtim_ck.clk,
 734         &armwdt_ck.clk,
 735         &arminth_ck1510,  &arminth_ck16xx,
 736         /* CK_GEN2 clocks */
 737         &dsp_ck,
 738         &dspmmu_ck,
 739         &dspper_ck,
 740         &dspxor_ck,
 741         &dsptim_ck,
 742         /* CK_GEN3 clocks */
 743         &tc_ck.clk,
 744         &tipb_ck,
 745         &l3_ocpi_ck,
 746         &tc1_ck,
 747         &tc2_ck,
 748         &dma_ck,
 749         &dma_lcdfree_ck,
 750         &api_ck.clk,
 751         &lb_ck.clk,
 752         &rhea1_ck,
 753         &rhea2_ck,
 754         &lcd_ck_16xx,
 755         &lcd_ck_1510.clk,
 756         /* ULPD clocks */
 757         &uart1_1510,
 758         &uart1_16xx.clk,
 759         &uart2_ck,
 760         &uart3_1510,
 761         &uart3_16xx.clk,
 762         &usb_clko,
 763         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 764         &usb_dc_ck,
 765         &mclk_1510,  &mclk_16xx,
 766         &bclk_1510,  &bclk_16xx,
 767         &mmc1_ck,
 768         &mmc2_ck,
 769         /* Virtual clocks */
 770         &virtual_ck_mpu,
 771         &i2c_fck,
 772         &i2c_ick,
 773 };
 774
 775 #endif