arch/arm/mach-omap1/ams-delta-fiq.c

   1 /*
   2  *  Amstrad E3 FIQ handling
   3  *
   4  *  Copyright (C) 2009 Janusz Krzysztofik
   5  *  Copyright (c) 2006 Matt Callow
   6  *  Copyright (c) 2004 Amstrad Plc
   7  *  Copyright (C) 2001 RidgeRun, Inc.
   8  *
   9  * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
  10  * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License version 2 as published by
  14  * the Free Software Foundation.
  15  */
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/platform_data/ams-delta-fiq.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <mach/board-ams-delta.h>
  26
  27 #include <asm/fiq.h>
  28
  29 #include "ams-delta-fiq.h"
  30
  31 static struct fiq_handler fh = {
  32         .name   = "ams-delta-fiq"
  33 };
  34
  35 /*
  36  * This buffer is shared between FIQ and IRQ contexts.
  37  * The FIQ and IRQ isrs can both read and write it.
  38  * It is structured as a header section several 32bit slots,
  39  * followed by the circular buffer where the FIQ isr stores
  40  * keystrokes received from the qwerty keyboard.  See
  41  * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
  42  */
  43 static unsigned int fiq_buffer[1024];
  44
  45 static struct irq_chip *irq_chip;
  46 static struct irq_data *irq_data[16];
  47 static unsigned int irq_counter[16];
  48
  49 static const char *pin_name[16] __initconst = {
  50         [AMS_DELTA_GPIO_PIN_KEYBRD_DATA]        = "keybrd_data",
  51         [AMS_DELTA_GPIO_PIN_KEYBRD_CLK]         = "keybrd_clk",
  52 };
  53
  54 static irqreturn_t deferred_fiq(int irq, void *dev_id)
  55 {
  56         struct irq_data *d;
  57         int gpio, irq_num, fiq_count;
  58
  59         /*
  60          * For each handled GPIO interrupt, keep calling its interrupt handler
  61          * until the IRQ counter catches the FIQ incremented interrupt counter.
  62          */
  63         for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
  64                         gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
  65                 d = irq_data[gpio];
  66                 irq_num = d->irq;
  67                 fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
  68
  69                 if (irq_counter[gpio] < fiq_count &&
  70                                 gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
  71                         /*
  72                          * handle_simple_irq() that OMAP GPIO edge
  73                          * interrupts default to since commit 80ac93c27441
  74                          * requires interrupt already acked and unmasked.
  75                          */
  76                         if (irq_chip->irq_ack)
  77                                 irq_chip->irq_ack(d);
  78                         if (irq_chip->irq_unmask)
  79                                 irq_chip->irq_unmask(d);
  80                 }
  81                 for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
  82                         generic_handle_irq(irq_num);
  83         }
  84         return IRQ_HANDLED;
  85 }
  86
  87 void __init ams_delta_init_fiq(struct gpio_chip *chip,
  88                                struct platform_device *serio)
  89 {
  90         struct gpio_desc *gpiod, *data = NULL, *clk = NULL;
  91         void *fiqhandler_start;
  92         unsigned int fiqhandler_length;
  93         struct pt_regs FIQ_regs;
  94         unsigned long val, offset;
  95         int i, retval;
  96
  97         /* Store irq_chip location for IRQ handler use */
  98         irq_chip = chip->irq.chip;
  99         if (!irq_chip) {
 100                 pr_err("%s: GPIO chip %s is missing IRQ function\n", __func__,
 101                        chip->label);
 102                 return;
 103         }
 104
 105         for (i = 0; i < ARRAY_SIZE(irq_data); i++) {
 106                 gpiod = gpiochip_request_own_desc(chip, i, pin_name[i]);
 107                 if (IS_ERR(gpiod)) {
 108                         pr_err("%s: failed to get GPIO pin %d (%ld)\n",
 109                                __func__, i, PTR_ERR(gpiod));
 110                         return;
 111                 }
 112                 /* Store irq_data location for IRQ handler use */
 113                 irq_data[i] = irq_get_irq_data(gpiod_to_irq(gpiod));
 114
 115                 /*
 116                  * FIQ handler takes full control over serio data and clk GPIO
 117                  * pins.  Initiaize them and keep requested so nobody can
 118                  * interfere.  Fail if any of those two couldn't be requested.
 119                  */
 120                 switch (i) {
 121                 case AMS_DELTA_GPIO_PIN_KEYBRD_DATA:
 122                         data = gpiod;
 123                         gpiod_direction_input(data);
 124                         break;
 125                 case AMS_DELTA_GPIO_PIN_KEYBRD_CLK:
 126                         clk = gpiod;
 127                         gpiod_direction_input(clk);
 128                         break;
 129                 default:
 130                         gpiochip_free_own_desc(gpiod);
 131                         break;
 132                 }
 133         }
 134         if (!data || !clk)
 135                 goto out_gpio;
 136
 137         fiqhandler_start = &qwerty_fiqin_start;
 138         fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
 139         pr_info("Installing fiq handler from %p, length 0x%x\n",
 140                         fiqhandler_start, fiqhandler_length);
 141
 142         retval = claim_fiq(&fh);
 143         if (retval) {
 144                 pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
 145                                 retval);
 146                 goto out_gpio;
 147         }
 148
 149         retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
 150                         IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
 151         if (retval < 0) {
 152                 pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
 153                 release_fiq(&fh);
 154                 goto out_gpio;
 155         }
 156         /*
 157          * Since no set_type() method is provided by OMAP irq chip,
 158          * switch to edge triggered interrupt type manually.
 159          */
 160         offset = IRQ_ILR0_REG_OFFSET +
 161                         ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
 162         val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
 163         omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
 164
 165         set_fiq_handler(fiqhandler_start, fiqhandler_length);
 166
 167         /*
 168          * Initialise the buffer which is shared
 169          * between FIQ mode and IRQ mode
 170          */
 171         fiq_buffer[FIQ_GPIO_INT_MASK]   = 0;
 172         fiq_buffer[FIQ_MASK]            = 0;
 173         fiq_buffer[FIQ_STATE]           = 0;
 174         fiq_buffer[FIQ_KEY]             = 0;
 175         fiq_buffer[FIQ_KEYS_CNT]        = 0;
 176         fiq_buffer[FIQ_KEYS_HICNT]      = 0;
 177         fiq_buffer[FIQ_TAIL_OFFSET]     = 0;
 178         fiq_buffer[FIQ_HEAD_OFFSET]     = 0;
 179         fiq_buffer[FIQ_BUF_LEN]         = 256;
 180         fiq_buffer[FIQ_MISSED_KEYS]     = 0;
 181         fiq_buffer[FIQ_BUFFER_START]    =
 182                         (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
 183
 184         for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
 185                 fiq_buffer[i] = 0;
 186
 187         /*
 188          * FIQ mode r9 always points to the fiq_buffer, because the FIQ isr
 189          * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
 190          * only means of communication with the IRQ level and other kernel
 191          * context code.
 192          */
 193         FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
 194         set_fiq_regs(&FIQ_regs);
 195
 196         pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
 197
 198         /*
 199          * Redirect GPIO interrupts to FIQ
 200          */
 201         offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
 202         val = omap_readl(OMAP_IH1_BASE + offset) | 1;
 203         omap_writel(val, OMAP_IH1_BASE + offset);
 204
 205         /* Initialize serio device IRQ resource and platform_data */
 206         serio->resource[0].start = gpiod_to_irq(clk);
 207         serio->resource[0].end = serio->resource[0].start;
 208         serio->dev.platform_data = fiq_buffer;
 209
 210         /*
 211          * Since FIQ handler performs handling of GPIO registers for
 212          * "keybrd_clk" IRQ pin, ams_delta_serio driver used to set
 213          * handle_simple_irq() as active IRQ handler for that pin to avoid
 214          * bad interaction with gpio-omap driver.  This is no longer needed
 215          * as handle_simple_irq() is now the default handler for OMAP GPIO
 216          * edge interrupts.
 217          * This comment replaces the obsolete code which has been removed
 218          * from the ams_delta_serio driver and stands here only as a reminder
 219          * of that dependency on gpio-omap driver behavior.
 220          */
 221
 222         return;
 223
 224 out_gpio:
 225         if (data)
 226                 gpiochip_free_own_desc(data);
 227         if (clk)
 228                 gpiochip_free_own_desc(clk);
 229 }