1 // SPDX-License-Identifier: GPL-2.0-only
3 * iop13xx tpmi device resources
4 * Copyright (c) 2005-2006, Intel Corporation.
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
13 #include <linux/sizes.h>
14 #include <mach/irqs.h>
16 /* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
17 #define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
18 #define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
19 #define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
20 #define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
21 #define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1)
22 #define IOP13XX_TPMI_MEM_SIZE (255)
23 #define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1)
24 #define IOP13XX_TPMI_RESOURCE_MMR 0
25 #define IOP13XX_TPMI_RESOURCE_MEM 1
26 #define IOP13XX_TPMI_RESOURCE_CTRL 2
27 #define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
28 #define IOP13XX_TPMI_RESOURCE_IRQ 4
30 static struct resource iop13xx_tpmi_0_resources[] = {
31 [IOP13XX_TPMI_RESOURCE_MMR] = {
32 .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
33 .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
34 .flags = IORESOURCE_MEM,
36 [IOP13XX_TPMI_RESOURCE_MEM] = {
37 .start = IOP13XX_TPMI_MEM(0),
38 .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
39 .flags = IORESOURCE_MEM,
41 [IOP13XX_TPMI_RESOURCE_CTRL] = {
42 .start = IOP13XX_TPMI_CTRL(0),
43 .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
44 .flags = IORESOURCE_MEM,
46 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
47 .start = IOP13XX_TPMI_IOP_CTRL(0),
48 .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
49 .flags = IORESOURCE_MEM,
51 [IOP13XX_TPMI_RESOURCE_IRQ] = {
52 .start = IRQ_IOP13XX_TPMI0_OUT,
53 .end = IRQ_IOP13XX_TPMI0_OUT,
54 .flags = IORESOURCE_IRQ
58 static struct resource iop13xx_tpmi_1_resources[] = {
59 [IOP13XX_TPMI_RESOURCE_MMR] = {
60 .start = IOP13XX_TPMI_MMR(1),
61 .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
62 .flags = IORESOURCE_MEM,
64 [IOP13XX_TPMI_RESOURCE_MEM] = {
65 .start = IOP13XX_TPMI_MEM(1),
66 .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
67 .flags = IORESOURCE_MEM,
69 [IOP13XX_TPMI_RESOURCE_CTRL] = {
70 .start = IOP13XX_TPMI_CTRL(1),
71 .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
72 .flags = IORESOURCE_MEM,
74 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
75 .start = IOP13XX_TPMI_IOP_CTRL(1),
76 .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
77 .flags = IORESOURCE_MEM,
79 [IOP13XX_TPMI_RESOURCE_IRQ] = {
80 .start = IRQ_IOP13XX_TPMI1_OUT,
81 .end = IRQ_IOP13XX_TPMI1_OUT,
82 .flags = IORESOURCE_IRQ
86 static struct resource iop13xx_tpmi_2_resources[] = {
87 [IOP13XX_TPMI_RESOURCE_MMR] = {
88 .start = IOP13XX_TPMI_MMR(2),
89 .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
90 .flags = IORESOURCE_MEM,
92 [IOP13XX_TPMI_RESOURCE_MEM] = {
93 .start = IOP13XX_TPMI_MEM(2),
94 .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
95 .flags = IORESOURCE_MEM,
97 [IOP13XX_TPMI_RESOURCE_CTRL] = {
98 .start = IOP13XX_TPMI_CTRL(2),
99 .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
100 .flags = IORESOURCE_MEM,
102 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
103 .start = IOP13XX_TPMI_IOP_CTRL(2),
104 .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
105 .flags = IORESOURCE_MEM,
107 [IOP13XX_TPMI_RESOURCE_IRQ] = {
108 .start = IRQ_IOP13XX_TPMI2_OUT,
109 .end = IRQ_IOP13XX_TPMI2_OUT,
110 .flags = IORESOURCE_IRQ
114 static struct resource iop13xx_tpmi_3_resources[] = {
115 [IOP13XX_TPMI_RESOURCE_MMR] = {
116 .start = IOP13XX_TPMI_MMR(3),
117 .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
118 .flags = IORESOURCE_MEM,
120 [IOP13XX_TPMI_RESOURCE_MEM] = {
121 .start = IOP13XX_TPMI_MEM(3),
122 .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
123 .flags = IORESOURCE_MEM,
125 [IOP13XX_TPMI_RESOURCE_CTRL] = {
126 .start = IOP13XX_TPMI_CTRL(3),
127 .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
128 .flags = IORESOURCE_MEM,
130 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
131 .start = IOP13XX_TPMI_IOP_CTRL(3),
132 .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
133 .flags = IORESOURCE_MEM,
135 [IOP13XX_TPMI_RESOURCE_IRQ] = {
136 .start = IRQ_IOP13XX_TPMI3_OUT,
137 .end = IRQ_IOP13XX_TPMI3_OUT,
138 .flags = IORESOURCE_IRQ
142 u64 iop13xx_tpmi_mask = DMA_BIT_MASK(32);
143 static struct platform_device iop13xx_tpmi_0_device = {
146 .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
147 .resource = iop13xx_tpmi_0_resources,
149 .dma_mask = &iop13xx_tpmi_mask,
150 .coherent_dma_mask = DMA_BIT_MASK(32),
154 static struct platform_device iop13xx_tpmi_1_device = {
157 .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
158 .resource = iop13xx_tpmi_1_resources,
160 .dma_mask = &iop13xx_tpmi_mask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
165 static struct platform_device iop13xx_tpmi_2_device = {
168 .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
169 .resource = iop13xx_tpmi_2_resources,
171 .dma_mask = &iop13xx_tpmi_mask,
172 .coherent_dma_mask = DMA_BIT_MASK(32),
176 static struct platform_device iop13xx_tpmi_3_device = {
179 .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
180 .resource = iop13xx_tpmi_3_resources,
182 .dma_mask = &iop13xx_tpmi_mask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
187 __init void iop13xx_add_tpmi_devices(void)
189 unsigned short device_id;
191 /* tpmi's not present on iop341 or iop342 */
192 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
193 /* ATUE must be present */
194 device_id = __raw_readw(IOP13XX_ATUE_DID);
196 /* ATUX must be present */
197 device_id = __raw_readw(IOP13XX_ATUX_DID);
200 /* iop34[1|2] 0-tpmi */
235 platform_device_register(&iop13xx_tpmi_0_device);
238 platform_device_register(&iop13xx_tpmi_0_device);
239 platform_device_register(&iop13xx_tpmi_1_device);
240 platform_device_register(&iop13xx_tpmi_2_device);
241 platform_device_register(&iop13xx_tpmi_3_device);