2 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/memory.h>
19 #include <linux/platform_device.h>
20 #include <linux/mtd/physmap.h>
21 #include <linux/mtd/platnand.h>
22 #include <linux/gpio.h>
24 #include <asm/mach-types.h>
25 #include <asm/mach/arch.h>
26 #include <asm/mach/time.h>
27 #include <asm/mach/map.h>
29 #include <asm/setup.h>
32 #include "devices-imx31.h"
34 #include "iomux-mx3.h"
37 #define QONG_FPGA_VERSION(major, minor, rev) \
38 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
40 #define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
41 #define QONG_FPGA_PERIPH_SIZE (1 << 24)
43 #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
44 #define QONG_FPGA_CTRL_SIZE 0x10
45 /* FPGA control registers */
46 #define QONG_FPGA_CTRL_VERSION 0x00
48 #define QONG_DNET_ID 1
49 #define QONG_DNET_BASEADDR \
50 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
51 #define QONG_DNET_SIZE 0x00001000
53 static const struct imxuart_platform_data uart_pdata __initconst = {
54 .flags = IMXUART_HAVE_RTSCTS,
57 static int uart_pins[] = {
64 static inline void __init mxc_init_imx_uart(void)
66 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
68 imx31_add_imx_uart0(&uart_pdata);
71 static struct resource dnet_resources[] = {
73 .name = "dnet-memory",
74 .start = QONG_DNET_BASEADDR,
75 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
76 .flags = IORESOURCE_MEM,
78 /* irq number is run-time assigned */
79 .flags = IORESOURCE_IRQ,
83 static struct platform_device dnet_device = {
86 .num_resources = ARRAY_SIZE(dnet_resources),
87 .resource = dnet_resources,
90 static int __init qong_init_dnet(void)
94 dnet_resources[1].start =
95 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
96 dnet_resources[1].end =
97 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
98 ret = platform_device_register(&dnet_device);
104 static struct physmap_flash_data qong_flash_data = {
108 static struct resource qong_flash_resource = {
109 .start = MX31_CS0_BASE_ADDR,
110 .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
111 .flags = IORESOURCE_MEM,
114 static struct platform_device qong_nor_mtd_device = {
115 .name = "physmap-flash",
118 .platform_data = &qong_flash_data,
120 .resource = &qong_flash_resource,
124 static void qong_init_nor_mtd(void)
126 (void)platform_device_register(&qong_nor_mtd_device);
130 * Hardware specific access to control-lines
132 static void qong_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
135 if (cmd == NAND_CMD_NONE)
139 writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 24));
141 writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 23));
145 * Read the Device Ready pin.
147 static int qong_nand_device_ready(struct nand_chip *chip)
149 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
152 static void qong_nand_select_chip(struct nand_chip *chip, int cs)
155 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
157 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
160 static struct platform_nand_data qong_nand_data = {
167 .cmd_ctrl = qong_nand_cmd_ctrl,
168 .dev_ready = qong_nand_device_ready,
169 .select_chip = qong_nand_select_chip,
173 static struct resource qong_nand_resource = {
174 .start = MX31_CS3_BASE_ADDR,
175 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
176 .flags = IORESOURCE_MEM,
179 static struct platform_device qong_nand_device = {
183 .platform_data = &qong_nand_data,
186 .resource = &qong_nand_resource,
189 static void __init qong_init_nand_mtd(void)
192 imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
193 imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
194 imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
196 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
199 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
200 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
201 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
204 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
205 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
206 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
208 /* write protect pin */
209 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
210 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
211 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
213 platform_device_register(&qong_nand_device);
216 static void __init qong_init_fpga(void)
221 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
223 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
228 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
230 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
231 (fpga_ver & 0xF000) >> 12,
232 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
233 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
234 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
235 "devices won't be registered!\n");
239 /* register FPGA-based devices */
240 qong_init_nand_mtd();
245 * Board specific initialization.
247 static void __init qong_init(void)
253 imx31_add_imx2_wdt();
256 static void __init qong_timer_init(void)
258 mx31_clocks_init(26000000);
261 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
262 /* Maintainer: DENX Software Engineering GmbH */
263 .atag_offset = 0x100,
264 .map_io = mx31_map_io,
265 .init_early = imx31_init_early,
266 .init_irq = mx31_init_irq,
267 .init_time = qong_timer_init,
268 .init_machine = qong_init,
269 .init_late = qong_init_fpga,
270 .restart = mxc_restart,