arch/arm/mach-imx/clock-imx6q.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/types.h>
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <asm/div64.h>
  22 #include <asm/mach/map.h>
  23 #include <mach/clock.h>
  24 #include <mach/common.h>
  25 #include <mach/hardware.h>
  26
  27 #define PLL_BASE                IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR)
  28 #define PLL1_SYS                (PLL_BASE + 0x000)
  29 #define PLL2_BUS                (PLL_BASE + 0x030)
  30 #define PLL3_USB_OTG            (PLL_BASE + 0x010)
  31 #define PLL4_AUDIO              (PLL_BASE + 0x070)
  32 #define PLL5_VIDEO              (PLL_BASE + 0x0a0)
  33 #define PLL6_MLB                (PLL_BASE + 0x0d0)
  34 #define PLL7_USB_HOST           (PLL_BASE + 0x020)
  35 #define PLL8_ENET               (PLL_BASE + 0x0e0)
  36 #define PFD_480                 (PLL_BASE + 0x0f0)
  37 #define PFD_528                 (PLL_BASE + 0x100)
  38 #define PLL_NUM_OFFSET          0x010
  39 #define PLL_DENOM_OFFSET        0x020
  40
  41 #define PFD0                    7
  42 #define PFD1                    15
  43 #define PFD2                    23
  44 #define PFD3                    31
  45 #define PFD_FRAC_MASK           0x3f
  46
  47 #define BM_PLL_BYPASS                   (0x1 << 16)
  48 #define BM_PLL_ENABLE                   (0x1 << 13)
  49 #define BM_PLL_POWER_DOWN               (0x1 << 12)
  50 #define BM_PLL_LOCK                     (0x1 << 31)
  51 #define BP_PLL_SYS_DIV_SELECT           0
  52 #define BM_PLL_SYS_DIV_SELECT           (0x7f << 0)
  53 #define BP_PLL_BUS_DIV_SELECT           0
  54 #define BM_PLL_BUS_DIV_SELECT           (0x1 << 0)
  55 #define BP_PLL_USB_DIV_SELECT           0
  56 #define BM_PLL_USB_DIV_SELECT           (0x3 << 0)
  57 #define BP_PLL_AV_DIV_SELECT            0
  58 #define BM_PLL_AV_DIV_SELECT            (0x7f << 0)
  59 #define BP_PLL_ENET_DIV_SELECT          0
  60 #define BM_PLL_ENET_DIV_SELECT          (0x3 << 0)
  61 #define BM_PLL_ENET_EN_PCIE             (0x1 << 19)
  62 #define BM_PLL_ENET_EN_SATA             (0x1 << 20)
  63
  64 #define CCM_BASE        IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR)
  65 #define CCR             (CCM_BASE + 0x00)
  66 #define CCDR            (CCM_BASE + 0x04)
  67 #define CSR             (CCM_BASE + 0x08)
  68 #define CCSR            (CCM_BASE + 0x0c)
  69 #define CACRR           (CCM_BASE + 0x10)
  70 #define CBCDR           (CCM_BASE + 0x14)
  71 #define CBCMR           (CCM_BASE + 0x18)
  72 #define CSCMR1          (CCM_BASE + 0x1c)
  73 #define CSCMR2          (CCM_BASE + 0x20)
  74 #define CSCDR1          (CCM_BASE + 0x24)
  75 #define CS1CDR          (CCM_BASE + 0x28)
  76 #define CS2CDR          (CCM_BASE + 0x2c)
  77 #define CDCDR           (CCM_BASE + 0x30)
  78 #define CHSCCDR         (CCM_BASE + 0x34)
  79 #define CSCDR2          (CCM_BASE + 0x38)
  80 #define CSCDR3          (CCM_BASE + 0x3c)
  81 #define CSCDR4          (CCM_BASE + 0x40)
  82 #define CWDR            (CCM_BASE + 0x44)
  83 #define CDHIPR          (CCM_BASE + 0x48)
  84 #define CDCR            (CCM_BASE + 0x4c)
  85 #define CTOR            (CCM_BASE + 0x50)
  86 #define CLPCR           (CCM_BASE + 0x54)
  87 #define CISR            (CCM_BASE + 0x58)
  88 #define CIMR            (CCM_BASE + 0x5c)
  89 #define CCOSR           (CCM_BASE + 0x60)
  90 #define CGPR            (CCM_BASE + 0x64)
  91 #define CCGR0           (CCM_BASE + 0x68)
  92 #define CCGR1           (CCM_BASE + 0x6c)
  93 #define CCGR2           (CCM_BASE + 0x70)
  94 #define CCGR3           (CCM_BASE + 0x74)
  95 #define CCGR4           (CCM_BASE + 0x78)
  96 #define CCGR5           (CCM_BASE + 0x7c)
  97 #define CCGR6           (CCM_BASE + 0x80)
  98 #define CCGR7           (CCM_BASE + 0x84)
  99 #define CMEOR           (CCM_BASE + 0x88)
 100
 101 #define CG0             0
 102 #define CG1             2
 103 #define CG2             4
 104 #define CG3             6
 105 #define CG4             8
 106 #define CG5             10
 107 #define CG6             12
 108 #define CG7             14
 109 #define CG8             16
 110 #define CG9             18
 111 #define CG10            20
 112 #define CG11            22
 113 #define CG12            24
 114 #define CG13            26
 115 #define CG14            28
 116 #define CG15            30
 117
 118 #define BM_CCSR_PLL1_SW_SEL             (0x1 << 2)
 119 #define BM_CCSR_STEP_SEL                (0x1 << 8)
 120
 121 #define BP_CACRR_ARM_PODF               0
 122 #define BM_CACRR_ARM_PODF               (0x7 << 0)
 123
 124 #define BP_CBCDR_PERIPH2_CLK2_PODF      0
 125 #define BM_CBCDR_PERIPH2_CLK2_PODF      (0x7 << 0)
 126 #define BP_CBCDR_MMDC_CH1_AXI_PODF      3
 127 #define BM_CBCDR_MMDC_CH1_AXI_PODF      (0x7 << 3)
 128 #define BP_CBCDR_AXI_SEL                6
 129 #define BM_CBCDR_AXI_SEL                (0x3 << 6)
 130 #define BP_CBCDR_IPG_PODF               8
 131 #define BM_CBCDR_IPG_PODF               (0x3 << 8)
 132 #define BP_CBCDR_AHB_PODF               10
 133 #define BM_CBCDR_AHB_PODF               (0x7 << 10)
 134 #define BP_CBCDR_AXI_PODF               16
 135 #define BM_CBCDR_AXI_PODF               (0x7 << 16)
 136 #define BP_CBCDR_MMDC_CH0_AXI_PODF      19
 137 #define BM_CBCDR_MMDC_CH0_AXI_PODF      (0x7 << 19)
 138 #define BP_CBCDR_PERIPH_CLK_SEL         25
 139 #define BM_CBCDR_PERIPH_CLK_SEL         (0x1 << 25)
 140 #define BP_CBCDR_PERIPH2_CLK_SEL        26
 141 #define BM_CBCDR_PERIPH2_CLK_SEL        (0x1 << 26)
 142 #define BP_CBCDR_PERIPH_CLK2_PODF       27
 143 #define BM_CBCDR_PERIPH_CLK2_PODF       (0x7 << 27)
 144
 145 #define BP_CBCMR_GPU2D_AXI_SEL          0
 146 #define BM_CBCMR_GPU2D_AXI_SEL          (0x1 << 0)
 147 #define BP_CBCMR_GPU3D_AXI_SEL          1
 148 #define BM_CBCMR_GPU3D_AXI_SEL          (0x1 << 1)
 149 #define BP_CBCMR_GPU3D_CORE_SEL         4
 150 #define BM_CBCMR_GPU3D_CORE_SEL         (0x3 << 4)
 151 #define BP_CBCMR_GPU3D_SHADER_SEL       8
 152 #define BM_CBCMR_GPU3D_SHADER_SEL       (0x3 << 8)
 153 #define BP_CBCMR_PCIE_AXI_SEL           10
 154 #define BM_CBCMR_PCIE_AXI_SEL           (0x1 << 10)
 155 #define BP_CBCMR_VDO_AXI_SEL            11
 156 #define BM_CBCMR_VDO_AXI_SEL            (0x1 << 11)
 157 #define BP_CBCMR_PERIPH_CLK2_SEL        12
 158 #define BM_CBCMR_PERIPH_CLK2_SEL        (0x3 << 12)
 159 #define BP_CBCMR_VPU_AXI_SEL            14
 160 #define BM_CBCMR_VPU_AXI_SEL            (0x3 << 14)
 161 #define BP_CBCMR_GPU2D_CORE_SEL         16
 162 #define BM_CBCMR_GPU2D_CORE_SEL         (0x3 << 16)
 163 #define BP_CBCMR_PRE_PERIPH_CLK_SEL     18
 164 #define BM_CBCMR_PRE_PERIPH_CLK_SEL     (0x3 << 18)
 165 #define BP_CBCMR_PERIPH2_CLK2_SEL       20
 166 #define BM_CBCMR_PERIPH2_CLK2_SEL       (0x1 << 20)
 167 #define BP_CBCMR_PRE_PERIPH2_CLK_SEL    21
 168 #define BM_CBCMR_PRE_PERIPH2_CLK_SEL    (0x3 << 21)
 169 #define BP_CBCMR_GPU2D_CORE_PODF        23
 170 #define BM_CBCMR_GPU2D_CORE_PODF        (0x7 << 23)
 171 #define BP_CBCMR_GPU3D_CORE_PODF        26
 172 #define BM_CBCMR_GPU3D_CORE_PODF        (0x7 << 26)
 173 #define BP_CBCMR_GPU3D_SHADER_PODF      29
 174 #define BM_CBCMR_GPU3D_SHADER_PODF      (0x7 << 29)
 175
 176 #define BP_CSCMR1_PERCLK_PODF           0
 177 #define BM_CSCMR1_PERCLK_PODF           (0x3f << 0)
 178 #define BP_CSCMR1_SSI1_SEL              10
 179 #define BM_CSCMR1_SSI1_SEL              (0x3 << 10)
 180 #define BP_CSCMR1_SSI2_SEL              12
 181 #define BM_CSCMR1_SSI2_SEL              (0x3 << 12)
 182 #define BP_CSCMR1_SSI3_SEL              14
 183 #define BM_CSCMR1_SSI3_SEL              (0x3 << 14)
 184 #define BP_CSCMR1_USDHC1_SEL            16
 185 #define BM_CSCMR1_USDHC1_SEL            (0x1 << 16)
 186 #define BP_CSCMR1_USDHC2_SEL            17
 187 #define BM_CSCMR1_USDHC2_SEL            (0x1 << 17)
 188 #define BP_CSCMR1_USDHC3_SEL            18
 189 #define BM_CSCMR1_USDHC3_SEL            (0x1 << 18)
 190 #define BP_CSCMR1_USDHC4_SEL            19
 191 #define BM_CSCMR1_USDHC4_SEL            (0x1 << 19)
 192 #define BP_CSCMR1_EMI_PODF              20
 193 #define BM_CSCMR1_EMI_PODF              (0x7 << 20)
 194 #define BP_CSCMR1_EMI_SLOW_PODF         23
 195 #define BM_CSCMR1_EMI_SLOW_PODF         (0x7 << 23)
 196 #define BP_CSCMR1_EMI_SEL               27
 197 #define BM_CSCMR1_EMI_SEL               (0x3 << 27)
 198 #define BP_CSCMR1_EMI_SLOW_SEL          29
 199 #define BM_CSCMR1_EMI_SLOW_SEL          (0x3 << 29)
 200
 201 #define BP_CSCMR2_CAN_PODF              2
 202 #define BM_CSCMR2_CAN_PODF              (0x3f << 2)
 203 #define BM_CSCMR2_LDB_DI0_IPU_DIV       (0x1 << 10)
 204 #define BM_CSCMR2_LDB_DI1_IPU_DIV       (0x1 << 11)
 205 #define BP_CSCMR2_ESAI_SEL              19
 206 #define BM_CSCMR2_ESAI_SEL              (0x3 << 19)
 207
 208 #define BP_CSCDR1_UART_PODF             0
 209 #define BM_CSCDR1_UART_PODF             (0x3f << 0)
 210 #define BP_CSCDR1_USDHC1_PODF           11
 211 #define BM_CSCDR1_USDHC1_PODF           (0x7 << 11)
 212 #define BP_CSCDR1_USDHC2_PODF           16
 213 #define BM_CSCDR1_USDHC2_PODF           (0x7 << 16)
 214 #define BP_CSCDR1_USDHC3_PODF           19
 215 #define BM_CSCDR1_USDHC3_PODF           (0x7 << 19)
 216 #define BP_CSCDR1_USDHC4_PODF           22
 217 #define BM_CSCDR1_USDHC4_PODF           (0x7 << 22)
 218 #define BP_CSCDR1_VPU_AXI_PODF          25
 219 #define BM_CSCDR1_VPU_AXI_PODF          (0x7 << 25)
 220
 221 #define BP_CS1CDR_SSI1_PODF             0
 222 #define BM_CS1CDR_SSI1_PODF             (0x3f << 0)
 223 #define BP_CS1CDR_SSI1_PRED             6
 224 #define BM_CS1CDR_SSI1_PRED             (0x7 << 6)
 225 #define BP_CS1CDR_ESAI_PRED             9
 226 #define BM_CS1CDR_ESAI_PRED             (0x7 << 9)
 227 #define BP_CS1CDR_SSI3_PODF             16
 228 #define BM_CS1CDR_SSI3_PODF             (0x3f << 16)
 229 #define BP_CS1CDR_SSI3_PRED             22
 230 #define BM_CS1CDR_SSI3_PRED             (0x7 << 22)
 231 #define BP_CS1CDR_ESAI_PODF             25
 232 #define BM_CS1CDR_ESAI_PODF             (0x7 << 25)
 233
 234 #define BP_CS2CDR_SSI2_PODF             0
 235 #define BM_CS2CDR_SSI2_PODF             (0x3f << 0)
 236 #define BP_CS2CDR_SSI2_PRED             6
 237 #define BM_CS2CDR_SSI2_PRED             (0x7 << 6)
 238 #define BP_CS2CDR_LDB_DI0_SEL           9
 239 #define BM_CS2CDR_LDB_DI0_SEL           (0x7 << 9)
 240 #define BP_CS2CDR_LDB_DI1_SEL           12
 241 #define BM_CS2CDR_LDB_DI1_SEL           (0x7 << 12)
 242 #define BP_CS2CDR_ENFC_SEL              16
 243 #define BM_CS2CDR_ENFC_SEL              (0x3 << 16)
 244 #define BP_CS2CDR_ENFC_PRED             18
 245 #define BM_CS2CDR_ENFC_PRED             (0x7 << 18)
 246 #define BP_CS2CDR_ENFC_PODF             21
 247 #define BM_CS2CDR_ENFC_PODF             (0x3f << 21)
 248
 249 #define BP_CDCDR_ASRC_SERIAL_SEL        7
 250 #define BM_CDCDR_ASRC_SERIAL_SEL        (0x3 << 7)
 251 #define BP_CDCDR_ASRC_SERIAL_PODF       9
 252 #define BM_CDCDR_ASRC_SERIAL_PODF       (0x7 << 9)
 253 #define BP_CDCDR_ASRC_SERIAL_PRED       12
 254 #define BM_CDCDR_ASRC_SERIAL_PRED       (0x7 << 12)
 255 #define BP_CDCDR_SPDIF_SEL              20
 256 #define BM_CDCDR_SPDIF_SEL              (0x3 << 20)
 257 #define BP_CDCDR_SPDIF_PODF             22
 258 #define BM_CDCDR_SPDIF_PODF             (0x7 << 22)
 259 #define BP_CDCDR_SPDIF_PRED             25
 260 #define BM_CDCDR_SPDIF_PRED             (0x7 << 25)
 261 #define BP_CDCDR_HSI_TX_PODF            29
 262 #define BM_CDCDR_HSI_TX_PODF            (0x7 << 29)
 263 #define BP_CDCDR_HSI_TX_SEL             28
 264 #define BM_CDCDR_HSI_TX_SEL             (0x1 << 28)
 265
 266 #define BP_CHSCCDR_IPU1_DI0_SEL         0
 267 #define BM_CHSCCDR_IPU1_DI0_SEL         (0x7 << 0)
 268 #define BP_CHSCCDR_IPU1_DI0_PRE_PODF    3
 269 #define BM_CHSCCDR_IPU1_DI0_PRE_PODF    (0x7 << 3)
 270 #define BP_CHSCCDR_IPU1_DI0_PRE_SEL     6
 271 #define BM_CHSCCDR_IPU1_DI0_PRE_SEL     (0x7 << 6)
 272 #define BP_CHSCCDR_IPU1_DI1_SEL         9
 273 #define BM_CHSCCDR_IPU1_DI1_SEL         (0x7 << 9)
 274 #define BP_CHSCCDR_IPU1_DI1_PRE_PODF    12
 275 #define BM_CHSCCDR_IPU1_DI1_PRE_PODF    (0x7 << 12)
 276 #define BP_CHSCCDR_IPU1_DI1_PRE_SEL     15
 277 #define BM_CHSCCDR_IPU1_DI1_PRE_SEL     (0x7 << 15)
 278
 279 #define BP_CSCDR2_IPU2_DI0_SEL          0
 280 #define BM_CSCDR2_IPU2_DI0_SEL          (0x7)
 281 #define BP_CSCDR2_IPU2_DI0_PRE_PODF     3
 282 #define BM_CSCDR2_IPU2_DI0_PRE_PODF     (0x7 << 3)
 283 #define BP_CSCDR2_IPU2_DI0_PRE_SEL      6
 284 #define BM_CSCDR2_IPU2_DI0_PRE_SEL      (0x7 << 6)
 285 #define BP_CSCDR2_IPU2_DI1_SEL          9
 286 #define BM_CSCDR2_IPU2_DI1_SEL          (0x7 << 9)
 287 #define BP_CSCDR2_IPU2_DI1_PRE_PODF     12
 288 #define BM_CSCDR2_IPU2_DI1_PRE_PODF     (0x7 << 12)
 289 #define BP_CSCDR2_IPU2_DI1_PRE_SEL      15
 290 #define BM_CSCDR2_IPU2_DI1_PRE_SEL      (0x7 << 15)
 291 #define BP_CSCDR2_ECSPI_CLK_PODF        19
 292 #define BM_CSCDR2_ECSPI_CLK_PODF        (0x3f << 19)
 293
 294 #define BP_CSCDR3_IPU1_HSP_SEL          9
 295 #define BM_CSCDR3_IPU1_HSP_SEL          (0x3 << 9)
 296 #define BP_CSCDR3_IPU1_HSP_PODF         11
 297 #define BM_CSCDR3_IPU1_HSP_PODF         (0x7 << 11)
 298 #define BP_CSCDR3_IPU2_HSP_SEL          14
 299 #define BM_CSCDR3_IPU2_HSP_SEL          (0x3 << 14)
 300 #define BP_CSCDR3_IPU2_HSP_PODF         16
 301 #define BM_CSCDR3_IPU2_HSP_PODF         (0x7 << 16)
 302
 303 #define BM_CDHIPR_AXI_PODF_BUSY         (0x1 << 0)
 304 #define BM_CDHIPR_AHB_PODF_BUSY         (0x1 << 1)
 305 #define BM_CDHIPR_MMDC_CH1_PODF_BUSY    (0x1 << 2)
 306 #define BM_CDHIPR_PERIPH2_SEL_BUSY      (0x1 << 3)
 307 #define BM_CDHIPR_MMDC_CH0_PODF_BUSY    (0x1 << 4)
 308 #define BM_CDHIPR_PERIPH_SEL_BUSY       (0x1 << 5)
 309 #define BM_CDHIPR_ARM_PODF_BUSY         (0x1 << 16)
 310
 311 #define BP_CLPCR_LPM                    0
 312 #define BM_CLPCR_LPM                    (0x3 << 0)
 313 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
 314 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
 315 #define BM_CLPCR_SBYOS                  (0x1 << 6)
 316 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
 317 #define BM_CLPCR_VSTBY                  (0x1 << 8)
 318 #define BP_CLPCR_STBY_COUNT             9
 319 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
 320 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
 321 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
 322 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
 323 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
 324 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
 325 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
 326 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
 327 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
 328 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
 329 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
 330 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
 331
 332 #define BP_CCOSR_CKO1_EN                7
 333 #define BP_CCOSR_CKO1_PODF              4
 334 #define BM_CCOSR_CKO1_PODF              (0x7 << 4)
 335 #define BP_CCOSR_CKO1_SEL               0
 336 #define BM_CCOSR_CKO1_SEL               (0xf << 0)
 337
 338 #define FREQ_480M       480000000
 339 #define FREQ_528M       528000000
 340 #define FREQ_594M       594000000
 341 #define FREQ_650M       650000000
 342 #define FREQ_1300M      1300000000
 343
 344 static struct clk pll1_sys;
 345 static struct clk pll2_bus;
 346 static struct clk pll3_usb_otg;
 347 static struct clk pll4_audio;
 348 static struct clk pll5_video;
 349 static struct clk pll6_mlb;
 350 static struct clk pll7_usb_host;
 351 static struct clk pll8_enet;
 352 static struct clk apbh_dma_clk;
 353 static struct clk arm_clk;
 354 static struct clk ipg_clk;
 355 static struct clk ahb_clk;
 356 static struct clk axi_clk;
 357 static struct clk mmdc_ch0_axi_clk;
 358 static struct clk mmdc_ch1_axi_clk;
 359 static struct clk periph_clk;
 360 static struct clk periph_pre_clk;
 361 static struct clk periph_clk2_clk;
 362 static struct clk periph2_clk;
 363 static struct clk periph2_pre_clk;
 364 static struct clk periph2_clk2_clk;
 365 static struct clk gpu2d_core_clk;
 366 static struct clk gpu3d_core_clk;
 367 static struct clk gpu3d_shader_clk;
 368 static struct clk ipg_perclk;
 369 static struct clk emi_clk;
 370 static struct clk emi_slow_clk;
 371 static struct clk can1_clk;
 372 static struct clk uart_clk;
 373 static struct clk usdhc1_clk;
 374 static struct clk usdhc2_clk;
 375 static struct clk usdhc3_clk;
 376 static struct clk usdhc4_clk;
 377 static struct clk vpu_clk;
 378 static struct clk hsi_tx_clk;
 379 static struct clk ipu1_di0_pre_clk;
 380 static struct clk ipu1_di1_pre_clk;
 381 static struct clk ipu2_di0_pre_clk;
 382 static struct clk ipu2_di1_pre_clk;
 383 static struct clk ipu1_clk;
 384 static struct clk ipu2_clk;
 385 static struct clk ssi1_clk;
 386 static struct clk ssi3_clk;
 387 static struct clk esai_clk;
 388 static struct clk ssi2_clk;
 389 static struct clk spdif_clk;
 390 static struct clk asrc_serial_clk;
 391 static struct clk gpu2d_axi_clk;
 392 static struct clk gpu3d_axi_clk;
 393 static struct clk pcie_clk;
 394 static struct clk vdo_axi_clk;
 395 static struct clk ldb_di0_clk;
 396 static struct clk ldb_di1_clk;
 397 static struct clk ipu1_di0_clk;
 398 static struct clk ipu1_di1_clk;
 399 static struct clk ipu2_di0_clk;
 400 static struct clk ipu2_di1_clk;
 401 static struct clk enfc_clk;
 402 static struct clk cko1_clk;
 403 static struct clk dummy_clk = {};
 404
 405 static unsigned long external_high_reference;
 406 static unsigned long external_low_reference;
 407 static unsigned long oscillator_reference;
 408
 409 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 410 {
 411         return oscillator_reference;
 412 }
 413
 414 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 415 {
 416         return external_high_reference;
 417 }
 418
 419 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 420 {
 421         return external_low_reference;
 422 }
 423
 424 static struct clk ckil_clk = {
 425         .get_rate = get_low_reference_clock_rate,
 426 };
 427
 428 static struct clk ckih_clk = {
 429         .get_rate = get_high_reference_clock_rate,
 430 };
 431
 432 static struct clk osc_clk = {
 433         .get_rate = get_oscillator_reference_clock_rate,
 434 };
 435
 436 static inline void __iomem *pll_get_reg_addr(struct clk *pll)
 437 {
 438         if (pll == &pll1_sys)
 439                 return PLL1_SYS;
 440         else if (pll == &pll2_bus)
 441                 return PLL2_BUS;
 442         else if (pll == &pll3_usb_otg)
 443                 return PLL3_USB_OTG;
 444         else if (pll == &pll4_audio)
 445                 return PLL4_AUDIO;
 446         else if (pll == &pll5_video)
 447                 return PLL5_VIDEO;
 448         else if (pll == &pll6_mlb)
 449                 return PLL6_MLB;
 450         else if (pll == &pll7_usb_host)
 451                 return PLL7_USB_HOST;
 452         else if (pll == &pll8_enet)
 453                 return PLL8_ENET;
 454         else
 455                 BUG();
 456
 457         return NULL;
 458 }
 459
 460 static int pll_enable(struct clk *clk)
 461 {
 462         int timeout = 0x100000;
 463         void __iomem *reg;
 464         u32 val;
 465
 466         reg = pll_get_reg_addr(clk);
 467         val = readl_relaxed(reg);
 468         val &= ~BM_PLL_BYPASS;
 469         val &= ~BM_PLL_POWER_DOWN;
 470         /* 480MHz PLLs have the opposite definition for power bit */
 471         if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
 472                 val |= BM_PLL_POWER_DOWN;
 473         writel_relaxed(val, reg);
 474
 475         /* Wait for PLL to lock */
 476         while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)
 477                 cpu_relax();
 478
 479         if (unlikely(!timeout))
 480                 return -EBUSY;
 481
 482         /* Enable the PLL output now */
 483         val = readl_relaxed(reg);
 484         val |= BM_PLL_ENABLE;
 485         writel_relaxed(val, reg);
 486
 487         return 0;
 488 }
 489
 490 static void pll_disable(struct clk *clk)
 491 {
 492         void __iomem *reg;
 493         u32 val;
 494
 495         reg = pll_get_reg_addr(clk);
 496         val = readl_relaxed(reg);
 497         val &= ~BM_PLL_ENABLE;
 498         val |= BM_PLL_BYPASS;
 499         val |= BM_PLL_POWER_DOWN;
 500         if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
 501                 val &= ~BM_PLL_POWER_DOWN;
 502         writel_relaxed(val, reg);
 503 }
 504
 505 static unsigned long pll1_sys_get_rate(struct clk *clk)
 506 {
 507         u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>
 508                   BP_PLL_SYS_DIV_SELECT;
 509
 510         return clk_get_rate(clk->parent) * div / 2;
 511 }
 512
 513 static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
 514 {
 515         u32 val, div;
 516
 517         if (rate < FREQ_650M || rate > FREQ_1300M)
 518                 return -EINVAL;
 519
 520         div = rate * 2 / clk_get_rate(clk->parent);
 521         val = readl_relaxed(PLL1_SYS);
 522         val &= ~BM_PLL_SYS_DIV_SELECT;
 523         val |= div << BP_PLL_SYS_DIV_SELECT;
 524         writel_relaxed(val, PLL1_SYS);
 525
 526         return 0;
 527 }
 528
 529 static unsigned long pll8_enet_get_rate(struct clk *clk)
 530 {
 531         u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
 532                   BP_PLL_ENET_DIV_SELECT;
 533
 534         switch (div) {
 535         case 0:
 536                 return 25000000;
 537         case 1:
 538                 return 50000000;
 539         case 2:
 540                 return 100000000;
 541         case 3:
 542                 return 125000000;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
 549 {
 550         u32 val, div;
 551
 552         switch (rate) {
 553         case 25000000:
 554                 div = 0;
 555                 break;
 556         case 50000000:
 557                 div = 1;
 558                 break;
 559         case 100000000:
 560                 div = 2;
 561                 break;
 562         case 125000000:
 563                 div = 3;
 564                 break;
 565         default:
 566                 return -EINVAL;
 567         }
 568
 569         val = readl_relaxed(PLL8_ENET);
 570         val &= ~BM_PLL_ENET_DIV_SELECT;
 571         val |= div << BP_PLL_ENET_DIV_SELECT;
 572         writel_relaxed(val, PLL8_ENET);
 573
 574         return 0;
 575 }
 576
 577 static unsigned long pll_av_get_rate(struct clk *clk)
 578 {
 579         void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
 580         unsigned long parent_rate = clk_get_rate(clk->parent);
 581         u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);
 582         u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);
 583         u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>
 584                   BP_PLL_AV_DIV_SELECT;
 585
 586         return (parent_rate * div) + ((parent_rate / mfd) * mfn);
 587 }
 588
 589 static int pll_av_set_rate(struct clk *clk, unsigned long rate)
 590 {
 591         void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
 592         unsigned int parent_rate = clk_get_rate(clk->parent);
 593         u32 val, div;
 594         u32 mfn, mfd = 1000000;
 595         s64 temp64;
 596
 597         if (rate < FREQ_650M || rate > FREQ_1300M)
 598                 return -EINVAL;
 599
 600         div = rate / parent_rate;
 601         temp64 = (u64) (rate - div * parent_rate);
 602         temp64 *= mfd;
 603         do_div(temp64, parent_rate);
 604         mfn = temp64;
 605
 606         val = readl_relaxed(reg);
 607         val &= ~BM_PLL_AV_DIV_SELECT;
 608         val |= div << BP_PLL_AV_DIV_SELECT;
 609         writel_relaxed(val, reg);
 610         writel_relaxed(mfn, reg + PLL_NUM_OFFSET);
 611         writel_relaxed(mfd, reg + PLL_DENOM_OFFSET);
 612
 613         return 0;
 614 }
 615
 616 static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
 617 {
 618         void __iomem *reg;
 619
 620         if (clk == &pll2_bus) {
 621                 reg = PLL2_BUS;
 622                 *bp = BP_PLL_BUS_DIV_SELECT;
 623                 *bm = BM_PLL_BUS_DIV_SELECT;
 624         } else if (clk == &pll3_usb_otg) {
 625                 reg = PLL3_USB_OTG;
 626                 *bp = BP_PLL_USB_DIV_SELECT;
 627                 *bm = BM_PLL_USB_DIV_SELECT;
 628         } else if (clk == &pll7_usb_host) {
 629                 reg = PLL7_USB_HOST;
 630                 *bp = BP_PLL_USB_DIV_SELECT;
 631                 *bm = BM_PLL_USB_DIV_SELECT;
 632         } else {
 633                 BUG();
 634         }
 635
 636         return reg;
 637 }
 638
 639 static unsigned long pll_get_rate(struct clk *clk)
 640 {
 641         void __iomem *reg;
 642         u32 div, bp, bm;
 643
 644         reg = pll_get_div_reg_bit(clk, &bp, &bm);
 645         div = (readl_relaxed(reg) & bm) >> bp;
 646
 647         return (div == 1) ? clk_get_rate(clk->parent) * 22 :
 648                             clk_get_rate(clk->parent) * 20;
 649 }
 650
 651 static int pll_set_rate(struct clk *clk, unsigned long rate)
 652 {
 653         void __iomem *reg;
 654         u32 val, div, bp, bm;
 655
 656         if (rate == FREQ_528M)
 657                 div = 1;
 658         else if (rate == FREQ_480M)
 659                 div = 0;
 660         else
 661                 return -EINVAL;
 662
 663         reg = pll_get_div_reg_bit(clk, &bp, &bm);
 664         val = readl_relaxed(reg);
 665         val &= ~bm;
 666         val |= div << bp;
 667         writel_relaxed(val, reg);
 668
 669         return 0;
 670 }
 671
 672 #define pll2_bus_get_rate       pll_get_rate
 673 #define pll2_bus_set_rate       pll_set_rate
 674 #define pll3_usb_otg_get_rate   pll_get_rate
 675 #define pll3_usb_otg_set_rate   pll_set_rate
 676 #define pll7_usb_host_get_rate  pll_get_rate
 677 #define pll7_usb_host_set_rate  pll_set_rate
 678 #define pll4_audio_get_rate     pll_av_get_rate
 679 #define pll4_audio_set_rate     pll_av_set_rate
 680 #define pll5_video_get_rate     pll_av_get_rate
 681 #define pll5_video_set_rate     pll_av_set_rate
 682 #define pll6_mlb_get_rate       NULL
 683 #define pll6_mlb_set_rate       NULL
 684
 685 #define DEF_PLL(name)                                   \
 686         static struct clk name = {                      \
 687                 .enable         = pll_enable,           \
 688                 .disable        = pll_disable,          \
 689                 .get_rate       = name##_get_rate,      \
 690                 .set_rate       = name##_set_rate,      \
 691                 .parent         = &osc_clk,             \
 692         }
 693
 694 DEF_PLL(pll1_sys);
 695 DEF_PLL(pll2_bus);
 696 DEF_PLL(pll3_usb_otg);
 697 DEF_PLL(pll4_audio);
 698 DEF_PLL(pll5_video);
 699 DEF_PLL(pll6_mlb);
 700 DEF_PLL(pll7_usb_host);
 701 DEF_PLL(pll8_enet);
 702
 703 static unsigned long pfd_get_rate(struct clk *clk)
 704 {
 705         u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
 706         u32 frac, bp_frac;
 707
 708         if (apbh_dma_clk.usecount == 0)
 709                 apbh_dma_clk.enable(&apbh_dma_clk);
 710
 711         bp_frac = clk->enable_shift - 7;
 712         frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;
 713         do_div(tmp, frac);
 714
 715         return tmp;
 716 }
 717
 718 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 719 {
 720         u32 val, frac, bp_frac;
 721         u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
 722
 723         if (apbh_dma_clk.usecount == 0)
 724                 apbh_dma_clk.enable(&apbh_dma_clk);
 725
 726         /*
 727          * Round up the divider so that we don't set a rate
 728          * higher than what is requested
 729          */
 730         tmp += rate / 2;
 731         do_div(tmp, rate);
 732         frac = tmp;
 733         frac = (frac < 12) ? 12 : frac;
 734         frac = (frac > 35) ? 35 : frac;
 735
 736         /*
 737          * The frac field always starts from 7 bits lower
 738          * position of enable bit
 739          */
 740         bp_frac = clk->enable_shift - 7;
 741         val = readl_relaxed(clk->enable_reg);
 742         val &= ~(PFD_FRAC_MASK << bp_frac);
 743         val |= frac << bp_frac;
 744         writel_relaxed(val, clk->enable_reg);
 745
 746         tmp = (u64) clk_get_rate(clk->parent) * 18;
 747         do_div(tmp, frac);
 748
 749         if (apbh_dma_clk.usecount == 0)
 750                 apbh_dma_clk.disable(&apbh_dma_clk);
 751
 752         return 0;
 753 }
 754
 755 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 756 {
 757         u32 frac;
 758         u64 tmp;
 759
 760         tmp = (u64) clk_get_rate(clk->parent) * 18;
 761         tmp += rate / 2;
 762         do_div(tmp, rate);
 763         frac = tmp;
 764         frac = (frac < 12) ? 12 : frac;
 765         frac = (frac > 35) ? 35 : frac;
 766         tmp = (u64) clk_get_rate(clk->parent) * 18;
 767         do_div(tmp, frac);
 768
 769         return tmp;
 770 }
 771
 772 static int pfd_enable(struct clk *clk)
 773 {
 774         u32 val;
 775
 776         if (apbh_dma_clk.usecount == 0)
 777                 apbh_dma_clk.enable(&apbh_dma_clk);
 778
 779         val = readl_relaxed(clk->enable_reg);
 780         val &= ~(1 << clk->enable_shift);
 781         writel_relaxed(val, clk->enable_reg);
 782
 783         if (apbh_dma_clk.usecount == 0)
 784                 apbh_dma_clk.disable(&apbh_dma_clk);
 785
 786         return 0;
 787 }
 788
 789 static void pfd_disable(struct clk *clk)
 790 {
 791         u32 val;
 792
 793         if (apbh_dma_clk.usecount == 0)
 794                 apbh_dma_clk.enable(&apbh_dma_clk);
 795
 796         val = readl_relaxed(clk->enable_reg);
 797         val |= 1 << clk->enable_shift;
 798         writel_relaxed(val, clk->enable_reg);
 799
 800         if (apbh_dma_clk.usecount == 0)
 801                 apbh_dma_clk.disable(&apbh_dma_clk);
 802 }
 803
 804 #define DEF_PFD(name, er, es, p)                        \
 805         static struct clk name = {                      \
 806                 .enable_reg     = er,                   \
 807                 .enable_shift   = es,                   \
 808                 .enable         = pfd_enable,           \
 809                 .disable        = pfd_disable,          \
 810                 .get_rate       = pfd_get_rate,         \
 811                 .set_rate       = pfd_set_rate,         \
 812                 .round_rate     = pfd_round_rate,       \
 813                 .parent         = p,                    \
 814         }
 815
 816 DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus);
 817 DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus);
 818 DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus);
 819 DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg);
 820 DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
 821 DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
 822 DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
 823
 824 static unsigned long twd_clk_get_rate(struct clk *clk)
 825 {
 826         return clk_get_rate(clk->parent) / 2;
 827 }
 828
 829 static struct clk twd_clk = {
 830         .parent = &arm_clk,
 831         .get_rate = twd_clk_get_rate,
 832 };
 833
 834 static unsigned long pll2_200m_get_rate(struct clk *clk)
 835 {
 836         return clk_get_rate(clk->parent) / 2;
 837 }
 838
 839 static struct clk pll2_200m = {
 840         .parent = &pll2_pfd_400m,
 841         .get_rate = pll2_200m_get_rate,
 842 };
 843
 844 static unsigned long pll3_120m_get_rate(struct clk *clk)
 845 {
 846         return clk_get_rate(clk->parent) / 4;
 847 }
 848
 849 static struct clk pll3_120m = {
 850         .parent = &pll3_usb_otg,
 851         .get_rate = pll3_120m_get_rate,
 852 };
 853
 854 static unsigned long pll3_80m_get_rate(struct clk *clk)
 855 {
 856         return clk_get_rate(clk->parent) / 6;
 857 }
 858
 859 static struct clk pll3_80m = {
 860         .parent = &pll3_usb_otg,
 861         .get_rate = pll3_80m_get_rate,
 862 };
 863
 864 static unsigned long pll3_60m_get_rate(struct clk *clk)
 865 {
 866         return clk_get_rate(clk->parent) / 8;
 867 }
 868
 869 static struct clk pll3_60m = {
 870         .parent = &pll3_usb_otg,
 871         .get_rate = pll3_60m_get_rate,
 872 };
 873
 874 static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
 875 {
 876         u32 val = readl_relaxed(CCSR);
 877
 878         if (parent == &pll1_sys) {
 879                 val &= ~BM_CCSR_PLL1_SW_SEL;
 880                 val &= ~BM_CCSR_STEP_SEL;
 881         } else if (parent == &osc_clk) {
 882                 val |= BM_CCSR_PLL1_SW_SEL;
 883                 val &= ~BM_CCSR_STEP_SEL;
 884         } else if (parent == &pll2_pfd_400m) {
 885                 val |= BM_CCSR_PLL1_SW_SEL;
 886                 val |= BM_CCSR_STEP_SEL;
 887         } else {
 888                 return -EINVAL;
 889         }
 890
 891         writel_relaxed(val, CCSR);
 892
 893         return 0;
 894 }
 895
 896 static struct clk pll1_sw_clk = {
 897         .parent = &pll1_sys,
 898         .set_parent = pll1_sw_clk_set_parent,
 899 };
 900
 901 static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf)
 902 {
 903         u32 min_pred, temp_pred, old_err, err;
 904
 905         if (div >= 512) {
 906                 *pred = 8;
 907                 *podf = 64;
 908         } else if (div >= 8) {
 909                 min_pred = (div - 1) / 64 + 1;
 910                 old_err = 8;
 911                 for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) {
 912                         err = div % temp_pred;
 913                         if (err == 0) {
 914                                 *pred = temp_pred;
 915                                 break;
 916                         }
 917                         err = temp_pred - err;
 918                         if (err < old_err) {
 919                                 old_err = err;
 920                                 *pred = temp_pred;
 921                         }
 922                 }
 923                 *podf = (div + *pred - 1) / *pred;
 924         } else if (div < 8) {
 925                 *pred = div;
 926                 *podf = 1;
 927         }
 928 }
 929
 930 static int _clk_enable(struct clk *clk)
 931 {
 932         u32 reg;
 933         reg = readl_relaxed(clk->enable_reg);
 934         reg |= 0x3 << clk->enable_shift;
 935         writel_relaxed(reg, clk->enable_reg);
 936
 937         return 0;
 938 }
 939
 940 static void _clk_disable(struct clk *clk)
 941 {
 942         u32 reg;
 943         reg = readl_relaxed(clk->enable_reg);
 944         reg &= ~(0x3 << clk->enable_shift);
 945         writel_relaxed(reg, clk->enable_reg);
 946 }
 947
 948 static int _clk_enable_1b(struct clk *clk)
 949 {
 950         u32 reg;
 951         reg = readl_relaxed(clk->enable_reg);
 952         reg |= 0x1 << clk->enable_shift;
 953         writel_relaxed(reg, clk->enable_reg);
 954
 955         return 0;
 956 }
 957
 958 static void _clk_disable_1b(struct clk *clk)
 959 {
 960         u32 reg;
 961         reg = readl_relaxed(clk->enable_reg);
 962         reg &= ~(0x1 << clk->enable_shift);
 963         writel_relaxed(reg, clk->enable_reg);
 964 }
 965
 966 struct divider {
 967         struct clk *clk;
 968         void __iomem *reg;
 969         u32 bp_pred;
 970         u32 bm_pred;
 971         u32 bp_podf;
 972         u32 bm_podf;
 973 };
 974
 975 #define DEF_CLK_DIV1(d, c, r, b)                                \
 976         static struct divider d = {                             \
 977                 .clk = c,                                       \
 978                 .reg = r,                                       \
 979                 .bp_podf = BP_##r##_##b##_PODF,                 \
 980                 .bm_podf = BM_##r##_##b##_PODF,                 \
 981         }
 982
 983 DEF_CLK_DIV1(arm_div,           &arm_clk,               CACRR,  ARM);
 984 DEF_CLK_DIV1(ipg_div,           &ipg_clk,               CBCDR,  IPG);
 985 DEF_CLK_DIV1(ahb_div,           &ahb_clk,               CBCDR,  AHB);
 986 DEF_CLK_DIV1(axi_div,           &axi_clk,               CBCDR,  AXI);
 987 DEF_CLK_DIV1(mmdc_ch0_axi_div,  &mmdc_ch0_axi_clk,      CBCDR,  MMDC_CH0_AXI);
 988 DEF_CLK_DIV1(mmdc_ch1_axi_div,  &mmdc_ch1_axi_clk,      CBCDR,  MMDC_CH1_AXI);
 989 DEF_CLK_DIV1(periph_clk2_div,   &periph_clk2_clk,       CBCDR,  PERIPH_CLK2);
 990 DEF_CLK_DIV1(periph2_clk2_div,  &periph2_clk2_clk,      CBCDR,  PERIPH2_CLK2);
 991 DEF_CLK_DIV1(gpu2d_core_div,    &gpu2d_core_clk,        CBCMR,  GPU2D_CORE);
 992 DEF_CLK_DIV1(gpu3d_core_div,    &gpu3d_core_clk,        CBCMR,  GPU3D_CORE);
 993 DEF_CLK_DIV1(gpu3d_shader_div,  &gpu3d_shader_clk,      CBCMR,  GPU3D_SHADER);
 994 DEF_CLK_DIV1(ipg_perclk_div,    &ipg_perclk,            CSCMR1, PERCLK);
 995 DEF_CLK_DIV1(emi_div,           &emi_clk,               CSCMR1, EMI);
 996 DEF_CLK_DIV1(emi_slow_div,      &emi_slow_clk,          CSCMR1, EMI_SLOW);
 997 DEF_CLK_DIV1(can_div,           &can1_clk,              CSCMR2, CAN);
 998 DEF_CLK_DIV1(uart_div,          &uart_clk,              CSCDR1, UART);
 999 DEF_CLK_DIV1(usdhc1_div,        &usdhc1_clk,            CSCDR1, USDHC1);
1000 DEF_CLK_DIV1(usdhc2_div,        &usdhc2_clk,            CSCDR1, USDHC2);
1001 DEF_CLK_DIV1(usdhc3_div,        &usdhc3_clk,            CSCDR1, USDHC3);
1002 DEF_CLK_DIV1(usdhc4_div,        &usdhc4_clk,            CSCDR1, USDHC4);
1003 DEF_CLK_DIV1(vpu_div,           &vpu_clk,               CSCDR1, VPU_AXI);
1004 DEF_CLK_DIV1(hsi_tx_div,        &hsi_tx_clk,            CDCDR,  HSI_TX);
1005 DEF_CLK_DIV1(ipu1_di0_pre_div,  &ipu1_di0_pre_clk,      CHSCCDR, IPU1_DI0_PRE);
1006 DEF_CLK_DIV1(ipu1_di1_pre_div,  &ipu1_di1_pre_clk,      CHSCCDR, IPU1_DI1_PRE);
1007 DEF_CLK_DIV1(ipu2_di0_pre_div,  &ipu2_di0_pre_clk,      CSCDR2, IPU2_DI0_PRE);
1008 DEF_CLK_DIV1(ipu2_di1_pre_div,  &ipu2_di1_pre_clk,      CSCDR2, IPU2_DI1_PRE);
1009 DEF_CLK_DIV1(ipu1_div,          &ipu1_clk,              CSCDR3, IPU1_HSP);
1010 DEF_CLK_DIV1(ipu2_div,          &ipu2_clk,              CSCDR3, IPU2_HSP);
1011 DEF_CLK_DIV1(cko1_div,          &cko1_clk,              CCOSR, CKO1);
1012
1013 #define DEF_CLK_DIV2(d, c, r, b)                                \
1014         static struct divider d = {                             \
1015                 .clk = c,                                       \
1016                 .reg = r,                                       \
1017                 .bp_pred = BP_##r##_##b##_PRED,                 \
1018                 .bm_pred = BM_##r##_##b##_PRED,                 \
1019                 .bp_podf = BP_##r##_##b##_PODF,                 \
1020                 .bm_podf = BM_##r##_##b##_PODF,                 \
1021         }
1022
1023 DEF_CLK_DIV2(ssi1_div,          &ssi1_clk,              CS1CDR, SSI1);
1024 DEF_CLK_DIV2(ssi3_div,          &ssi3_clk,              CS1CDR, SSI3);
1025 DEF_CLK_DIV2(esai_div,          &esai_clk,              CS1CDR, ESAI);
1026 DEF_CLK_DIV2(ssi2_div,          &ssi2_clk,              CS2CDR, SSI2);
1027 DEF_CLK_DIV2(enfc_div,          &enfc_clk,              CS2CDR, ENFC);
1028 DEF_CLK_DIV2(spdif_div,         &spdif_clk,             CDCDR,  SPDIF);
1029 DEF_CLK_DIV2(asrc_serial_div,   &asrc_serial_clk,       CDCDR,  ASRC_SERIAL);
1030
1031 static struct divider *dividers[] = {
1032         &arm_div,
1033         &ipg_div,
1034         &ahb_div,
1035         &axi_div,
1036         &mmdc_ch0_axi_div,
1037         &mmdc_ch1_axi_div,
1038         &periph_clk2_div,
1039         &periph2_clk2_div,
1040         &gpu2d_core_div,
1041         &gpu3d_core_div,
1042         &gpu3d_shader_div,
1043         &ipg_perclk_div,
1044         &emi_div,
1045         &emi_slow_div,
1046         &can_div,
1047         &uart_div,
1048         &usdhc1_div,
1049         &usdhc2_div,
1050         &usdhc3_div,
1051         &usdhc4_div,
1052         &vpu_div,
1053         &hsi_tx_div,
1054         &ipu1_di0_pre_div,
1055         &ipu1_di1_pre_div,
1056         &ipu2_di0_pre_div,
1057         &ipu2_di1_pre_div,
1058         &ipu1_div,
1059         &ipu2_div,
1060         &ssi1_div,
1061         &ssi3_div,
1062         &esai_div,
1063         &ssi2_div,
1064         &enfc_div,
1065         &spdif_div,
1066         &asrc_serial_div,
1067         &cko1_div,
1068 };
1069
1070 static unsigned long ldb_di_clk_get_rate(struct clk *clk)
1071 {
1072         u32 val = readl_relaxed(CSCMR2);
1073
1074         val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV :
1075                                        BM_CSCMR2_LDB_DI1_IPU_DIV;
1076         if (val)
1077                 return clk_get_rate(clk->parent) / 7;
1078         else
1079                 return clk_get_rate(clk->parent) * 2 / 7;
1080 }
1081
1082 static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate)
1083 {
1084         unsigned long parent_rate = clk_get_rate(clk->parent);
1085         u32 val = readl_relaxed(CSCMR2);
1086
1087         if (rate * 7 <= parent_rate + parent_rate / 20)
1088                 val |= BM_CSCMR2_LDB_DI0_IPU_DIV;
1089         else
1090                 val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV;
1091
1092         writel_relaxed(val, CSCMR2);
1093
1094         return 0;
1095 }
1096
1097 static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate)
1098 {
1099         unsigned long parent_rate = clk_get_rate(clk->parent);
1100
1101         if (rate * 7 <= parent_rate + parent_rate / 20)
1102                 return parent_rate / 7;
1103         else
1104                 return 2 * parent_rate / 7;
1105 }
1106
1107 static unsigned long _clk_get_rate(struct clk *clk)
1108 {
1109         struct divider *d;
1110         u32 val, pred, podf;
1111         int i, num;
1112
1113         if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
1114                 return ldb_di_clk_get_rate(clk);
1115
1116         num = ARRAY_SIZE(dividers);
1117         for (i = 0; i < num; i++)
1118                 if (dividers[i]->clk == clk) {
1119                         d = dividers[i];
1120                         break;
1121                 }
1122         if (i == num)
1123                 return clk_get_rate(clk->parent);
1124
1125         val = readl_relaxed(d->reg);
1126         pred = ((val & d->bm_pred) >> d->bp_pred) + 1;
1127         podf = ((val & d->bm_podf) >> d->bp_podf) + 1;
1128
1129         return clk_get_rate(clk->parent) / (pred * podf);
1130 }
1131
1132 static int clk_busy_wait(struct clk *clk)
1133 {
1134         int timeout = 0x100000;
1135         u32 bm;
1136
1137         if (clk == &axi_clk)
1138                 bm = BM_CDHIPR_AXI_PODF_BUSY;
1139         else if (clk == &ahb_clk)
1140                 bm = BM_CDHIPR_AHB_PODF_BUSY;
1141         else if (clk == &mmdc_ch0_axi_clk)
1142                 bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY;
1143         else if (clk == &periph_clk)
1144                 bm = BM_CDHIPR_PERIPH_SEL_BUSY;
1145         else if (clk == &arm_clk)
1146                 bm = BM_CDHIPR_ARM_PODF_BUSY;
1147         else
1148                 return -EINVAL;
1149
1150         while ((readl_relaxed(CDHIPR) & bm) && --timeout)
1151                 cpu_relax();
1152
1153         if (unlikely(!timeout))
1154                 return -EBUSY;
1155
1156         return 0;
1157 }
1158
1159 static int _clk_set_rate(struct clk *clk, unsigned long rate)
1160 {
1161         unsigned long parent_rate = clk_get_rate(clk->parent);
1162         struct divider *d;
1163         u32 val, div, max_div, pred = 0, podf;
1164         int i, num;
1165
1166         if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
1167                 return ldb_di_clk_set_rate(clk, rate);
1168
1169         num = ARRAY_SIZE(dividers);
1170         for (i = 0; i < num; i++)
1171                 if (dividers[i]->clk == clk) {
1172                         d = dividers[i];
1173                         break;
1174                 }
1175         if (i == num)
1176                 return -EINVAL;
1177
1178         max_div = ((d->bm_pred >> d->bp_pred) + 1) *
1179                   ((d->bm_podf >> d->bp_podf) + 1);
1180
1181         div = parent_rate / rate;
1182         if (div == 0)
1183                 div++;
1184
1185         if ((parent_rate / div != rate) || div > max_div)
1186                 return -EINVAL;
1187
1188         if (d->bm_pred) {
1189                 calc_pred_podf_dividers(div, &pred, &podf);
1190         } else {
1191                 pred = 1;
1192                 podf = div;
1193         }
1194
1195         val = readl_relaxed(d->reg);
1196         val &= ~(d->bm_pred | d->bm_podf);
1197         val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf;
1198         writel_relaxed(val, d->reg);
1199
1200         if (clk == &axi_clk || clk == &ahb_clk ||
1201             clk == &mmdc_ch0_axi_clk || clk == &arm_clk)
1202                 return clk_busy_wait(clk);
1203
1204         return 0;
1205 }
1206
1207 static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate)
1208 {
1209         unsigned long parent_rate = clk_get_rate(clk->parent);
1210         u32 div = parent_rate / rate;
1211         u32 div_max, pred = 0, podf;
1212         struct divider *d;
1213         int i, num;
1214
1215         if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
1216                 return ldb_di_clk_round_rate(clk, rate);
1217
1218         num = ARRAY_SIZE(dividers);
1219         for (i = 0; i < num; i++)
1220                 if (dividers[i]->clk == clk) {
1221                         d = dividers[i];
1222                         break;
1223                 }
1224         if (i == num)
1225                 return -EINVAL;
1226
1227         if (div == 0 || parent_rate % rate)
1228                 div++;
1229
1230         if (d->bm_pred) {
1231                 calc_pred_podf_dividers(div, &pred, &podf);
1232                 div = pred * podf;
1233         } else {
1234                 div_max = (d->bm_podf >> d->bp_podf) + 1;
1235                 if (div > div_max)
1236                         div = div_max;
1237         }
1238
1239         return parent_rate / div;
1240 }
1241
1242 struct multiplexer {
1243         struct clk *clk;
1244         void __iomem *reg;
1245         u32 bp;
1246         u32 bm;
1247         int pnum;
1248         struct clk *parents[];
1249 };
1250
1251 static struct multiplexer axi_mux = {
1252         .clk = &axi_clk,
1253         .reg = CBCDR,
1254         .bp = BP_CBCDR_AXI_SEL,
1255         .bm = BM_CBCDR_AXI_SEL,
1256         .parents = {
1257                 &periph_clk,
1258                 &pll2_pfd_400m,
1259                 &pll3_pfd_540m,
1260                 NULL
1261         },
1262 };
1263
1264 static struct multiplexer periph_mux = {
1265         .clk = &periph_clk,
1266         .reg = CBCDR,
1267         .bp = BP_CBCDR_PERIPH_CLK_SEL,
1268         .bm = BM_CBCDR_PERIPH_CLK_SEL,
1269         .parents = {
1270                 &periph_pre_clk,
1271                 &periph_clk2_clk,
1272                 NULL
1273         },
1274 };
1275
1276 static struct multiplexer periph_pre_mux = {
1277         .clk = &periph_pre_clk,
1278         .reg = CBCMR,
1279         .bp = BP_CBCMR_PRE_PERIPH_CLK_SEL,
1280         .bm = BM_CBCMR_PRE_PERIPH_CLK_SEL,
1281         .parents = {
1282                 &pll2_bus,
1283                 &pll2_pfd_400m,
1284                 &pll2_pfd_352m,
1285                 &pll2_200m,
1286                 NULL
1287         },
1288 };
1289
1290 static struct multiplexer periph_clk2_mux = {
1291         .clk = &periph_clk2_clk,
1292         .reg = CBCMR,
1293         .bp = BP_CBCMR_PERIPH_CLK2_SEL,
1294         .bm = BM_CBCMR_PERIPH_CLK2_SEL,
1295         .parents = {
1296                 &pll3_usb_otg,
1297                 &osc_clk,
1298                 NULL
1299         },
1300 };
1301
1302 static struct multiplexer periph2_mux = {
1303         .clk = &periph2_clk,
1304         .reg = CBCDR,
1305         .bp = BP_CBCDR_PERIPH2_CLK_SEL,
1306         .bm = BM_CBCDR_PERIPH2_CLK_SEL,
1307         .parents = {
1308                 &periph2_pre_clk,
1309                 &periph2_clk2_clk,
1310                 NULL
1311         },
1312 };
1313
1314 static struct multiplexer periph2_pre_mux = {
1315         .clk = &periph2_pre_clk,
1316         .reg = CBCMR,
1317         .bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL,
1318         .bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL,
1319         .parents = {
1320                 &pll2_bus,
1321                 &pll2_pfd_400m,
1322                 &pll2_pfd_352m,
1323                 &pll2_200m,
1324                 NULL
1325         },
1326 };
1327
1328 static struct multiplexer periph2_clk2_mux = {
1329         .clk = &periph2_clk2_clk,
1330         .reg = CBCMR,
1331         .bp = BP_CBCMR_PERIPH2_CLK2_SEL,
1332         .bm = BM_CBCMR_PERIPH2_CLK2_SEL,
1333         .parents = {
1334                 &pll3_usb_otg,
1335                 &osc_clk,
1336                 NULL
1337         },
1338 };
1339
1340 static struct multiplexer gpu2d_axi_mux = {
1341         .clk = &gpu2d_axi_clk,
1342         .reg = CBCMR,
1343         .bp = BP_CBCMR_GPU2D_AXI_SEL,
1344         .bm = BM_CBCMR_GPU2D_AXI_SEL,
1345         .parents = {
1346                 &axi_clk,
1347                 &ahb_clk,
1348                 NULL
1349         },
1350 };
1351
1352 static struct multiplexer gpu3d_axi_mux = {
1353         .clk = &gpu3d_axi_clk,
1354         .reg = CBCMR,
1355         .bp = BP_CBCMR_GPU3D_AXI_SEL,
1356         .bm = BM_CBCMR_GPU3D_AXI_SEL,
1357         .parents = {
1358                 &axi_clk,
1359                 &ahb_clk,
1360                 NULL
1361         },
1362 };
1363
1364 static struct multiplexer gpu3d_core_mux = {
1365         .clk = &gpu3d_core_clk,
1366         .reg = CBCMR,
1367         .bp = BP_CBCMR_GPU3D_CORE_SEL,
1368         .bm = BM_CBCMR_GPU3D_CORE_SEL,
1369         .parents = {
1370                 &mmdc_ch0_axi_clk,
1371                 &pll3_usb_otg,
1372                 &pll2_pfd_594m,
1373                 &pll2_pfd_400m,
1374                 NULL
1375         },
1376 };
1377
1378 static struct multiplexer gpu3d_shader_mux = {
1379         .clk = &gpu3d_shader_clk,
1380         .reg = CBCMR,
1381         .bp = BP_CBCMR_GPU3D_SHADER_SEL,
1382         .bm = BM_CBCMR_GPU3D_SHADER_SEL,
1383         .parents = {
1384                 &mmdc_ch0_axi_clk,
1385                 &pll3_usb_otg,
1386                 &pll2_pfd_594m,
1387                 &pll3_pfd_720m,
1388                 NULL
1389         },
1390 };
1391
1392 static struct multiplexer pcie_axi_mux = {
1393         .clk = &pcie_clk,
1394         .reg = CBCMR,
1395         .bp = BP_CBCMR_PCIE_AXI_SEL,
1396         .bm = BM_CBCMR_PCIE_AXI_SEL,
1397         .parents = {
1398                 &axi_clk,
1399                 &ahb_clk,
1400                 NULL
1401         },
1402 };
1403
1404 static struct multiplexer vdo_axi_mux = {
1405         .clk = &vdo_axi_clk,
1406         .reg = CBCMR,
1407         .bp = BP_CBCMR_VDO_AXI_SEL,
1408         .bm = BM_CBCMR_VDO_AXI_SEL,
1409         .parents = {
1410                 &axi_clk,
1411                 &ahb_clk,
1412                 NULL
1413         },
1414 };
1415
1416 static struct multiplexer vpu_axi_mux = {
1417         .clk = &vpu_clk,
1418         .reg = CBCMR,
1419         .bp = BP_CBCMR_VPU_AXI_SEL,
1420         .bm = BM_CBCMR_VPU_AXI_SEL,
1421         .parents = {
1422                 &axi_clk,
1423                 &pll2_pfd_400m,
1424                 &pll2_pfd_352m,
1425                 NULL
1426         },
1427 };
1428
1429 static struct multiplexer gpu2d_core_mux = {
1430         .clk = &gpu2d_core_clk,
1431         .reg = CBCMR,
1432         .bp = BP_CBCMR_GPU2D_CORE_SEL,
1433         .bm = BM_CBCMR_GPU2D_CORE_SEL,
1434         .parents = {
1435                 &axi_clk,
1436                 &pll3_usb_otg,
1437                 &pll2_pfd_352m,
1438                 &pll2_pfd_400m,
1439                 NULL
1440         },
1441 };
1442
1443 #define DEF_SSI_MUX(id)                                                 \
1444         static struct multiplexer ssi##id##_mux = {                     \
1445                 .clk = &ssi##id##_clk,                                  \
1446                 .reg = CSCMR1,                                          \
1447                 .bp = BP_CSCMR1_SSI##id##_SEL,                          \
1448                 .bm = BM_CSCMR1_SSI##id##_SEL,                          \
1449                 .parents = {                                            \
1450                         &pll3_pfd_508m,                                 \
1451                         &pll3_pfd_454m,                                 \
1452                         &pll4_audio,                                    \
1453                         NULL                                            \
1454                 },                                                      \
1455         }
1456
1457 DEF_SSI_MUX(1);
1458 DEF_SSI_MUX(2);
1459 DEF_SSI_MUX(3);
1460
1461 #define DEF_USDHC_MUX(id)                                               \
1462         static struct multiplexer usdhc##id##_mux = {                   \
1463                 .clk = &usdhc##id##_clk,                                \
1464                 .reg = CSCMR1,                                          \
1465                 .bp = BP_CSCMR1_USDHC##id##_SEL,                        \
1466                 .bm = BM_CSCMR1_USDHC##id##_SEL,                        \
1467                 .parents = {                                            \
1468                         &pll2_pfd_400m,                                 \
1469                         &pll2_pfd_352m,                                 \
1470                         NULL                                            \
1471                 },                                                      \
1472         }
1473
1474 DEF_USDHC_MUX(1);
1475 DEF_USDHC_MUX(2);
1476 DEF_USDHC_MUX(3);
1477 DEF_USDHC_MUX(4);
1478
1479 static struct multiplexer emi_mux = {
1480         .clk = &emi_clk,
1481         .reg = CSCMR1,
1482         .bp = BP_CSCMR1_EMI_SEL,
1483         .bm = BM_CSCMR1_EMI_SEL,
1484         .parents = {
1485                 &axi_clk,
1486                 &pll3_usb_otg,
1487                 &pll2_pfd_400m,
1488                 &pll2_pfd_352m,
1489                 NULL
1490         },
1491 };
1492
1493 static struct multiplexer emi_slow_mux = {
1494         .clk = &emi_slow_clk,
1495         .reg = CSCMR1,
1496         .bp = BP_CSCMR1_EMI_SLOW_SEL,
1497         .bm = BM_CSCMR1_EMI_SLOW_SEL,
1498         .parents = {
1499                 &axi_clk,
1500                 &pll3_usb_otg,
1501                 &pll2_pfd_400m,
1502                 &pll2_pfd_352m,
1503                 NULL
1504         },
1505 };
1506
1507 static struct multiplexer esai_mux = {
1508         .clk = &esai_clk,
1509         .reg = CSCMR2,
1510         .bp = BP_CSCMR2_ESAI_SEL,
1511         .bm = BM_CSCMR2_ESAI_SEL,
1512         .parents = {
1513                 &pll4_audio,
1514                 &pll3_pfd_508m,
1515                 &pll3_pfd_454m,
1516                 &pll3_usb_otg,
1517                 NULL
1518         },
1519 };
1520
1521 #define DEF_LDB_DI_MUX(id)                                              \
1522         static struct multiplexer ldb_di##id##_mux = {                  \
1523                 .clk = &ldb_di##id##_clk,                               \
1524                 .reg = CS2CDR,                                          \
1525                 .bp = BP_CS2CDR_LDB_DI##id##_SEL,                       \
1526                 .bm = BM_CS2CDR_LDB_DI##id##_SEL,                       \
1527                 .parents = {                                            \
1528                         &pll5_video,                                    \
1529                         &pll2_pfd_352m,                                 \
1530                         &pll2_pfd_400m,                                 \
1531                         &pll3_pfd_540m,                                 \
1532                         &pll3_usb_otg,                                  \
1533                         NULL                                            \
1534                 },                                                      \
1535         }
1536
1537 DEF_LDB_DI_MUX(0);
1538 DEF_LDB_DI_MUX(1);
1539
1540 static struct multiplexer enfc_mux = {
1541         .clk = &enfc_clk,
1542         .reg = CS2CDR,
1543         .bp = BP_CS2CDR_ENFC_SEL,
1544         .bm = BM_CS2CDR_ENFC_SEL,
1545         .parents = {
1546                 &pll2_pfd_352m,
1547                 &pll2_bus,
1548                 &pll3_usb_otg,
1549                 &pll2_pfd_400m,
1550                 NULL
1551         },
1552 };
1553
1554 static struct multiplexer spdif_mux = {
1555         .clk = &spdif_clk,
1556         .reg = CDCDR,
1557         .bp = BP_CDCDR_SPDIF_SEL,
1558         .bm = BM_CDCDR_SPDIF_SEL,
1559         .parents = {
1560                 &pll4_audio,
1561                 &pll3_pfd_508m,
1562                 &pll3_pfd_454m,
1563                 &pll3_usb_otg,
1564                 NULL
1565         },
1566 };
1567
1568 static struct multiplexer asrc_serial_mux = {
1569         .clk = &asrc_serial_clk,
1570         .reg = CDCDR,
1571         .bp = BP_CDCDR_ASRC_SERIAL_SEL,
1572         .bm = BM_CDCDR_ASRC_SERIAL_SEL,
1573         .parents = {
1574                 &pll4_audio,
1575                 &pll3_pfd_508m,
1576                 &pll3_pfd_454m,
1577                 &pll3_usb_otg,
1578                 NULL
1579         },
1580 };
1581
1582 static struct multiplexer hsi_tx_mux = {
1583         .clk = &hsi_tx_clk,
1584         .reg = CDCDR,
1585         .bp = BP_CDCDR_HSI_TX_SEL,
1586         .bm = BM_CDCDR_HSI_TX_SEL,
1587         .parents = {
1588                 &pll3_120m,
1589                 &pll2_pfd_400m,
1590                 NULL
1591         },
1592 };
1593
1594 #define DEF_IPU_DI_PRE_MUX(r, i, d)                                     \
1595         static struct multiplexer ipu##i##_di##d##_pre_mux = {          \
1596                 .clk = &ipu##i##_di##d##_pre_clk,                       \
1597                 .reg = r,                                               \
1598                 .bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL,                \
1599                 .bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL,                \
1600                 .parents = {                                            \
1601                         &mmdc_ch0_axi_clk,                              \
1602                         &pll3_usb_otg,                                  \
1603                         &pll5_video,                                    \
1604                         &pll2_pfd_352m,                                 \
1605                         &pll2_pfd_400m,                                 \
1606                         &pll3_pfd_540m,                                 \
1607                         NULL                                            \
1608                 },                                                      \
1609         }
1610
1611 DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0);
1612 DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1);
1613 DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0);
1614 DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1);
1615
1616 #define DEF_IPU_DI_MUX(r, i, d)                                         \
1617         static struct multiplexer ipu##i##_di##d##_mux = {              \
1618                 .clk = &ipu##i##_di##d##_clk,                           \
1619                 .reg = r,                                               \
1620                 .bp = BP_##r##_IPU##i##_DI##d##_SEL,                    \
1621                 .bm = BM_##r##_IPU##i##_DI##d##_SEL,                    \
1622                 .parents = {                                            \
1623                         &ipu##i##_di##d##_pre_clk,                      \
1624                         &dummy_clk,                                     \
1625                         &dummy_clk,                                     \
1626                         &ldb_di0_clk,                                   \
1627                         &ldb_di1_clk,                                   \
1628                         NULL                                            \
1629                 },                                                      \
1630         }
1631
1632 DEF_IPU_DI_MUX(CHSCCDR, 1, 0);
1633 DEF_IPU_DI_MUX(CHSCCDR, 1, 1);
1634 DEF_IPU_DI_MUX(CSCDR2, 2, 0);
1635 DEF_IPU_DI_MUX(CSCDR2, 2, 1);
1636
1637 #define DEF_IPU_MUX(id)                                                 \
1638         static struct multiplexer ipu##id##_mux = {                     \
1639                 .clk = &ipu##id##_clk,                                  \
1640                 .reg = CSCDR3,                                          \
1641                 .bp = BP_CSCDR3_IPU##id##_HSP_SEL,                      \
1642                 .bm = BM_CSCDR3_IPU##id##_HSP_SEL,                      \
1643                 .parents = {                                            \
1644                         &mmdc_ch0_axi_clk,                              \
1645                         &pll2_pfd_400m,                                 \
1646                         &pll3_120m,                                     \
1647                         &pll3_pfd_540m,                                 \
1648                         NULL                                            \
1649                 },                                                      \
1650         }
1651
1652 DEF_IPU_MUX(1);
1653 DEF_IPU_MUX(2);
1654
1655 static struct multiplexer cko1_mux = {
1656         .clk = &cko1_clk,
1657         .reg = CCOSR,
1658         .bp = BP_CCOSR_CKO1_SEL,
1659         .bm = BM_CCOSR_CKO1_SEL,
1660         .parents = {
1661                 &pll3_usb_otg,
1662                 &pll2_bus,
1663                 &pll1_sys,
1664                 &pll5_video,
1665                 &dummy_clk,
1666                 &axi_clk,
1667                 &enfc_clk,
1668                 &ipu1_di0_clk,
1669                 &ipu1_di1_clk,
1670                 &ipu2_di0_clk,
1671                 &ipu2_di1_clk,
1672                 &ahb_clk,
1673                 &ipg_clk,
1674                 &ipg_perclk,
1675                 &ckil_clk,
1676                 &pll4_audio,
1677                 NULL
1678         },
1679 };
1680
1681 static struct multiplexer *multiplexers[] = {
1682         &axi_mux,
1683         &periph_mux,
1684         &periph_pre_mux,
1685         &periph_clk2_mux,
1686         &periph2_mux,
1687         &periph2_pre_mux,
1688         &periph2_clk2_mux,
1689         &gpu2d_axi_mux,
1690         &gpu3d_axi_mux,
1691         &gpu3d_core_mux,
1692         &gpu3d_shader_mux,
1693         &pcie_axi_mux,
1694         &vdo_axi_mux,
1695         &vpu_axi_mux,
1696         &gpu2d_core_mux,
1697         &ssi1_mux,
1698         &ssi2_mux,
1699         &ssi3_mux,
1700         &usdhc1_mux,
1701         &usdhc2_mux,
1702         &usdhc3_mux,
1703         &usdhc4_mux,
1704         &emi_mux,
1705         &emi_slow_mux,
1706         &esai_mux,
1707         &ldb_di0_mux,
1708         &ldb_di1_mux,
1709         &enfc_mux,
1710         &spdif_mux,
1711         &asrc_serial_mux,
1712         &hsi_tx_mux,
1713         &ipu1_di0_pre_mux,
1714         &ipu1_di0_mux,
1715         &ipu1_di1_pre_mux,
1716         &ipu1_di1_mux,
1717         &ipu2_di0_pre_mux,
1718         &ipu2_di0_mux,
1719         &ipu2_di1_pre_mux,
1720         &ipu2_di1_mux,
1721         &ipu1_mux,
1722         &ipu2_mux,
1723         &cko1_mux,
1724 };
1725
1726 static int _clk_set_parent(struct clk *clk, struct clk *parent)
1727 {
1728         struct multiplexer *m;
1729         int i, num;
1730         u32 val;
1731
1732         num = ARRAY_SIZE(multiplexers);
1733         for (i = 0; i < num; i++)
1734                 if (multiplexers[i]->clk == clk) {
1735                         m = multiplexers[i];
1736                         break;
1737                 }
1738         if (i == num)
1739                 return -EINVAL;
1740
1741         i = 0;
1742         while (m->parents[i]) {
1743                 if (parent == m->parents[i])
1744                         break;
1745                 i++;
1746         }
1747         if (!m->parents[i] || m->parents[i] == &dummy_clk)
1748                 return -EINVAL;
1749
1750         val = readl_relaxed(m->reg);
1751         val &= ~m->bm;
1752         val |= i << m->bp;
1753         writel_relaxed(val, m->reg);
1754
1755         if (clk == &periph_clk)
1756                 return clk_busy_wait(clk);
1757
1758         return 0;
1759 }
1760
1761 #define DEF_NG_CLK(name, p)                             \
1762         static struct clk name = {                      \
1763                 .get_rate       = _clk_get_rate,        \
1764                 .set_rate       = _clk_set_rate,        \
1765                 .round_rate     = _clk_round_rate,      \
1766                 .set_parent     = _clk_set_parent,      \
1767                 .parent         = p,                    \
1768         }
1769
1770 DEF_NG_CLK(periph_clk2_clk,     &osc_clk);
1771 DEF_NG_CLK(periph_pre_clk,      &pll2_bus);
1772 DEF_NG_CLK(periph_clk,          &periph_pre_clk);
1773 DEF_NG_CLK(periph2_clk2_clk,    &osc_clk);
1774 DEF_NG_CLK(periph2_pre_clk,     &pll2_bus);
1775 DEF_NG_CLK(periph2_clk,         &periph2_pre_clk);
1776 DEF_NG_CLK(axi_clk,             &periph_clk);
1777 DEF_NG_CLK(emi_clk,             &axi_clk);
1778 DEF_NG_CLK(arm_clk,             &pll1_sw_clk);
1779 DEF_NG_CLK(ahb_clk,             &periph_clk);
1780 DEF_NG_CLK(ipg_clk,             &ahb_clk);
1781 DEF_NG_CLK(ipg_perclk,          &ipg_clk);
1782 DEF_NG_CLK(ipu1_di0_pre_clk,    &pll3_pfd_540m);
1783 DEF_NG_CLK(ipu1_di1_pre_clk,    &pll3_pfd_540m);
1784 DEF_NG_CLK(ipu2_di0_pre_clk,    &pll3_pfd_540m);
1785 DEF_NG_CLK(ipu2_di1_pre_clk,    &pll3_pfd_540m);
1786 DEF_NG_CLK(asrc_serial_clk,     &pll3_usb_otg);
1787
1788 #define DEF_CLK(name, er, es, p, s)                     \
1789         static struct clk name = {                      \
1790                 .enable_reg     = er,                   \
1791                 .enable_shift   = es,                   \
1792                 .enable         = _clk_enable,          \
1793                 .disable        = _clk_disable,         \
1794                 .get_rate       = _clk_get_rate,        \
1795                 .set_rate       = _clk_set_rate,        \
1796                 .round_rate     = _clk_round_rate,      \
1797                 .set_parent     = _clk_set_parent,      \
1798                 .parent         = p,                    \
1799                 .secondary      = s,                    \
1800         }
1801
1802 #define DEF_CLK_1B(name, er, es, p, s)                  \
1803         static struct clk name = {                      \
1804                 .enable_reg     = er,                   \
1805                 .enable_shift   = es,                   \
1806                 .enable         = _clk_enable_1b,       \
1807                 .disable        = _clk_disable_1b,      \
1808                 .get_rate       = _clk_get_rate,        \
1809                 .set_rate       = _clk_set_rate,        \
1810                 .round_rate     = _clk_round_rate,      \
1811                 .set_parent     = _clk_set_parent,      \
1812                 .parent         = p,                    \
1813                 .secondary      = s,                    \
1814         }
1815
1816 DEF_CLK(aips_tz1_clk,     CCGR0, CG0,  &ahb_clk,          NULL);
1817 DEF_CLK(aips_tz2_clk,     CCGR0, CG1,  &ahb_clk,          NULL);
1818 DEF_CLK(apbh_dma_clk,     CCGR0, CG2,  &ahb_clk,          NULL);
1819 DEF_CLK(asrc_clk,         CCGR0, CG3,  &pll4_audio,       NULL);
1820 DEF_CLK(can1_serial_clk,  CCGR0, CG8,  &pll3_usb_otg,     NULL);
1821 DEF_CLK(can1_clk,         CCGR0, CG7,  &pll3_usb_otg,     &can1_serial_clk);
1822 DEF_CLK(can2_serial_clk,  CCGR0, CG10, &pll3_usb_otg,     NULL);
1823 DEF_CLK(can2_clk,         CCGR0, CG9,  &pll3_usb_otg,     &can2_serial_clk);
1824 DEF_CLK(ecspi1_clk,       CCGR1, CG0,  &pll3_60m,         NULL);
1825 DEF_CLK(ecspi2_clk,       CCGR1, CG1,  &pll3_60m,         NULL);
1826 DEF_CLK(ecspi3_clk,       CCGR1, CG2,  &pll3_60m,         NULL);
1827 DEF_CLK(ecspi4_clk,       CCGR1, CG3,  &pll3_60m,         NULL);
1828 DEF_CLK(ecspi5_clk,       CCGR1, CG4,  &pll3_60m,         NULL);
1829 DEF_CLK(enet_clk,         CCGR1, CG5,  &ipg_clk,          NULL);
1830 DEF_CLK(esai_clk,         CCGR1, CG8,  &pll3_usb_otg,     NULL);
1831 DEF_CLK(gpt_serial_clk,   CCGR1, CG11, &ipg_perclk,       NULL);
1832 DEF_CLK(gpt_clk,          CCGR1, CG10, &ipg_perclk,       &gpt_serial_clk);
1833 DEF_CLK(gpu2d_core_clk,   CCGR1, CG12, &pll2_pfd_352m,    &gpu2d_axi_clk);
1834 DEF_CLK(gpu3d_core_clk,   CCGR1, CG13, &pll2_pfd_594m,    &gpu3d_axi_clk);
1835 DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m,    &gpu3d_axi_clk);
1836 DEF_CLK(hdmi_iahb_clk,    CCGR2, CG0,  &ahb_clk,          NULL);
1837 DEF_CLK(hdmi_isfr_clk,    CCGR2, CG2,  &pll3_pfd_540m,    &hdmi_iahb_clk);
1838 DEF_CLK(i2c1_clk,         CCGR2, CG3,  &ipg_perclk,       NULL);
1839 DEF_CLK(i2c2_clk,         CCGR2, CG4,  &ipg_perclk,       NULL);
1840 DEF_CLK(i2c3_clk,         CCGR2, CG5,  &ipg_perclk,       NULL);
1841 DEF_CLK(iim_clk,          CCGR2, CG6,  &ipg_clk,          NULL);
1842 DEF_CLK(enfc_clk,         CCGR2, CG7,  &pll2_pfd_352m,    NULL);
1843 DEF_CLK(ipu1_clk,         CCGR3, CG0,  &mmdc_ch0_axi_clk, NULL);
1844 DEF_CLK(ipu1_di0_clk,     CCGR3, CG1,  &ipu1_di0_pre_clk, NULL);
1845 DEF_CLK(ipu1_di1_clk,     CCGR3, CG2,  &ipu1_di1_pre_clk, NULL);
1846 DEF_CLK(ipu2_clk,         CCGR3, CG3,  &mmdc_ch0_axi_clk, NULL);
1847 DEF_CLK(ipu2_di0_clk,     CCGR3, CG4,  &ipu2_di0_pre_clk, NULL);
1848 DEF_CLK(ipu2_di1_clk,     CCGR3, CG5,  &ipu2_di1_pre_clk, NULL);
1849 DEF_CLK(ldb_di0_clk,      CCGR3, CG6,  &pll3_pfd_540m,    NULL);
1850 DEF_CLK(ldb_di1_clk,      CCGR3, CG7,  &pll3_pfd_540m,    NULL);
1851 DEF_CLK(hsi_tx_clk,       CCGR3, CG8,  &pll2_pfd_400m,    NULL);
1852 DEF_CLK(mlb_clk,          CCGR3, CG9,  &pll6_mlb,         NULL);
1853 DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk,          NULL);
1854 DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk,       &mmdc_ch0_ipg_clk);
1855 DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk,          NULL);
1856 DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk,      &mmdc_ch1_ipg_clk);
1857 DEF_CLK(openvg_axi_clk,   CCGR3, CG13, &axi_clk,          NULL);
1858 DEF_CLK(pwm1_clk,         CCGR4, CG8,  &ipg_perclk,       NULL);
1859 DEF_CLK(pwm2_clk,         CCGR4, CG9,  &ipg_perclk,       NULL);
1860 DEF_CLK(pwm3_clk,         CCGR4, CG10, &ipg_perclk,       NULL);
1861 DEF_CLK(pwm4_clk,         CCGR4, CG11, &ipg_perclk,       NULL);
1862 DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk,       NULL);
1863 DEF_CLK(gpmi_bch_clk,     CCGR4, CG13, &usdhc4_clk,       &gpmi_bch_apb_clk);
1864 DEF_CLK(gpmi_apb_clk,     CCGR4, CG15, &usdhc3_clk,       &gpmi_bch_clk);
1865 DEF_CLK(gpmi_io_clk,      CCGR4, CG14, &enfc_clk,         &gpmi_apb_clk);
1866 DEF_CLK(sdma_clk,         CCGR5, CG3,  &ahb_clk,          NULL);
1867 DEF_CLK(spba_clk,         CCGR5, CG6,  &ipg_clk,          NULL);
1868 DEF_CLK(spdif_clk,        CCGR5, CG7,  &pll3_usb_otg,     &spba_clk);
1869 DEF_CLK(ssi1_clk,         CCGR5, CG9,  &pll3_pfd_508m,    NULL);
1870 DEF_CLK(ssi2_clk,         CCGR5, CG10, &pll3_pfd_508m,    NULL);
1871 DEF_CLK(ssi3_clk,         CCGR5, CG11, &pll3_pfd_508m,    NULL);
1872 DEF_CLK(uart_serial_clk,  CCGR5, CG13, &pll3_usb_otg,     NULL);
1873 DEF_CLK(uart_clk,         CCGR5, CG12, &pll3_80m,         &uart_serial_clk);
1874 DEF_CLK(usboh3_clk,       CCGR6, CG0,  &ipg_clk,          NULL);
1875 DEF_CLK(usdhc1_clk,       CCGR6, CG1,  &pll2_pfd_400m,    NULL);
1876 DEF_CLK(usdhc2_clk,       CCGR6, CG2,  &pll2_pfd_400m,    NULL);
1877 DEF_CLK(usdhc3_clk,       CCGR6, CG3,  &pll2_pfd_400m,    NULL);
1878 DEF_CLK(usdhc4_clk,       CCGR6, CG4,  &pll2_pfd_400m,    NULL);
1879 DEF_CLK(emi_slow_clk,     CCGR6, CG5,  &axi_clk,          NULL);
1880 DEF_CLK(vdo_axi_clk,      CCGR6, CG6,  &axi_clk,          NULL);
1881 DEF_CLK(vpu_clk,          CCGR6, CG7,  &axi_clk,          NULL);
1882 DEF_CLK_1B(cko1_clk,      CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
1883
1884 static int pcie_clk_enable(struct clk *clk)
1885 {
1886         u32 val;
1887
1888         val = readl_relaxed(PLL8_ENET);
1889         val |= BM_PLL_ENET_EN_PCIE;
1890         writel_relaxed(val, PLL8_ENET);
1891
1892         return _clk_enable(clk);
1893 }
1894
1895 static void pcie_clk_disable(struct clk *clk)
1896 {
1897         u32 val;
1898
1899         _clk_disable(clk);
1900
1901         val = readl_relaxed(PLL8_ENET);
1902         val &= BM_PLL_ENET_EN_PCIE;
1903         writel_relaxed(val, PLL8_ENET);
1904 }
1905
1906 static struct clk pcie_clk = {
1907         .enable_reg = CCGR4,
1908         .enable_shift = CG0,
1909         .enable = pcie_clk_enable,
1910         .disable = pcie_clk_disable,
1911         .set_parent = _clk_set_parent,
1912         .parent = &axi_clk,
1913         .secondary = &pll8_enet,
1914 };
1915
1916 static int sata_clk_enable(struct clk *clk)
1917 {
1918         u32 val;
1919
1920         val = readl_relaxed(PLL8_ENET);
1921         val |= BM_PLL_ENET_EN_SATA;
1922         writel_relaxed(val, PLL8_ENET);
1923
1924         return _clk_enable(clk);
1925 }
1926
1927 static void sata_clk_disable(struct clk *clk)
1928 {
1929         u32 val;
1930
1931         _clk_disable(clk);
1932
1933         val = readl_relaxed(PLL8_ENET);
1934         val &= BM_PLL_ENET_EN_SATA;
1935         writel_relaxed(val, PLL8_ENET);
1936 }
1937
1938 static struct clk sata_clk = {
1939         .enable_reg = CCGR5,
1940         .enable_shift = CG2,
1941         .enable = sata_clk_enable,
1942         .disable = sata_clk_disable,
1943         .parent = &ipg_clk,
1944         .secondary = &pll8_enet,
1945 };
1946
1947 #define _REGISTER_CLOCK(d, n, c) \
1948         { \
1949                 .dev_id = d, \
1950                 .con_id = n, \
1951                 .clk = &c, \
1952         }
1953
1954 static struct clk_lookup lookups[] = {
1955         _REGISTER_CLOCK("2020000.uart", NULL, uart_clk),
1956         _REGISTER_CLOCK("21e8000.uart", NULL, uart_clk),
1957         _REGISTER_CLOCK("21ec000.uart", NULL, uart_clk),
1958         _REGISTER_CLOCK("21f0000.uart", NULL, uart_clk),
1959         _REGISTER_CLOCK("21f4000.uart", NULL, uart_clk),
1960         _REGISTER_CLOCK("2188000.enet", NULL, enet_clk),
1961         _REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk),
1962         _REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk),
1963         _REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk),
1964         _REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk),
1965         _REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk),
1966         _REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk),
1967         _REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk),
1968         _REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk),
1969         _REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk),
1970         _REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk),
1971         _REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk),
1972         _REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk),
1973         _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
1974         _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
1975         _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
1976         _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
1977         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
1978         _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
1979         _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
1980         _REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk),
1981         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
1982         _REGISTER_CLOCK(NULL, "can2_clk", can2_clk),
1983         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk),
1984         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
1985         _REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
1986         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
1987         _REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk),
1988         _REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk),
1989         _REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk),
1990         _REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk),
1991         _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
1992         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
1993         _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
1994         _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
1995 };
1996
1997 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
1998 {
1999         u32 val = readl_relaxed(CLPCR);
2000
2001         val &= ~BM_CLPCR_LPM;
2002         switch (mode) {
2003         case WAIT_CLOCKED:
2004                 break;
2005         case WAIT_UNCLOCKED:
2006                 val |= 0x1 << BP_CLPCR_LPM;
2007                 break;
2008         case STOP_POWER_ON:
2009                 val |= 0x2 << BP_CLPCR_LPM;
2010                 break;
2011         case WAIT_UNCLOCKED_POWER_OFF:
2012                 val |= 0x1 << BP_CLPCR_LPM;
2013                 val &= ~BM_CLPCR_VSTBY;
2014                 val &= ~BM_CLPCR_SBYOS;
2015                 break;
2016         case STOP_POWER_OFF:
2017                 val |= 0x2 << BP_CLPCR_LPM;
2018                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
2019                 val |= BM_CLPCR_VSTBY;
2020                 val |= BM_CLPCR_SBYOS;
2021                 break;
2022         default:
2023                 return -EINVAL;
2024         }
2025         writel_relaxed(val, CLPCR);
2026
2027         return 0;
2028 }
2029
2030 static struct map_desc imx6q_clock_desc[] = {
2031         imx_map_entry(MX6Q, CCM, MT_DEVICE),
2032         imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
2033 };
2034
2035 void __init imx6q_clock_map_io(void)
2036 {
2037         iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
2038 }
2039
2040 int __init mx6q_clocks_init(void)
2041 {
2042         struct device_node *np;
2043         void __iomem *base;
2044         int i, irq;
2045
2046         /* retrieve the freqency of fixed clocks from device tree */
2047         for_each_compatible_node(np, NULL, "fixed-clock") {
2048                 u32 rate;
2049                 if (of_property_read_u32(np, "clock-frequency", &rate))
2050                         continue;
2051
2052                 if (of_device_is_compatible(np, "fsl,imx-ckil"))
2053                         external_low_reference = rate;
2054                 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
2055                         external_high_reference = rate;
2056                 else if (of_device_is_compatible(np, "fsl,imx-osc"))
2057                         oscillator_reference = rate;
2058         }
2059
2060         for (i = 0; i < ARRAY_SIZE(lookups); i++)
2061                 clkdev_add(&lookups[i]);
2062
2063         /* only keep necessary clocks on */
2064         writel_relaxed(0x3 << CG0  | 0x3 << CG1  | 0x3 << CG2,  CCGR0);
2065         writel_relaxed(0x3 << CG8  | 0x3 << CG9  | 0x3 << CG10, CCGR2);
2066         writel_relaxed(0x3 << CG10 | 0x3 << CG12,               CCGR3);
2067         writel_relaxed(0x3 << CG4  | 0x3 << CG6  | 0x3 << CG7,  CCGR4);
2068         writel_relaxed(0x3 << CG0,                              CCGR5);
2069         writel_relaxed(0,                                       CCGR6);
2070         writel_relaxed(0,                                       CCGR7);
2071
2072         clk_enable(&uart_clk);
2073         clk_enable(&mmdc_ch0_axi_clk);
2074
2075         clk_set_rate(&pll4_audio, FREQ_650M);
2076         clk_set_rate(&pll5_video, FREQ_650M);
2077         clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk);
2078         clk_set_parent(&ipu1_di0_pre_clk, &pll5_video);
2079         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m);
2080         clk_set_rate(&gpu3d_shader_clk, FREQ_594M);
2081         clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);
2082         clk_set_rate(&gpu3d_core_clk, FREQ_528M);
2083         clk_set_parent(&asrc_serial_clk, &pll3_usb_otg);
2084         clk_set_rate(&asrc_serial_clk, 1500000);
2085         clk_set_rate(&enfc_clk, 11000000);
2086
2087         /*
2088          * Before pinctrl API is available, we have to rely on the pad
2089          * configuration set up by bootloader.  For usdhc example here,
2090          * u-boot sets up the pads for 49.5 MHz case, and we have to lower
2091          * the usdhc clock from 198 to 49.5 MHz to match the pad configuration.
2092          *
2093          * FIXME: This is should be removed after pinctrl API is available.
2094          * At that time, usdhc driver can call pinctrl API to change pad
2095          * configuration dynamically per different usdhc clock settings.
2096          */
2097         clk_set_rate(&usdhc1_clk, 49500000);
2098         clk_set_rate(&usdhc2_clk, 49500000);
2099         clk_set_rate(&usdhc3_clk, 49500000);
2100         clk_set_rate(&usdhc4_clk, 49500000);
2101
2102         clk_set_parent(&cko1_clk, &ahb_clk);
2103
2104         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
2105         base = of_iomap(np, 0);
2106         WARN_ON(!base);
2107         irq = irq_of_parse_and_map(np, 0);
2108         mxc_timer_init(&gpt_clk, base, irq);
2109
2110         return 0;
2111 }