arch/arm/mach-exynos/suspend.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   4 //              http://www.samsung.com
   5 //
   6 // EXYNOS - Suspend support
   7 //
   8 // Based on arch/arm/mach-s3c2410/pm.c
   9 // Copyright (c) 2006 Simtec Electronics
  10 //      Ben Dooks <ben@simtec.co.uk>
  11
  12 #include <linux/init.h>
  13 #include <linux/suspend.h>
  14 #include <linux/syscore_ops.h>
  15 #include <linux/cpu_pm.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqchip.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/of_address.h>
  21 #include <linux/err.h>
  22 #include <linux/regulator/machine.h>
  23 #include <linux/soc/samsung/exynos-pmu.h>
  24 #include <linux/soc/samsung/exynos-regs-pmu.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/hardware/cache-l2x0.h>
  28 #include <asm/firmware.h>
  29 #include <asm/mcpm.h>
  30 #include <asm/smp_scu.h>
  31 #include <asm/suspend.h>
  32
  33 #include "common.h"
  34
  35 #define REG_TABLE_END (-1U)
  36
  37 #define EXYNOS5420_CPU_STATE    0x28
  38
  39 /**
  40  * struct exynos_wkup_irq - PMU IRQ to mask mapping
  41  * @hwirq: Hardware IRQ signal of the PMU
  42  * @mask: Mask in PMU wake-up mask register
  43  */
  44 struct exynos_wkup_irq {
  45         unsigned int hwirq;
  46         u32 mask;
  47 };
  48
  49 struct exynos_pm_data {
  50         const struct exynos_wkup_irq *wkup_irq;
  51         unsigned int wake_disable_mask;
  52
  53         void (*pm_prepare)(void);
  54         void (*pm_resume_prepare)(void);
  55         void (*pm_resume)(void);
  56         int (*pm_suspend)(void);
  57         int (*cpu_suspend)(unsigned long);
  58 };
  59
  60 /* Used only on Exynos542x/5800 */
  61 struct exynos_pm_state {
  62         int cpu_state;
  63         unsigned int pmu_spare3;
  64         void __iomem *sysram_base;
  65 };
  66
  67 static const struct exynos_pm_data *pm_data __ro_after_init;
  68 static struct exynos_pm_state pm_state;
  69
  70 /*
  71  * GIC wake-up support
  72  */
  73
  74 static u32 exynos_irqwake_intmask = 0xffffffff;
  75
  76 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
  77         { 73, BIT(1) }, /* RTC alarm */
  78         { 74, BIT(2) }, /* RTC tick */
  79         { /* sentinel */ },
  80 };
  81
  82 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  83         { 44, BIT(1) }, /* RTC alarm */
  84         { 45, BIT(2) }, /* RTC tick */
  85         { /* sentinel */ },
  86 };
  87
  88 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  89         { 43, BIT(1) }, /* RTC alarm */
  90         { 44, BIT(2) }, /* RTC tick */
  91         { /* sentinel */ },
  92 };
  93
  94 static u32 exynos_read_eint_wakeup_mask(void)
  95 {
  96         return pmu_raw_readl(EXYNOS_EINT_WAKEUP_MASK);
  97 }
  98
  99 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 100 {
 101         const struct exynos_wkup_irq *wkup_irq;
 102
 103         if (!pm_data->wkup_irq)
 104                 return -ENOENT;
 105         wkup_irq = pm_data->wkup_irq;
 106
 107         while (wkup_irq->mask) {
 108                 if (wkup_irq->hwirq == data->hwirq) {
 109                         if (!state)
 110                                 exynos_irqwake_intmask |= wkup_irq->mask;
 111                         else
 112                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
 113                         return 0;
 114                 }
 115                 ++wkup_irq;
 116         }
 117
 118         return -ENOENT;
 119 }
 120
 121 static struct irq_chip exynos_pmu_chip = {
 122         .name                   = "PMU",
 123         .irq_eoi                = irq_chip_eoi_parent,
 124         .irq_mask               = irq_chip_mask_parent,
 125         .irq_unmask             = irq_chip_unmask_parent,
 126         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 127         .irq_set_wake           = exynos_irq_set_wake,
 128 #ifdef CONFIG_SMP
 129         .irq_set_affinity       = irq_chip_set_affinity_parent,
 130 #endif
 131 };
 132
 133 static int exynos_pmu_domain_translate(struct irq_domain *d,
 134                                        struct irq_fwspec *fwspec,
 135                                        unsigned long *hwirq,
 136                                        unsigned int *type)
 137 {
 138         if (is_of_node(fwspec->fwnode)) {
 139                 if (fwspec->param_count != 3)
 140                         return -EINVAL;
 141
 142                 /* No PPI should point to this domain */
 143                 if (fwspec->param[0] != 0)
 144                         return -EINVAL;
 145
 146                 *hwirq = fwspec->param[1];
 147                 *type = fwspec->param[2];
 148                 return 0;
 149         }
 150
 151         return -EINVAL;
 152 }
 153
 154 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
 155                                    unsigned int virq,
 156                                    unsigned int nr_irqs, void *data)
 157 {
 158         struct irq_fwspec *fwspec = data;
 159         struct irq_fwspec parent_fwspec;
 160         irq_hw_number_t hwirq;
 161         int i;
 162
 163         if (fwspec->param_count != 3)
 164                 return -EINVAL; /* Not GIC compliant */
 165         if (fwspec->param[0] != 0)
 166                 return -EINVAL; /* No PPI should point to this domain */
 167
 168         hwirq = fwspec->param[1];
 169
 170         for (i = 0; i < nr_irqs; i++)
 171                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 172                                               &exynos_pmu_chip, NULL);
 173
 174         parent_fwspec = *fwspec;
 175         parent_fwspec.fwnode = domain->parent->fwnode;
 176         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 177                                             &parent_fwspec);
 178 }
 179
 180 static const struct irq_domain_ops exynos_pmu_domain_ops = {
 181         .translate      = exynos_pmu_domain_translate,
 182         .alloc          = exynos_pmu_domain_alloc,
 183         .free           = irq_domain_free_irqs_common,
 184 };
 185
 186 static int __init exynos_pmu_irq_init(struct device_node *node,
 187                                       struct device_node *parent)
 188 {
 189         struct irq_domain *parent_domain, *domain;
 190
 191         if (!parent) {
 192                 pr_err("%pOF: no parent, giving up\n", node);
 193                 return -ENODEV;
 194         }
 195
 196         parent_domain = irq_find_host(parent);
 197         if (!parent_domain) {
 198                 pr_err("%pOF: unable to obtain parent domain\n", node);
 199                 return -ENXIO;
 200         }
 201
 202         pmu_base_addr = of_iomap(node, 0);
 203
 204         if (!pmu_base_addr) {
 205                 pr_err("%pOF: failed to find exynos pmu register\n", node);
 206                 return -ENOMEM;
 207         }
 208
 209         domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
 210                                           node, &exynos_pmu_domain_ops,
 211                                           NULL);
 212         if (!domain) {
 213                 iounmap(pmu_base_addr);
 214                 pmu_base_addr = NULL;
 215                 return -ENOMEM;
 216         }
 217
 218         /*
 219          * Clear the OF_POPULATED flag set in of_irq_init so that
 220          * later the Exynos PMU platform device won't be skipped.
 221          */
 222         of_node_clear_flag(node, OF_POPULATED);
 223
 224         return 0;
 225 }
 226
 227 #define EXYNOS_PMU_IRQ(symbol, name)    IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
 228
 229 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
 230 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
 231 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
 232 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
 233 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
 234
 235 static int exynos_cpu_do_idle(void)
 236 {
 237         /* issue the standby signal into the pm unit. */
 238         cpu_do_idle();
 239
 240         pr_info("Failed to suspend the system\n");
 241         return 1; /* Aborting suspend */
 242 }
 243 static void exynos_flush_cache_all(void)
 244 {
 245         flush_cache_all();
 246         outer_flush_all();
 247 }
 248
 249 static int exynos_cpu_suspend(unsigned long arg)
 250 {
 251         exynos_flush_cache_all();
 252         return exynos_cpu_do_idle();
 253 }
 254
 255 static int exynos3250_cpu_suspend(unsigned long arg)
 256 {
 257         flush_cache_all();
 258         return exynos_cpu_do_idle();
 259 }
 260
 261 static int exynos5420_cpu_suspend(unsigned long arg)
 262 {
 263         /* MCPM works with HW CPU identifiers */
 264         unsigned int mpidr = read_cpuid_mpidr();
 265         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 266         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 267
 268         writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
 269
 270         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 271                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
 272                 mcpm_cpu_suspend();
 273         }
 274
 275         pr_info("Failed to suspend the system\n");
 276
 277         /* return value != 0 means failure */
 278         return 1;
 279 }
 280
 281 static void exynos_pm_set_wakeup_mask(void)
 282 {
 283         /*
 284          * Set wake-up mask registers
 285          * EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
 286          */
 287         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 288 }
 289
 290 static void exynos_pm_enter_sleep_mode(void)
 291 {
 292         /* Set value of power down register for sleep mode */
 293         exynos_sys_powerdown_conf(SYS_SLEEP);
 294         pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
 295 }
 296
 297 static void exynos_pm_prepare(void)
 298 {
 299         exynos_set_delayed_reset_assertion(false);
 300
 301         /* Set wake-up mask registers */
 302         exynos_pm_set_wakeup_mask();
 303
 304         exynos_pm_enter_sleep_mode();
 305
 306         /* ensure at least INFORM0 has the resume address */
 307         pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 308 }
 309
 310 static void exynos3250_pm_prepare(void)
 311 {
 312         unsigned int tmp;
 313
 314         /* Set wake-up mask registers */
 315         exynos_pm_set_wakeup_mask();
 316
 317         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
 318         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 319         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
 320
 321         exynos_pm_enter_sleep_mode();
 322
 323         /* ensure at least INFORM0 has the resume address */
 324         pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 325 }
 326
 327 static void exynos5420_pm_prepare(void)
 328 {
 329         unsigned int tmp;
 330
 331         /* Set wake-up mask registers */
 332         exynos_pm_set_wakeup_mask();
 333
 334         pm_state.pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
 335         /*
 336          * The cpu state needs to be saved and restored so that the
 337          * secondary CPUs will enter low power start. Though the U-Boot
 338          * is setting the cpu state with low power flag, the kernel
 339          * needs to restore it back in case, the primary cpu fails to
 340          * suspend for any reason.
 341          */
 342         pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
 343                                            EXYNOS5420_CPU_STATE);
 344
 345         exynos_pm_enter_sleep_mode();
 346
 347         /* ensure at least INFORM0 has the resume address */
 348         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 349                 pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
 350
 351         tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
 352         tmp &= ~EXYNOS_L2_USE_RETENTION;
 353         pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
 354
 355         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 356         tmp |= EXYNOS5420_UFS;
 357         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 358
 359         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 360         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
 361         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
 362
 363         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 364         tmp |= EXYNOS5420_EMULATION;
 365         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 366
 367         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 368         tmp |= EXYNOS5420_EMULATION;
 369         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 370 }
 371
 372
 373 static int exynos_pm_suspend(void)
 374 {
 375         exynos_pm_central_suspend();
 376
 377         /* Setting SEQ_OPTION register */
 378         pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
 379                        S5P_CENTRAL_SEQ_OPTION);
 380
 381         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 382                 exynos_cpu_save_register();
 383
 384         return 0;
 385 }
 386
 387 static int exynos5420_pm_suspend(void)
 388 {
 389         u32 this_cluster;
 390
 391         exynos_pm_central_suspend();
 392
 393         /* Setting SEQ_OPTION register */
 394
 395         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 396         if (!this_cluster)
 397                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
 398                                 S5P_CENTRAL_SEQ_OPTION);
 399         else
 400                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
 401                                 S5P_CENTRAL_SEQ_OPTION);
 402         return 0;
 403 }
 404
 405 static void exynos_pm_resume(void)
 406 {
 407         u32 cpuid = read_cpuid_part();
 408
 409         if (exynos_pm_central_resume())
 410                 goto early_wakeup;
 411
 412         if (cpuid == ARM_CPU_PART_CORTEX_A9)
 413                 exynos_scu_enable();
 414
 415         if (call_firmware_op(resume) == -ENOSYS
 416             && cpuid == ARM_CPU_PART_CORTEX_A9)
 417                 exynos_cpu_restore_register();
 418
 419 early_wakeup:
 420
 421         /* Clear SLEEP mode set in INFORM1 */
 422         pmu_raw_writel(0x0, S5P_INFORM1);
 423         exynos_set_delayed_reset_assertion(true);
 424 }
 425
 426 static void exynos3250_pm_resume(void)
 427 {
 428         u32 cpuid = read_cpuid_part();
 429
 430         if (exynos_pm_central_resume())
 431                 goto early_wakeup;
 432
 433         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 434
 435         if (call_firmware_op(resume) == -ENOSYS
 436             && cpuid == ARM_CPU_PART_CORTEX_A9)
 437                 exynos_cpu_restore_register();
 438
 439 early_wakeup:
 440
 441         /* Clear SLEEP mode set in INFORM1 */
 442         pmu_raw_writel(0x0, S5P_INFORM1);
 443 }
 444
 445 static void exynos5420_prepare_pm_resume(void)
 446 {
 447         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 448                 WARN_ON(mcpm_cpu_powered_up());
 449 }
 450
 451 static void exynos5420_pm_resume(void)
 452 {
 453         unsigned long tmp;
 454
 455         /* Restore the CPU0 low power state register */
 456         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 457         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
 458                        EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 459
 460         /* Restore the sysram cpu state register */
 461         writel_relaxed(pm_state.cpu_state,
 462                        pm_state.sysram_base + EXYNOS5420_CPU_STATE);
 463
 464         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 465                         S5P_CENTRAL_SEQ_OPTION);
 466
 467         if (exynos_pm_central_resume())
 468                 goto early_wakeup;
 469
 470         pmu_raw_writel(pm_state.pmu_spare3, S5P_PMU_SPARE3);
 471
 472 early_wakeup:
 473
 474         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 475         tmp &= ~EXYNOS5420_UFS;
 476         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 477
 478         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 479         tmp &= ~EXYNOS5420_EMULATION;
 480         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 481
 482         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 483         tmp &= ~EXYNOS5420_EMULATION;
 484         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 485
 486         /* Clear SLEEP mode set in INFORM1 */
 487         pmu_raw_writel(0x0, S5P_INFORM1);
 488 }
 489
 490 /*
 491  * Suspend Ops
 492  */
 493
 494 static int exynos_suspend_enter(suspend_state_t state)
 495 {
 496         u32 eint_wakeup_mask = exynos_read_eint_wakeup_mask();
 497         int ret;
 498
 499         pr_debug("%s: suspending the system...\n", __func__);
 500
 501         pr_debug("%s: wakeup masks: %08x,%08x\n", __func__,
 502                   exynos_irqwake_intmask, eint_wakeup_mask);
 503
 504         if (exynos_irqwake_intmask == -1U
 505             && eint_wakeup_mask == EXYNOS_EINT_WAKEUP_MASK_DISABLED) {
 506                 pr_err("%s: No wake-up sources!\n", __func__);
 507                 pr_err("%s: Aborting sleep\n", __func__);
 508                 return -EINVAL;
 509         }
 510
 511         if (pm_data->pm_prepare)
 512                 pm_data->pm_prepare();
 513         flush_cache_all();
 514
 515         ret = call_firmware_op(suspend);
 516         if (ret == -ENOSYS)
 517                 ret = cpu_suspend(0, pm_data->cpu_suspend);
 518         if (ret)
 519                 return ret;
 520
 521         if (pm_data->pm_resume_prepare)
 522                 pm_data->pm_resume_prepare();
 523
 524         pr_debug("%s: wakeup stat: %08x\n", __func__,
 525                         pmu_raw_readl(S5P_WAKEUP_STAT));
 526
 527         pr_debug("%s: resuming the system...\n", __func__);
 528
 529         return 0;
 530 }
 531
 532 static int exynos_suspend_prepare(void)
 533 {
 534         int ret;
 535
 536         /*
 537          * REVISIT: It would be better if struct platform_suspend_ops
 538          * .prepare handler get the suspend_state_t as a parameter to
 539          * avoid hard-coding the suspend to mem state. It's safe to do
 540          * it now only because the suspend_valid_only_mem function is
 541          * used as the .valid callback used to check if a given state
 542          * is supported by the platform anyways.
 543          */
 544         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
 545         if (ret) {
 546                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
 547                 return ret;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static void exynos_suspend_finish(void)
 554 {
 555         int ret;
 556
 557         ret = regulator_suspend_finish();
 558         if (ret)
 559                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
 560 }
 561
 562 static const struct platform_suspend_ops exynos_suspend_ops = {
 563         .enter          = exynos_suspend_enter,
 564         .prepare        = exynos_suspend_prepare,
 565         .finish         = exynos_suspend_finish,
 566         .valid          = suspend_valid_only_mem,
 567 };
 568
 569 static const struct exynos_pm_data exynos3250_pm_data = {
 570         .wkup_irq       = exynos3250_wkup_irq,
 571         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 572         .pm_suspend     = exynos_pm_suspend,
 573         .pm_resume      = exynos3250_pm_resume,
 574         .pm_prepare     = exynos3250_pm_prepare,
 575         .cpu_suspend    = exynos3250_cpu_suspend,
 576 };
 577
 578 static const struct exynos_pm_data exynos4_pm_data = {
 579         .wkup_irq       = exynos4_wkup_irq,
 580         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 581         .pm_suspend     = exynos_pm_suspend,
 582         .pm_resume      = exynos_pm_resume,
 583         .pm_prepare     = exynos_pm_prepare,
 584         .cpu_suspend    = exynos_cpu_suspend,
 585 };
 586
 587 static const struct exynos_pm_data exynos5250_pm_data = {
 588         .wkup_irq       = exynos5250_wkup_irq,
 589         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 590         .pm_suspend     = exynos_pm_suspend,
 591         .pm_resume      = exynos_pm_resume,
 592         .pm_prepare     = exynos_pm_prepare,
 593         .cpu_suspend    = exynos_cpu_suspend,
 594 };
 595
 596 static const struct exynos_pm_data exynos5420_pm_data = {
 597         .wkup_irq       = exynos5250_wkup_irq,
 598         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
 599         .pm_resume_prepare = exynos5420_prepare_pm_resume,
 600         .pm_resume      = exynos5420_pm_resume,
 601         .pm_suspend     = exynos5420_pm_suspend,
 602         .pm_prepare     = exynos5420_pm_prepare,
 603         .cpu_suspend    = exynos5420_cpu_suspend,
 604 };
 605
 606 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
 607         {
 608                 .compatible = "samsung,exynos3250-pmu",
 609                 .data = &exynos3250_pm_data,
 610         }, {
 611                 .compatible = "samsung,exynos4210-pmu",
 612                 .data = &exynos4_pm_data,
 613         }, {
 614                 .compatible = "samsung,exynos4412-pmu",
 615                 .data = &exynos4_pm_data,
 616         }, {
 617                 .compatible = "samsung,exynos5250-pmu",
 618                 .data = &exynos5250_pm_data,
 619         }, {
 620                 .compatible = "samsung,exynos5420-pmu",
 621                 .data = &exynos5420_pm_data,
 622         },
 623         { /*sentinel*/ },
 624 };
 625
 626 static struct syscore_ops exynos_pm_syscore_ops;
 627
 628 void __init exynos_pm_init(void)
 629 {
 630         const struct of_device_id *match;
 631         struct device_node *np;
 632         u32 tmp;
 633
 634         np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
 635         if (!np) {
 636                 pr_err("Failed to find PMU node\n");
 637                 return;
 638         }
 639
 640         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
 641                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
 642                 return;
 643         }
 644
 645         pm_data = (const struct exynos_pm_data *) match->data;
 646
 647         /* All wakeup disable */
 648         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 649         tmp |= pm_data->wake_disable_mask;
 650         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 651
 652         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
 653         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
 654
 655         register_syscore_ops(&exynos_pm_syscore_ops);
 656         suspend_set_ops(&exynos_suspend_ops);
 657
 658         /*
 659          * Applicable as of now only to Exynos542x. If booted under secure
 660          * firmware, the non-secure region of sysram should be used.
 661          */
 662         if (exynos_secure_firmware_available())
 663                 pm_state.sysram_base = sysram_ns_base_addr;
 664         else
 665                 pm_state.sysram_base = sysram_base_addr;
 666 }