arch/arm/mach-exynos/firmware.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics.
   3  * Kyungmin Park <kyungmin.park@samsung.com>
   4  * Tomasz Figa <t.figa@samsung.com>
   5  *
   6  * This program is free software,you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/io.h>
  13 #include <linux/init.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/cputype.h>
  19 #include <asm/firmware.h>
  20 #include <asm/hardware/cache-l2x0.h>
  21 #include <asm/suspend.h>
  22
  23 #include "common.h"
  24 #include "smc.h"
  25
  26 #define EXYNOS_BOOT_ADDR        0x8
  27 #define EXYNOS_BOOT_FLAG        0xc
  28
  29 static void exynos_save_cp15(void)
  30 {
  31         /* Save Power control and Diagnostic registers */
  32         asm ("mrc p15, 0, %0, c15, c0, 0\n"
  33              "mrc p15, 0, %1, c15, c0, 1\n"
  34              : "=r" (cp15_save_power), "=r" (cp15_save_diag)
  35              : : "cc");
  36 }
  37
  38 static int exynos_do_idle(unsigned long mode)
  39 {
  40         switch (mode) {
  41         case FW_DO_IDLE_AFTR:
  42                 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
  43                         exynos_save_cp15();
  44                 writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
  45                                sysram_ns_base_addr + 0x24);
  46                 writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
  47                 if (soc_is_exynos3250()) {
  48                         flush_cache_all();
  49                         exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
  50                                    SMC_POWERSTATE_IDLE, 0);
  51                         exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
  52                                    SMC_POWERSTATE_IDLE, 0);
  53                 } else
  54                         exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
  55                 break;
  56         case FW_DO_IDLE_SLEEP:
  57                 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
  58         }
  59         return 0;
  60 }
  61
  62 static int exynos_cpu_boot(int cpu)
  63 {
  64         /*
  65          * Exynos3250 doesn't need to send smc command for secondary CPU boot
  66          * because Exynos3250 removes WFE in secure mode.
  67          */
  68         if (soc_is_exynos3250())
  69                 return 0;
  70
  71         /*
  72          * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
  73          */
  74         exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
  75         return 0;
  76 }
  77
  78 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
  79 {
  80         void __iomem *boot_reg;
  81
  82         if (!sysram_ns_base_addr)
  83                 return -ENODEV;
  84
  85         boot_reg = sysram_ns_base_addr + 0x1c;
  86
  87         /*
  88          * Almost all Exynos-series of SoCs that run in secure mode don't need
  89          * additional offset for every CPU, with Exynos4412 being the only
  90          * exception.
  91          */
  92         if (soc_is_exynos4412())
  93                 boot_reg += 4 * cpu;
  94
  95         writel_relaxed(boot_addr, boot_reg);
  96         return 0;
  97 }
  98
  99 static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
 100 {
 101         void __iomem *boot_reg;
 102
 103         if (!sysram_ns_base_addr)
 104                 return -ENODEV;
 105
 106         boot_reg = sysram_ns_base_addr + 0x1c;
 107
 108         if (soc_is_exynos4412())
 109                 boot_reg += 4 * cpu;
 110
 111         *boot_addr = readl_relaxed(boot_reg);
 112         return 0;
 113 }
 114
 115 static int exynos_cpu_suspend(unsigned long arg)
 116 {
 117         flush_cache_all();
 118         outer_flush_all();
 119
 120         exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
 121
 122         pr_info("Failed to suspend the system\n");
 123         writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
 124         return 1;
 125 }
 126
 127 static int exynos_suspend(void)
 128 {
 129         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 130                 exynos_save_cp15();
 131
 132         writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
 133         writel(__pa_symbol(exynos_cpu_resume_ns),
 134                 sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
 135
 136         return cpu_suspend(0, exynos_cpu_suspend);
 137 }
 138
 139 static int exynos_resume(void)
 140 {
 141         writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
 142
 143         return 0;
 144 }
 145
 146 static const struct firmware_ops exynos_firmware_ops = {
 147         .do_idle                = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
 148         .set_cpu_boot_addr      = exynos_set_cpu_boot_addr,
 149         .get_cpu_boot_addr      = exynos_get_cpu_boot_addr,
 150         .cpu_boot               = exynos_cpu_boot,
 151         .suspend                = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
 152         .resume                 = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
 153 };
 154
 155 static void exynos_l2_write_sec(unsigned long val, unsigned reg)
 156 {
 157         static int l2cache_enabled;
 158
 159         switch (reg) {
 160         case L2X0_CTRL:
 161                 if (val & L2X0_CTRL_EN) {
 162                         /*
 163                          * Before the cache can be enabled, due to firmware
 164                          * design, SMC_CMD_L2X0INVALL must be called.
 165                          */
 166                         if (!l2cache_enabled) {
 167                                 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
 168                                 l2cache_enabled = 1;
 169                         }
 170                 } else {
 171                         l2cache_enabled = 0;
 172                 }
 173                 exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
 174                 break;
 175
 176         case L2X0_DEBUG_CTRL:
 177                 exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
 178                 break;
 179
 180         default:
 181                 WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
 182         }
 183 }
 184
 185 static void exynos_l2_configure(const struct l2x0_regs *regs)
 186 {
 187         exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
 188                    regs->prefetch_ctrl);
 189         exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
 190 }
 191
 192 void __init exynos_firmware_init(void)
 193 {
 194         struct device_node *nd;
 195         const __be32 *addr;
 196
 197         nd = of_find_compatible_node(NULL, NULL,
 198                                         "samsung,secure-firmware");
 199         if (!nd)
 200                 return;
 201
 202         addr = of_get_address(nd, 0, NULL, NULL);
 203         if (!addr) {
 204                 pr_err("%s: No address specified.\n", __func__);
 205                 return;
 206         }
 207
 208         pr_info("Running under secure firmware.\n");
 209
 210         register_firmware_ops(&exynos_firmware_ops);
 211
 212         /*
 213          * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
 214          * running under secure firmware, require certain registers of L2
 215          * cache controller to be written in secure mode. Here .write_sec
 216          * callback is provided to perform necessary SMC calls.
 217          */
 218         if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
 219             read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 220                 outer_cache.write_sec = exynos_l2_write_sec;
 221                 outer_cache.configure = exynos_l2_configure;
 222         }
 223 }
 224
 225 #define REG_CPU_STATE_ADDR      (sysram_ns_base_addr + 0x28)
 226 #define BOOT_MODE_MASK          0x1f
 227
 228 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
 229 {
 230         unsigned int tmp;
 231
 232         tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
 233
 234         if (mode & BOOT_MODE_MASK)
 235                 tmp &= ~BOOT_MODE_MASK;
 236
 237         tmp |= mode;
 238         writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 239 }
 240
 241 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
 242 {
 243         unsigned int tmp;
 244
 245         tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
 246         tmp &= ~mode;
 247         writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 248 }