2 * <mach/asp.h> - DaVinci Audio Serial Port support
4 #ifndef __ASM_ARCH_DAVINCI_ASP_H
5 #define __ASM_ARCH_DAVINCI_ASP_H
10 /* Bases of dm644x and dm355 register banks */
11 #define DAVINCI_ASP0_BASE 0x01E02000
12 #define DAVINCI_ASP1_BASE 0x01E04000
14 /* Bases of dm646x register banks */
15 #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
16 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
18 /* Bases of da850/da830 McASP0 register banks */
19 #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
21 /* Bases of da830 McASP1 register banks */
22 #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
24 /* EDMA channels of dm644x and dm355 */
25 #define DAVINCI_DMA_ASP0_TX 2
26 #define DAVINCI_DMA_ASP0_RX 3
27 #define DAVINCI_DMA_ASP1_TX 8
28 #define DAVINCI_DMA_ASP1_RX 9
30 /* EDMA channels of dm646x */
31 #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
32 #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
33 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
35 /* EDMA channels of da850/da830 McASP0 */
36 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
37 #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
39 /* EDMA channels of da830 McASP1 */
40 #define DAVINCI_DA830_DMA_MCASP1_AREVT 2
41 #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
44 #define DAVINCI_ASP0_RX_INT IRQ_MBRINT
45 #define DAVINCI_ASP0_TX_INT IRQ_MBXINT
46 #define DAVINCI_ASP1_RX_INT IRQ_MBRINT
47 #define DAVINCI_ASP1_TX_INT IRQ_MBXINT
49 struct snd_platform_data {
52 enum dma_event_q eventq_no; /* event queue number */
53 unsigned int codec_fmt;
55 * Allowing this is more efficient and eliminates left and right swaps
56 * caused by underruns, but will swap the left and right channels
57 * when compared to previous behavior.
59 unsigned enable_channel_combine:1;
60 unsigned sram_size_playback;
61 unsigned sram_size_capture;
63 /* McASP specific fields */
74 MCASP_VERSION_1 = 0, /* DM646x */
75 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
78 #define INACTIVE_MODE 0
82 #define DAVINCI_MCASP_IIS_MODE 0
83 #define DAVINCI_MCASP_DIT_MODE 1
85 #endif /* __ASM_ARCH_DAVINCI_ASP_H */