arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/init.h>
  14 #include <linux/clk.h>
  15 #include <linux/serial_8250.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/platform_data/edma.h>
  18 #include <linux/platform_data/gpio-davinci.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/cputype.h>
  23 #include <mach/irqs.h>
  24 #include "psc.h"
  25 #include <mach/mux.h>
  26 #include <mach/time.h>
  27 #include <mach/serial.h>
  28 #include <mach/common.h>
  29
  30 #include "davinci.h"
  31 #include "clock.h"
  32 #include "mux.h"
  33 #include "asp.h"
  34
  35 #define DAVINCI_VPIF_BASE       (0x01C12000)
  36
  37 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  38                                         BIT_MASK(0))
  39 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  40                                         BIT_MASK(8))
  41
  42 #define DM646X_EMAC_BASE                0x01c80000
  43 #define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
  44 #define DM646X_EMAC_CNTRL_OFFSET        0x0000
  45 #define DM646X_EMAC_CNTRL_MOD_OFFSET    0x1000
  46 #define DM646X_EMAC_CNTRL_RAM_OFFSET    0x2000
  47 #define DM646X_EMAC_CNTRL_RAM_SIZE      0x2000
  48
  49 static struct pll_data pll1_data = {
  50         .num       = 1,
  51         .phys_base = DAVINCI_PLL1_BASE,
  52 };
  53
  54 static struct pll_data pll2_data = {
  55         .num       = 2,
  56         .phys_base = DAVINCI_PLL2_BASE,
  57 };
  58
  59 static struct clk ref_clk = {
  60         .name = "ref_clk",
  61         /* rate is initialized in dm646x_init_time() */
  62 };
  63
  64 static struct clk aux_clkin = {
  65         .name = "aux_clkin",
  66         /* rate is initialized in dm646x_init_time() */
  67 };
  68
  69 static struct clk pll1_clk = {
  70         .name = "pll1",
  71         .parent = &ref_clk,
  72         .pll_data = &pll1_data,
  73         .flags = CLK_PLL,
  74 };
  75
  76 static struct clk pll1_sysclk1 = {
  77         .name = "pll1_sysclk1",
  78         .parent = &pll1_clk,
  79         .flags = CLK_PLL,
  80         .div_reg = PLLDIV1,
  81 };
  82
  83 static struct clk pll1_sysclk2 = {
  84         .name = "pll1_sysclk2",
  85         .parent = &pll1_clk,
  86         .flags = CLK_PLL,
  87         .div_reg = PLLDIV2,
  88 };
  89
  90 static struct clk pll1_sysclk3 = {
  91         .name = "pll1_sysclk3",
  92         .parent = &pll1_clk,
  93         .flags = CLK_PLL,
  94         .div_reg = PLLDIV3,
  95 };
  96
  97 static struct clk pll1_sysclk4 = {
  98         .name = "pll1_sysclk4",
  99         .parent = &pll1_clk,
 100         .flags = CLK_PLL,
 101         .div_reg = PLLDIV4,
 102 };
 103
 104 static struct clk pll1_sysclk5 = {
 105         .name = "pll1_sysclk5",
 106         .parent = &pll1_clk,
 107         .flags = CLK_PLL,
 108         .div_reg = PLLDIV5,
 109 };
 110
 111 static struct clk pll1_sysclk6 = {
 112         .name = "pll1_sysclk6",
 113         .parent = &pll1_clk,
 114         .flags = CLK_PLL,
 115         .div_reg = PLLDIV6,
 116 };
 117
 118 static struct clk pll1_sysclk8 = {
 119         .name = "pll1_sysclk8",
 120         .parent = &pll1_clk,
 121         .flags = CLK_PLL,
 122         .div_reg = PLLDIV8,
 123 };
 124
 125 static struct clk pll1_sysclk9 = {
 126         .name = "pll1_sysclk9",
 127         .parent = &pll1_clk,
 128         .flags = CLK_PLL,
 129         .div_reg = PLLDIV9,
 130 };
 131
 132 static struct clk pll1_sysclkbp = {
 133         .name = "pll1_sysclkbp",
 134         .parent = &pll1_clk,
 135         .flags = CLK_PLL | PRE_PLL,
 136         .div_reg = BPDIV,
 137 };
 138
 139 static struct clk pll1_aux_clk = {
 140         .name = "pll1_aux_clk",
 141         .parent = &pll1_clk,
 142         .flags = CLK_PLL | PRE_PLL,
 143 };
 144
 145 static struct clk pll2_clk = {
 146         .name = "pll2_clk",
 147         .parent = &ref_clk,
 148         .pll_data = &pll2_data,
 149         .flags = CLK_PLL,
 150 };
 151
 152 static struct clk pll2_sysclk1 = {
 153         .name = "pll2_sysclk1",
 154         .parent = &pll2_clk,
 155         .flags = CLK_PLL,
 156         .div_reg = PLLDIV1,
 157 };
 158
 159 static struct clk dsp_clk = {
 160         .name = "dsp",
 161         .parent = &pll1_sysclk1,
 162         .lpsc = DM646X_LPSC_C64X_CPU,
 163         .usecount = 1,                  /* REVISIT how to disable? */
 164 };
 165
 166 static struct clk arm_clk = {
 167         .name = "arm",
 168         .parent = &pll1_sysclk2,
 169         .lpsc = DM646X_LPSC_ARM,
 170         .flags = ALWAYS_ENABLED,
 171 };
 172
 173 static struct clk edma_cc_clk = {
 174         .name = "edma_cc",
 175         .parent = &pll1_sysclk2,
 176         .lpsc = DM646X_LPSC_TPCC,
 177         .flags = ALWAYS_ENABLED,
 178 };
 179
 180 static struct clk edma_tc0_clk = {
 181         .name = "edma_tc0",
 182         .parent = &pll1_sysclk2,
 183         .lpsc = DM646X_LPSC_TPTC0,
 184         .flags = ALWAYS_ENABLED,
 185 };
 186
 187 static struct clk edma_tc1_clk = {
 188         .name = "edma_tc1",
 189         .parent = &pll1_sysclk2,
 190         .lpsc = DM646X_LPSC_TPTC1,
 191         .flags = ALWAYS_ENABLED,
 192 };
 193
 194 static struct clk edma_tc2_clk = {
 195         .name = "edma_tc2",
 196         .parent = &pll1_sysclk2,
 197         .lpsc = DM646X_LPSC_TPTC2,
 198         .flags = ALWAYS_ENABLED,
 199 };
 200
 201 static struct clk edma_tc3_clk = {
 202         .name = "edma_tc3",
 203         .parent = &pll1_sysclk2,
 204         .lpsc = DM646X_LPSC_TPTC3,
 205         .flags = ALWAYS_ENABLED,
 206 };
 207
 208 static struct clk uart0_clk = {
 209         .name = "uart0",
 210         .parent = &aux_clkin,
 211         .lpsc = DM646X_LPSC_UART0,
 212 };
 213
 214 static struct clk uart1_clk = {
 215         .name = "uart1",
 216         .parent = &aux_clkin,
 217         .lpsc = DM646X_LPSC_UART1,
 218 };
 219
 220 static struct clk uart2_clk = {
 221         .name = "uart2",
 222         .parent = &aux_clkin,
 223         .lpsc = DM646X_LPSC_UART2,
 224 };
 225
 226 static struct clk i2c_clk = {
 227         .name = "I2CCLK",
 228         .parent = &pll1_sysclk3,
 229         .lpsc = DM646X_LPSC_I2C,
 230 };
 231
 232 static struct clk gpio_clk = {
 233         .name = "gpio",
 234         .parent = &pll1_sysclk3,
 235         .lpsc = DM646X_LPSC_GPIO,
 236 };
 237
 238 static struct clk mcasp0_clk = {
 239         .name = "mcasp0",
 240         .parent = &pll1_sysclk3,
 241         .lpsc = DM646X_LPSC_McASP0,
 242 };
 243
 244 static struct clk mcasp1_clk = {
 245         .name = "mcasp1",
 246         .parent = &pll1_sysclk3,
 247         .lpsc = DM646X_LPSC_McASP1,
 248 };
 249
 250 static struct clk aemif_clk = {
 251         .name = "aemif",
 252         .parent = &pll1_sysclk3,
 253         .lpsc = DM646X_LPSC_AEMIF,
 254         .flags = ALWAYS_ENABLED,
 255 };
 256
 257 static struct clk emac_clk = {
 258         .name = "emac",
 259         .parent = &pll1_sysclk3,
 260         .lpsc = DM646X_LPSC_EMAC,
 261 };
 262
 263 static struct clk pwm0_clk = {
 264         .name = "pwm0",
 265         .parent = &pll1_sysclk3,
 266         .lpsc = DM646X_LPSC_PWM0,
 267         .usecount = 1,            /* REVIST: disabling hangs system */
 268 };
 269
 270 static struct clk pwm1_clk = {
 271         .name = "pwm1",
 272         .parent = &pll1_sysclk3,
 273         .lpsc = DM646X_LPSC_PWM1,
 274         .usecount = 1,            /* REVIST: disabling hangs system */
 275 };
 276
 277 static struct clk timer0_clk = {
 278         .name = "timer0",
 279         .parent = &pll1_sysclk3,
 280         .lpsc = DM646X_LPSC_TIMER0,
 281 };
 282
 283 static struct clk timer1_clk = {
 284         .name = "timer1",
 285         .parent = &pll1_sysclk3,
 286         .lpsc = DM646X_LPSC_TIMER1,
 287 };
 288
 289 static struct clk timer2_clk = {
 290         .name = "timer2",
 291         .parent = &pll1_sysclk3,
 292         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 293 };
 294
 295
 296 static struct clk ide_clk = {
 297         .name = "ide",
 298         .parent = &pll1_sysclk4,
 299         .lpsc = DAVINCI_LPSC_ATA,
 300 };
 301
 302 static struct clk vpif0_clk = {
 303         .name = "vpif0",
 304         .parent = &ref_clk,
 305         .lpsc = DM646X_LPSC_VPSSMSTR,
 306         .flags = ALWAYS_ENABLED,
 307 };
 308
 309 static struct clk vpif1_clk = {
 310         .name = "vpif1",
 311         .parent = &ref_clk,
 312         .lpsc = DM646X_LPSC_VPSSSLV,
 313         .flags = ALWAYS_ENABLED,
 314 };
 315
 316 static struct clk_lookup dm646x_clks[] = {
 317         CLK(NULL, "ref", &ref_clk),
 318         CLK(NULL, "aux", &aux_clkin),
 319         CLK(NULL, "pll1", &pll1_clk),
 320         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 321         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 322         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 323         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 324         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 325         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 326         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 327         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 328         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 329         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 330         CLK(NULL, "pll2", &pll2_clk),
 331         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 332         CLK(NULL, "dsp", &dsp_clk),
 333         CLK(NULL, "arm", &arm_clk),
 334         CLK(NULL, "edma_cc", &edma_cc_clk),
 335         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 336         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 337         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 338         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 339         CLK("serial8250.0", NULL, &uart0_clk),
 340         CLK("serial8250.1", NULL, &uart1_clk),
 341         CLK("serial8250.2", NULL, &uart2_clk),
 342         CLK("i2c_davinci.1", NULL, &i2c_clk),
 343         CLK(NULL, "gpio", &gpio_clk),
 344         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
 345         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 346         CLK(NULL, "aemif", &aemif_clk),
 347         CLK("davinci_emac.1", NULL, &emac_clk),
 348         CLK("davinci_mdio.0", "fck", &emac_clk),
 349         CLK(NULL, "pwm0", &pwm0_clk),
 350         CLK(NULL, "pwm1", &pwm1_clk),
 351         CLK(NULL, "timer0", &timer0_clk),
 352         CLK(NULL, "timer1", &timer1_clk),
 353         CLK("davinci-wdt", NULL, &timer2_clk),
 354         CLK("palm_bk3710", NULL, &ide_clk),
 355         CLK(NULL, "vpif0", &vpif0_clk),
 356         CLK(NULL, "vpif1", &vpif1_clk),
 357         CLK(NULL, NULL, NULL),
 358 };
 359
 360 static struct emac_platform_data dm646x_emac_pdata = {
 361         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 362         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 363         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 364         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 365         .version                = EMAC_VERSION_2,
 366 };
 367
 368 static struct resource dm646x_emac_resources[] = {
 369         {
 370                 .start  = DM646X_EMAC_BASE,
 371                 .end    = DM646X_EMAC_BASE + SZ_16K - 1,
 372                 .flags  = IORESOURCE_MEM,
 373         },
 374         {
 375                 .start  = IRQ_DM646X_EMACRXTHINT,
 376                 .end    = IRQ_DM646X_EMACRXTHINT,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379         {
 380                 .start  = IRQ_DM646X_EMACRXINT,
 381                 .end    = IRQ_DM646X_EMACRXINT,
 382                 .flags  = IORESOURCE_IRQ,
 383         },
 384         {
 385                 .start  = IRQ_DM646X_EMACTXINT,
 386                 .end    = IRQ_DM646X_EMACTXINT,
 387                 .flags  = IORESOURCE_IRQ,
 388         },
 389         {
 390                 .start  = IRQ_DM646X_EMACMISCINT,
 391                 .end    = IRQ_DM646X_EMACMISCINT,
 392                 .flags  = IORESOURCE_IRQ,
 393         },
 394 };
 395
 396 static struct platform_device dm646x_emac_device = {
 397         .name           = "davinci_emac",
 398         .id             = 1,
 399         .dev = {
 400                 .platform_data  = &dm646x_emac_pdata,
 401         },
 402         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 403         .resource       = dm646x_emac_resources,
 404 };
 405
 406 static struct resource dm646x_mdio_resources[] = {
 407         {
 408                 .start  = DM646X_EMAC_MDIO_BASE,
 409                 .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412 };
 413
 414 static struct platform_device dm646x_mdio_device = {
 415         .name           = "davinci_mdio",
 416         .id             = 0,
 417         .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
 418         .resource       = dm646x_mdio_resources,
 419 };
 420
 421 /*
 422  * Device specific mux setup
 423  *
 424  *      soc     description     mux  mode   mode  mux    dbg
 425  *                              reg  offset mask  mode
 426  */
 427 static const struct mux_config dm646x_pins[] = {
 428 #ifdef CONFIG_DAVINCI_MUX
 429 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 430
 431 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 432
 433 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 434
 435 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 436
 437 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 438
 439 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 440
 441 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 442
 443 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 444
 445 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 446
 447 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 448
 449 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 450
 451 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 452
 453 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 454
 455 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 456 #endif
 457 };
 458
 459 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 460         [IRQ_DM646X_VP_VERTINT0]        = 7,
 461         [IRQ_DM646X_VP_VERTINT1]        = 7,
 462         [IRQ_DM646X_VP_VERTINT2]        = 7,
 463         [IRQ_DM646X_VP_VERTINT3]        = 7,
 464         [IRQ_DM646X_VP_ERRINT]          = 7,
 465         [IRQ_DM646X_RESERVED_1]         = 7,
 466         [IRQ_DM646X_RESERVED_2]         = 7,
 467         [IRQ_DM646X_WDINT]              = 7,
 468         [IRQ_DM646X_CRGENINT0]          = 7,
 469         [IRQ_DM646X_CRGENINT1]          = 7,
 470         [IRQ_DM646X_TSIFINT0]           = 7,
 471         [IRQ_DM646X_TSIFINT1]           = 7,
 472         [IRQ_DM646X_VDCEINT]            = 7,
 473         [IRQ_DM646X_USBINT]             = 7,
 474         [IRQ_DM646X_USBDMAINT]          = 7,
 475         [IRQ_DM646X_PCIINT]             = 7,
 476         [IRQ_CCINT0]                    = 7,    /* dma */
 477         [IRQ_CCERRINT]                  = 7,    /* dma */
 478         [IRQ_TCERRINT0]                 = 7,    /* dma */
 479         [IRQ_TCERRINT]                  = 7,    /* dma */
 480         [IRQ_DM646X_TCERRINT2]          = 7,
 481         [IRQ_DM646X_TCERRINT3]          = 7,
 482         [IRQ_DM646X_IDE]                = 7,
 483         [IRQ_DM646X_HPIINT]             = 7,
 484         [IRQ_DM646X_EMACRXTHINT]        = 7,
 485         [IRQ_DM646X_EMACRXINT]          = 7,
 486         [IRQ_DM646X_EMACTXINT]          = 7,
 487         [IRQ_DM646X_EMACMISCINT]        = 7,
 488         [IRQ_DM646X_MCASP0TXINT]        = 7,
 489         [IRQ_DM646X_MCASP0RXINT]        = 7,
 490         [IRQ_DM646X_RESERVED_3]         = 7,
 491         [IRQ_DM646X_MCASP1TXINT]        = 7,
 492         [IRQ_TINT0_TINT12]              = 7,    /* clockevent */
 493         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 494         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 495         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 496         [IRQ_PWMINT0]                   = 7,
 497         [IRQ_PWMINT1]                   = 7,
 498         [IRQ_DM646X_VLQINT]             = 7,
 499         [IRQ_I2C]                       = 7,
 500         [IRQ_UARTINT0]                  = 7,
 501         [IRQ_UARTINT1]                  = 7,
 502         [IRQ_DM646X_UARTINT2]           = 7,
 503         [IRQ_DM646X_SPINT0]             = 7,
 504         [IRQ_DM646X_SPINT1]             = 7,
 505         [IRQ_DM646X_DSP2ARMINT]         = 7,
 506         [IRQ_DM646X_RESERVED_4]         = 7,
 507         [IRQ_DM646X_PSCINT]             = 7,
 508         [IRQ_DM646X_GPIO0]              = 7,
 509         [IRQ_DM646X_GPIO1]              = 7,
 510         [IRQ_DM646X_GPIO2]              = 7,
 511         [IRQ_DM646X_GPIO3]              = 7,
 512         [IRQ_DM646X_GPIO4]              = 7,
 513         [IRQ_DM646X_GPIO5]              = 7,
 514         [IRQ_DM646X_GPIO6]              = 7,
 515         [IRQ_DM646X_GPIO7]              = 7,
 516         [IRQ_DM646X_GPIOBNK0]           = 7,
 517         [IRQ_DM646X_GPIOBNK1]           = 7,
 518         [IRQ_DM646X_GPIOBNK2]           = 7,
 519         [IRQ_DM646X_DDRINT]             = 7,
 520         [IRQ_DM646X_AEMIFINT]           = 7,
 521         [IRQ_COMMTX]                    = 7,
 522         [IRQ_COMMRX]                    = 7,
 523         [IRQ_EMUINT]                    = 7,
 524 };
 525
 526 /*----------------------------------------------------------------------*/
 527
 528 /* Four Transfer Controllers on DM646x */
 529 static s8 dm646x_queue_priority_mapping[][2] = {
 530         /* {event queue no, Priority} */
 531         {0, 4},
 532         {1, 0},
 533         {2, 5},
 534         {3, 1},
 535         {-1, -1},
 536 };
 537
 538 static const struct dma_slave_map dm646x_edma_map[] = {
 539         { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
 540         { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
 541         { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
 542         { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
 543         { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
 544 };
 545
 546 static struct edma_soc_info dm646x_edma_pdata = {
 547         .queue_priority_mapping = dm646x_queue_priority_mapping,
 548         .default_queue          = EVENTQ_1,
 549         .slave_map              = dm646x_edma_map,
 550         .slavecnt               = ARRAY_SIZE(dm646x_edma_map),
 551 };
 552
 553 static struct resource edma_resources[] = {
 554         {
 555                 .name   = "edma3_cc",
 556                 .start  = 0x01c00000,
 557                 .end    = 0x01c00000 + SZ_64K - 1,
 558                 .flags  = IORESOURCE_MEM,
 559         },
 560         {
 561                 .name   = "edma3_tc0",
 562                 .start  = 0x01c10000,
 563                 .end    = 0x01c10000 + SZ_1K - 1,
 564                 .flags  = IORESOURCE_MEM,
 565         },
 566         {
 567                 .name   = "edma3_tc1",
 568                 .start  = 0x01c10400,
 569                 .end    = 0x01c10400 + SZ_1K - 1,
 570                 .flags  = IORESOURCE_MEM,
 571         },
 572         {
 573                 .name   = "edma3_tc2",
 574                 .start  = 0x01c10800,
 575                 .end    = 0x01c10800 + SZ_1K - 1,
 576                 .flags  = IORESOURCE_MEM,
 577         },
 578         {
 579                 .name   = "edma3_tc3",
 580                 .start  = 0x01c10c00,
 581                 .end    = 0x01c10c00 + SZ_1K - 1,
 582                 .flags  = IORESOURCE_MEM,
 583         },
 584         {
 585                 .name   = "edma3_ccint",
 586                 .start  = IRQ_CCINT0,
 587                 .flags  = IORESOURCE_IRQ,
 588         },
 589         {
 590                 .name   = "edma3_ccerrint",
 591                 .start  = IRQ_CCERRINT,
 592                 .flags  = IORESOURCE_IRQ,
 593         },
 594         /* not using TC*_ERR */
 595 };
 596
 597 static const struct platform_device_info dm646x_edma_device __initconst = {
 598         .name           = "edma",
 599         .id             = 0,
 600         .dma_mask       = DMA_BIT_MASK(32),
 601         .res            = edma_resources,
 602         .num_res        = ARRAY_SIZE(edma_resources),
 603         .data           = &dm646x_edma_pdata,
 604         .size_data      = sizeof(dm646x_edma_pdata),
 605 };
 606
 607 static struct resource dm646x_mcasp0_resources[] = {
 608         {
 609                 .name   = "mpu",
 610                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 611                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 612                 .flags  = IORESOURCE_MEM,
 613         },
 614         {
 615                 .name   = "tx",
 616                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 617                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 618                 .flags  = IORESOURCE_DMA,
 619         },
 620         {
 621                 .name   = "rx",
 622                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 623                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 624                 .flags  = IORESOURCE_DMA,
 625         },
 626         {
 627                 .name   = "tx",
 628                 .start  = IRQ_DM646X_MCASP0TXINT,
 629                 .flags  = IORESOURCE_IRQ,
 630         },
 631         {
 632                 .name   = "rx",
 633                 .start  = IRQ_DM646X_MCASP0RXINT,
 634                 .flags  = IORESOURCE_IRQ,
 635         },
 636 };
 637
 638 /* DIT mode only, rx is not supported */
 639 static struct resource dm646x_mcasp1_resources[] = {
 640         {
 641                 .name   = "mpu",
 642                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 643                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 644                 .flags  = IORESOURCE_MEM,
 645         },
 646         {
 647                 .name   = "tx",
 648                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 649                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 650                 .flags  = IORESOURCE_DMA,
 651         },
 652         {
 653                 .name   = "tx",
 654                 .start  = IRQ_DM646X_MCASP1TXINT,
 655                 .flags  = IORESOURCE_IRQ,
 656         },
 657 };
 658
 659 static struct platform_device dm646x_mcasp0_device = {
 660         .name           = "davinci-mcasp",
 661         .id             = 0,
 662         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 663         .resource       = dm646x_mcasp0_resources,
 664 };
 665
 666 static struct platform_device dm646x_mcasp1_device = {
 667         .name           = "davinci-mcasp",
 668         .id             = 1,
 669         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 670         .resource       = dm646x_mcasp1_resources,
 671 };
 672
 673 static struct platform_device dm646x_dit_device = {
 674         .name   = "spdif-dit",
 675         .id     = -1,
 676 };
 677
 678 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 679
 680 static struct resource vpif_resource[] = {
 681         {
 682                 .start  = DAVINCI_VPIF_BASE,
 683                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 684                 .flags  = IORESOURCE_MEM,
 685         }
 686 };
 687
 688 static struct platform_device vpif_dev = {
 689         .name           = "vpif",
 690         .id             = -1,
 691         .dev            = {
 692                         .dma_mask               = &vpif_dma_mask,
 693                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 694         },
 695         .resource       = vpif_resource,
 696         .num_resources  = ARRAY_SIZE(vpif_resource),
 697 };
 698
 699 static struct resource vpif_display_resource[] = {
 700         {
 701                 .start = IRQ_DM646X_VP_VERTINT2,
 702                 .end   = IRQ_DM646X_VP_VERTINT2,
 703                 .flags = IORESOURCE_IRQ,
 704         },
 705         {
 706                 .start = IRQ_DM646X_VP_VERTINT3,
 707                 .end   = IRQ_DM646X_VP_VERTINT3,
 708                 .flags = IORESOURCE_IRQ,
 709         },
 710 };
 711
 712 static struct platform_device vpif_display_dev = {
 713         .name           = "vpif_display",
 714         .id             = -1,
 715         .dev            = {
 716                         .dma_mask               = &vpif_dma_mask,
 717                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 718         },
 719         .resource       = vpif_display_resource,
 720         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 721 };
 722
 723 static struct resource vpif_capture_resource[] = {
 724         {
 725                 .start = IRQ_DM646X_VP_VERTINT0,
 726                 .end   = IRQ_DM646X_VP_VERTINT0,
 727                 .flags = IORESOURCE_IRQ,
 728         },
 729         {
 730                 .start = IRQ_DM646X_VP_VERTINT1,
 731                 .end   = IRQ_DM646X_VP_VERTINT1,
 732                 .flags = IORESOURCE_IRQ,
 733         },
 734 };
 735
 736 static struct platform_device vpif_capture_dev = {
 737         .name           = "vpif_capture",
 738         .id             = -1,
 739         .dev            = {
 740                         .dma_mask               = &vpif_dma_mask,
 741                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 742         },
 743         .resource       = vpif_capture_resource,
 744         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 745 };
 746
 747 static struct resource dm646x_gpio_resources[] = {
 748         {       /* registers */
 749                 .start  = DAVINCI_GPIO_BASE,
 750                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 751                 .flags  = IORESOURCE_MEM,
 752         },
 753         {       /* interrupt */
 754                 .start  = IRQ_DM646X_GPIOBNK0,
 755                 .end    = IRQ_DM646X_GPIOBNK2,
 756                 .flags  = IORESOURCE_IRQ,
 757         },
 758 };
 759
 760 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
 761         .ngpio          = 43,
 762 };
 763
 764 int __init dm646x_gpio_register(void)
 765 {
 766         return davinci_gpio_register(dm646x_gpio_resources,
 767                                      ARRAY_SIZE(dm646x_gpio_resources),
 768                                      &dm646x_gpio_platform_data);
 769 }
 770 /*----------------------------------------------------------------------*/
 771
 772 static struct map_desc dm646x_io_desc[] = {
 773         {
 774                 .virtual        = IO_VIRT,
 775                 .pfn            = __phys_to_pfn(IO_PHYS),
 776                 .length         = IO_SIZE,
 777                 .type           = MT_DEVICE
 778         },
 779 };
 780
 781 /* Contents of JTAG ID register used to identify exact cpu type */
 782 static struct davinci_id dm646x_ids[] = {
 783         {
 784                 .variant        = 0x0,
 785                 .part_no        = 0xb770,
 786                 .manufacturer   = 0x017,
 787                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 788                 .name           = "dm6467_rev1.x",
 789         },
 790         {
 791                 .variant        = 0x1,
 792                 .part_no        = 0xb770,
 793                 .manufacturer   = 0x017,
 794                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 795                 .name           = "dm6467_rev3.x",
 796         },
 797 };
 798
 799 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 800
 801 /*
 802  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 803  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 804  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 805  * T1_TOP: Timer 1, top   :  <unused>
 806  */
 807 static struct davinci_timer_info dm646x_timer_info = {
 808         .timers         = davinci_timer_instance,
 809         .clockevent_id  = T0_BOT,
 810         .clocksource_id = T0_TOP,
 811 };
 812
 813 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
 814         {
 815                 .mapbase        = DAVINCI_UART0_BASE,
 816                 .irq            = IRQ_UARTINT0,
 817                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 818                                   UPF_IOREMAP,
 819                 .iotype         = UPIO_MEM32,
 820                 .regshift       = 2,
 821         },
 822         {
 823                 .flags  = 0,
 824         }
 825 };
 826 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
 827         {
 828                 .mapbase        = DAVINCI_UART1_BASE,
 829                 .irq            = IRQ_UARTINT1,
 830                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 831                                   UPF_IOREMAP,
 832                 .iotype         = UPIO_MEM32,
 833                 .regshift       = 2,
 834         },
 835         {
 836                 .flags  = 0,
 837         }
 838 };
 839 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
 840         {
 841                 .mapbase        = DAVINCI_UART2_BASE,
 842                 .irq            = IRQ_DM646X_UARTINT2,
 843                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 844                                   UPF_IOREMAP,
 845                 .iotype         = UPIO_MEM32,
 846                 .regshift       = 2,
 847         },
 848         {
 849                 .flags  = 0,
 850         }
 851 };
 852
 853 struct platform_device dm646x_serial_device[] = {
 854         {
 855                 .name                   = "serial8250",
 856                 .id                     = PLAT8250_DEV_PLATFORM,
 857                 .dev                    = {
 858                         .platform_data  = dm646x_serial0_platform_data,
 859                 }
 860         },
 861         {
 862                 .name                   = "serial8250",
 863                 .id                     = PLAT8250_DEV_PLATFORM1,
 864                 .dev                    = {
 865                         .platform_data  = dm646x_serial1_platform_data,
 866                 }
 867         },
 868         {
 869                 .name                   = "serial8250",
 870                 .id                     = PLAT8250_DEV_PLATFORM2,
 871                 .dev                    = {
 872                         .platform_data  = dm646x_serial2_platform_data,
 873                 }
 874         },
 875         {
 876         }
 877 };
 878
 879 static const struct davinci_soc_info davinci_soc_info_dm646x = {
 880         .io_desc                = dm646x_io_desc,
 881         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 882         .jtag_id_reg            = 0x01c40028,
 883         .ids                    = dm646x_ids,
 884         .ids_num                = ARRAY_SIZE(dm646x_ids),
 885         .psc_bases              = dm646x_psc_bases,
 886         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 887         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 888         .pinmux_pins            = dm646x_pins,
 889         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 890         .intc_base              = DAVINCI_ARM_INTC_BASE,
 891         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 892         .intc_irq_prios         = dm646x_default_priorities,
 893         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 894         .timer_info             = &dm646x_timer_info,
 895         .emac_pdata             = &dm646x_emac_pdata,
 896         .sram_dma               = 0x10010000,
 897         .sram_len               = SZ_32K,
 898 };
 899
 900 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 901 {
 902         dm646x_mcasp0_device.dev.platform_data = pdata;
 903         platform_device_register(&dm646x_mcasp0_device);
 904 }
 905
 906 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 907 {
 908         dm646x_mcasp1_device.dev.platform_data = pdata;
 909         platform_device_register(&dm646x_mcasp1_device);
 910         platform_device_register(&dm646x_dit_device);
 911 }
 912
 913 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 914                        struct vpif_capture_config *capture_config)
 915 {
 916         unsigned int value;
 917
 918         value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 919         value &= ~VSCLKDIS_MASK;
 920         __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 921
 922         value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 923         value &= ~VDD3P3V_VID_MASK;
 924         __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 925
 926         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 927         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 928         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 929         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 930
 931         vpif_display_dev.dev.platform_data = display_config;
 932         vpif_capture_dev.dev.platform_data = capture_config;
 933         platform_device_register(&vpif_dev);
 934         platform_device_register(&vpif_display_dev);
 935         platform_device_register(&vpif_capture_dev);
 936 }
 937
 938 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 939 {
 940         struct platform_device *edma_pdev;
 941
 942         dm646x_edma_pdata.rsv = rsv;
 943
 944         edma_pdev = platform_device_register_full(&dm646x_edma_device);
 945         return PTR_ERR_OR_ZERO(edma_pdev);
 946 }
 947
 948 void __init dm646x_init(void)
 949 {
 950         davinci_common_init(&davinci_soc_info_dm646x);
 951         davinci_map_sysmod();
 952 }
 953
 954 void __init dm646x_init_time(unsigned long ref_clk_rate,
 955                              unsigned long aux_clkin_rate)
 956 {
 957         ref_clk.rate = ref_clk_rate;
 958         aux_clkin.rate = aux_clkin_rate;
 959         davinci_clk_init(dm646x_clks);
 960         davinci_timer_init();
 961 }
 962
 963 static int __init dm646x_init_devices(void)
 964 {
 965         int ret = 0;
 966
 967         if (!cpu_is_davinci_dm646x())
 968                 return 0;
 969
 970         platform_device_register(&dm646x_mdio_device);
 971         platform_device_register(&dm646x_emac_device);
 972
 973         ret = davinci_init_wdt();
 974         if (ret)
 975                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
 976
 977         return ret;
 978 }
 979 postcore_initcall(dm646x_init_devices);