2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dmaengine.h>
16 #include <linux/init.h>
17 #include <linux/irqchip/irq-davinci-aintc.h>
18 #include <linux/platform_data/edma.h>
19 #include <linux/platform_data/gpio-davinci.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach/map.h>
25 #include <mach/common.h>
26 #include <mach/cputype.h>
28 #include <mach/serial.h>
29 #include <mach/time.h>
37 * Device specific clocks
39 #define DM644X_REF_FREQ 27000000
41 #define DM644X_EMAC_BASE 0x01c80000
42 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
43 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
44 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
45 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
46 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
48 static struct emac_platform_data dm644x_emac_pdata = {
49 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
50 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
51 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
52 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
53 .version = EMAC_VERSION_1,
56 static struct resource dm644x_emac_resources[] = {
58 .start = DM644X_EMAC_BASE,
59 .end = DM644X_EMAC_BASE + SZ_16K - 1,
60 .flags = IORESOURCE_MEM,
63 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
64 .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
65 .flags = IORESOURCE_IRQ,
69 static struct platform_device dm644x_emac_device = {
70 .name = "davinci_emac",
73 .platform_data = &dm644x_emac_pdata,
75 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
76 .resource = dm644x_emac_resources,
79 static struct resource dm644x_mdio_resources[] = {
81 .start = DM644X_EMAC_MDIO_BASE,
82 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
83 .flags = IORESOURCE_MEM,
87 static struct platform_device dm644x_mdio_device = {
88 .name = "davinci_mdio",
90 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
91 .resource = dm644x_mdio_resources,
95 * Device specific mux setup
97 * soc description mux mode mode mux dbg
98 * reg offset mask mode
100 static const struct mux_config dm644x_pins[] = {
101 #ifdef CONFIG_DAVINCI_MUX
102 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
103 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
104 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
106 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
108 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
109 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
110 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
111 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
112 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
113 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
115 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
117 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
119 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
121 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
122 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
124 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
126 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
128 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
130 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
131 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
132 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
134 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
136 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
138 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
139 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
140 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
141 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
143 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
145 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
146 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
150 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
151 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
168 [IRQ_CCINT0] = 5, /* dma */
169 [IRQ_CCERRINT] = 5, /* dma */
170 [IRQ_TCERRINT0] = 5, /* dma */
171 [IRQ_TCERRINT] = 5, /* dma */
184 [IRQ_TINT0_TINT12] = 2, /* clockevent */
185 [IRQ_TINT0_TINT34] = 2, /* clocksource */
186 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
187 [IRQ_TINT1_TINT34] = 7, /* system tick */
218 /*----------------------------------------------------------------------*/
220 static s8 queue_priority_mapping[][2] = {
221 /* {event queue no, Priority} */
227 static const struct dma_slave_map dm644x_edma_map[] = {
228 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
229 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
230 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
231 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
232 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
233 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
236 static struct edma_soc_info dm644x_edma_pdata = {
237 .queue_priority_mapping = queue_priority_mapping,
238 .default_queue = EVENTQ_1,
239 .slave_map = dm644x_edma_map,
240 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
243 static struct resource edma_resources[] = {
247 .end = 0x01c00000 + SZ_64K - 1,
248 .flags = IORESOURCE_MEM,
253 .end = 0x01c10000 + SZ_1K - 1,
254 .flags = IORESOURCE_MEM,
259 .end = 0x01c10400 + SZ_1K - 1,
260 .flags = IORESOURCE_MEM,
263 .name = "edma3_ccint",
264 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
265 .flags = IORESOURCE_IRQ,
268 .name = "edma3_ccerrint",
269 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
270 .flags = IORESOURCE_IRQ,
272 /* not using TC*_ERR */
275 static const struct platform_device_info dm644x_edma_device __initconst = {
278 .dma_mask = DMA_BIT_MASK(32),
279 .res = edma_resources,
280 .num_res = ARRAY_SIZE(edma_resources),
281 .data = &dm644x_edma_pdata,
282 .size_data = sizeof(dm644x_edma_pdata),
285 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
286 static struct resource dm644x_asp_resources[] = {
289 .start = DAVINCI_ASP0_BASE,
290 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
291 .flags = IORESOURCE_MEM,
294 .start = DAVINCI_DMA_ASP0_TX,
295 .end = DAVINCI_DMA_ASP0_TX,
296 .flags = IORESOURCE_DMA,
299 .start = DAVINCI_DMA_ASP0_RX,
300 .end = DAVINCI_DMA_ASP0_RX,
301 .flags = IORESOURCE_DMA,
305 static struct platform_device dm644x_asp_device = {
306 .name = "davinci-mcbsp",
308 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
309 .resource = dm644x_asp_resources,
312 #define DM644X_VPSS_BASE 0x01c73400
314 static struct resource dm644x_vpss_resources[] = {
316 /* VPSS Base address */
318 .start = DM644X_VPSS_BASE,
319 .end = DM644X_VPSS_BASE + 0xff,
320 .flags = IORESOURCE_MEM,
324 static struct platform_device dm644x_vpss_device = {
327 .dev.platform_data = "dm644x_vpss",
328 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
329 .resource = dm644x_vpss_resources,
332 static struct resource dm644x_vpfe_resources[] = {
334 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
335 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
336 .flags = IORESOURCE_IRQ,
339 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
340 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
341 .flags = IORESOURCE_IRQ,
345 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
346 static struct resource dm644x_ccdc_resource[] = {
347 /* CCDC Base address */
350 .end = 0x01c70400 + 0xff,
351 .flags = IORESOURCE_MEM,
355 static struct platform_device dm644x_ccdc_dev = {
356 .name = "dm644x_ccdc",
358 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
359 .resource = dm644x_ccdc_resource,
361 .dma_mask = &dm644x_video_dma_mask,
362 .coherent_dma_mask = DMA_BIT_MASK(32),
366 static struct platform_device dm644x_vpfe_dev = {
367 .name = CAPTURE_DRV_NAME,
369 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
370 .resource = dm644x_vpfe_resources,
372 .dma_mask = &dm644x_video_dma_mask,
373 .coherent_dma_mask = DMA_BIT_MASK(32),
377 #define DM644X_OSD_BASE 0x01c72600
379 static struct resource dm644x_osd_resources[] = {
381 .start = DM644X_OSD_BASE,
382 .end = DM644X_OSD_BASE + 0x1ff,
383 .flags = IORESOURCE_MEM,
387 static struct platform_device dm644x_osd_dev = {
388 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
390 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
391 .resource = dm644x_osd_resources,
393 .dma_mask = &dm644x_video_dma_mask,
394 .coherent_dma_mask = DMA_BIT_MASK(32),
398 #define DM644X_VENC_BASE 0x01c72400
400 static struct resource dm644x_venc_resources[] = {
402 .start = DM644X_VENC_BASE,
403 .end = DM644X_VENC_BASE + 0x17f,
404 .flags = IORESOURCE_MEM,
408 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
409 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
410 #define DM644X_VPSS_VENCLKEN BIT(3)
411 #define DM644X_VPSS_DACCLKEN BIT(4)
413 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
417 u32 v = DM644X_VPSS_VENCLKEN;
421 v |= DM644X_VPSS_DACCLKEN;
422 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
424 case VPBE_ENC_DV_TIMINGS:
425 if (pclock <= 27000000) {
426 v |= DM644X_VPSS_DACCLKEN;
427 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
430 * For HD, use external clock source since
431 * HD requires higher clock rate
433 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
434 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
444 static struct resource dm644x_v4l2_disp_resources[] = {
446 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
447 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
448 .flags = IORESOURCE_IRQ,
452 static struct platform_device dm644x_vpbe_display = {
455 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
456 .resource = dm644x_v4l2_disp_resources,
458 .dma_mask = &dm644x_video_dma_mask,
459 .coherent_dma_mask = DMA_BIT_MASK(32),
463 static struct venc_platform_data dm644x_venc_pdata = {
464 .setup_clock = dm644x_venc_setup_clock,
467 static struct platform_device dm644x_venc_dev = {
468 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
470 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
471 .resource = dm644x_venc_resources,
473 .dma_mask = &dm644x_video_dma_mask,
474 .coherent_dma_mask = DMA_BIT_MASK(32),
475 .platform_data = &dm644x_venc_pdata,
479 static struct platform_device dm644x_vpbe_dev = {
480 .name = "vpbe_controller",
483 .dma_mask = &dm644x_video_dma_mask,
484 .coherent_dma_mask = DMA_BIT_MASK(32),
488 static struct resource dm644_gpio_resources[] = {
490 .start = DAVINCI_GPIO_BASE,
491 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
492 .flags = IORESOURCE_MEM,
495 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
496 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
497 .flags = IORESOURCE_IRQ,
500 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
501 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
502 .flags = IORESOURCE_IRQ,
505 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
506 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
507 .flags = IORESOURCE_IRQ,
510 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
511 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
512 .flags = IORESOURCE_IRQ,
515 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
516 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
517 .flags = IORESOURCE_IRQ,
521 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
522 .no_auto_base = true,
527 int __init dm644x_gpio_register(void)
529 return davinci_gpio_register(dm644_gpio_resources,
530 ARRAY_SIZE(dm644_gpio_resources),
531 &dm644_gpio_platform_data);
533 /*----------------------------------------------------------------------*/
535 static struct map_desc dm644x_io_desc[] = {
538 .pfn = __phys_to_pfn(IO_PHYS),
544 /* Contents of JTAG ID register used to identify exact cpu type */
545 static struct davinci_id dm644x_ids[] = {
549 .manufacturer = 0x017,
550 .cpu_id = DAVINCI_CPU_ID_DM6446,
556 .manufacturer = 0x017,
557 .cpu_id = DAVINCI_CPU_ID_DM6446,
563 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
564 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
565 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
566 * T1_TOP: Timer 1, top : <unused>
568 static struct davinci_timer_info dm644x_timer_info = {
569 .timers = davinci_timer_instance,
570 .clockevent_id = T0_BOT,
571 .clocksource_id = T0_TOP,
574 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
576 .mapbase = DAVINCI_UART0_BASE,
577 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
578 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
587 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
589 .mapbase = DAVINCI_UART1_BASE,
590 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
591 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
600 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
602 .mapbase = DAVINCI_UART2_BASE,
603 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
604 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
614 struct platform_device dm644x_serial_device[] = {
616 .name = "serial8250",
617 .id = PLAT8250_DEV_PLATFORM,
619 .platform_data = dm644x_serial0_platform_data,
623 .name = "serial8250",
624 .id = PLAT8250_DEV_PLATFORM1,
626 .platform_data = dm644x_serial1_platform_data,
630 .name = "serial8250",
631 .id = PLAT8250_DEV_PLATFORM2,
633 .platform_data = dm644x_serial2_platform_data,
640 static const struct davinci_soc_info davinci_soc_info_dm644x = {
641 .io_desc = dm644x_io_desc,
642 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
643 .jtag_id_reg = 0x01c40028,
645 .ids_num = ARRAY_SIZE(dm644x_ids),
646 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
647 .pinmux_pins = dm644x_pins,
648 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
649 .timer_info = &dm644x_timer_info,
650 .emac_pdata = &dm644x_emac_pdata,
651 .sram_dma = 0x00008000,
655 void __init dm644x_init_asp(void)
657 davinci_cfg_reg(DM644X_MCBSP);
658 platform_device_register(&dm644x_asp_device);
661 void __init dm644x_init(void)
663 davinci_common_init(&davinci_soc_info_dm644x);
664 davinci_map_sysmod();
667 void __init dm644x_init_time(void)
669 void __iomem *pll1, *psc;
672 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
674 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
675 dm644x_pll1_init(NULL, pll1, NULL);
677 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
678 dm644x_psc_init(NULL, psc);
680 clk = clk_get(NULL, "timer0");
682 davinci_timer_init(clk);
685 static struct resource dm644x_pll2_resources[] = {
687 .start = DAVINCI_PLL2_BASE,
688 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
689 .flags = IORESOURCE_MEM,
693 static struct platform_device dm644x_pll2_device = {
694 .name = "dm644x-pll2",
696 .resource = dm644x_pll2_resources,
697 .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
700 void __init dm644x_register_clocks(void)
702 /* PLL1 and PSC are registered in dm644x_init_time() */
703 platform_device_register(&dm644x_pll2_device);
706 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
707 struct vpbe_config *vpbe_cfg)
709 if (vpfe_cfg || vpbe_cfg)
710 platform_device_register(&dm644x_vpss_device);
713 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
714 platform_device_register(&dm644x_ccdc_dev);
715 platform_device_register(&dm644x_vpfe_dev);
719 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
720 platform_device_register(&dm644x_osd_dev);
721 platform_device_register(&dm644x_venc_dev);
722 platform_device_register(&dm644x_vpbe_dev);
723 platform_device_register(&dm644x_vpbe_display);
729 static const struct davinci_aintc_config dm644x_aintc_config = {
731 .start = DAVINCI_ARM_INTC_BASE,
732 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
733 .flags = IORESOURCE_MEM,
736 .prios = dm644x_default_priorities,
739 void __init dm644x_init_irq(void)
741 davinci_aintc_init(&dm644x_aintc_config);
744 void __init dm644x_init_devices(void)
746 struct platform_device *edma_pdev;
749 edma_pdev = platform_device_register_full(&dm644x_edma_device);
750 if (IS_ERR(edma_pdev))
751 pr_warn("%s: Failed to register eDMA\n", __func__);
753 platform_device_register(&dm644x_mdio_device);
754 platform_device_register(&dm644x_emac_device);
756 ret = davinci_init_wdt();
758 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);