arch/arm/mach-at91/include/mach/cpu.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/cpu.h
   3  *
   4  * Copyright (C) 2006 SAN People
   5  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13
  14 #ifndef __MACH_CPU_H__
  15 #define __MACH_CPU_H__
  16
  17 #define ARCH_ID_AT91RM9200      0x09290780
  18 #define ARCH_ID_AT91SAM9260     0x019803a0
  19 #define ARCH_ID_AT91SAM9261     0x019703a0
  20 #define ARCH_ID_AT91SAM9263     0x019607a0
  21 #define ARCH_ID_AT91SAM9G10     0x019903a0
  22 #define ARCH_ID_AT91SAM9G20     0x019905a0
  23 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
  24 #define ARCH_ID_AT91SAM9G45     0x819b05a0
  25 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
  26 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
  27 #define ARCH_ID_AT91SAM9X5      0x819a05a0
  28 #define ARCH_ID_AT91SAM9N12     0x819a07a0
  29
  30 #define ARCH_ID_AT91SAM9XE128   0x329973a0
  31 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
  32 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
  33
  34 #define ARCH_ID_AT91M40800      0x14080044
  35 #define ARCH_ID_AT91R40807      0x44080746
  36 #define ARCH_ID_AT91M40807      0x14080745
  37 #define ARCH_ID_AT91R40008      0x44000840
  38
  39 #define ARCH_ID_SAMA5D3         0x8A5C07C0
  40
  41 #define ARCH_EXID_AT91SAM9M11   0x00000001
  42 #define ARCH_EXID_AT91SAM9M10   0x00000002
  43 #define ARCH_EXID_AT91SAM9G46   0x00000003
  44 #define ARCH_EXID_AT91SAM9G45   0x00000004
  45
  46 #define ARCH_EXID_AT91SAM9G15   0x00000000
  47 #define ARCH_EXID_AT91SAM9G35   0x00000001
  48 #define ARCH_EXID_AT91SAM9X35   0x00000002
  49 #define ARCH_EXID_AT91SAM9G25   0x00000003
  50 #define ARCH_EXID_AT91SAM9X25   0x00000004
  51
  52 #define ARCH_EXID_SAMA5D31      0x00444300
  53 #define ARCH_EXID_SAMA5D33      0x00414300
  54 #define ARCH_EXID_SAMA5D34      0x00414301
  55 #define ARCH_EXID_SAMA5D35      0x00584300
  56 #define ARCH_EXID_SAMA5D36      0x00004301
  57
  58 #define ARCH_FAMILY_AT91X92     0x09200000
  59 #define ARCH_FAMILY_AT91SAM9    0x01900000
  60 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
  61
  62 /* RM9200 type */
  63 #define ARCH_REVISON_9200_BGA   (0 << 0)
  64 #define ARCH_REVISON_9200_PQFP  (1 << 0)
  65
  66 #ifndef __ASSEMBLY__
  67 enum at91_soc_type {
  68         /* 920T */
  69         AT91_SOC_RM9200,
  70
  71         /* SAM92xx */
  72         AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
  73
  74         /* SAM9Gxx */
  75         AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
  76
  77         /* SAM9RL */
  78         AT91_SOC_SAM9RL,
  79
  80         /* SAM9X5 */
  81         AT91_SOC_SAM9X5,
  82
  83         /* SAM9N12 */
  84         AT91_SOC_SAM9N12,
  85
  86         /* SAMA5D3 */
  87         AT91_SOC_SAMA5D3,
  88
  89         /* Unknown type */
  90         AT91_SOC_UNKNOWN,
  91 };
  92
  93 enum at91_soc_subtype {
  94         /* RM9200 */
  95         AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
  96
  97         /* SAM9260 */
  98         AT91_SOC_SAM9XE,
  99
 100         /* SAM9G45 */
 101         AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
 102
 103         /* SAM9X5 */
 104         AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
 105         AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
 106
 107         /* SAMA5D3 */
 108         AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
 109         AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
 110
 111         /* No subtype for this SoC */
 112         AT91_SOC_SUBTYPE_NONE,
 113
 114         /* Unknown subtype */
 115         AT91_SOC_SUBTYPE_UNKNOWN,
 116 };
 117
 118 struct at91_socinfo {
 119         unsigned int type, subtype;
 120         unsigned int cidr, exid;
 121 };
 122
 123 extern struct at91_socinfo at91_soc_initdata;
 124 const char *at91_get_soc_type(struct at91_socinfo *c);
 125 const char *at91_get_soc_subtype(struct at91_socinfo *c);
 126
 127 static inline int at91_soc_is_detected(void)
 128 {
 129         return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
 130 }
 131
 132 #ifdef CONFIG_SOC_AT91RM9200
 133 #define cpu_is_at91rm9200()     (at91_soc_initdata.type == AT91_SOC_RM9200)
 134 #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
 135 #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
 136 #else
 137 #define cpu_is_at91rm9200()     (0)
 138 #define cpu_is_at91rm9200_bga() (0)
 139 #define cpu_is_at91rm9200_pqfp() (0)
 140 #endif
 141
 142 #ifdef CONFIG_SOC_AT91SAM9260
 143 #define cpu_is_at91sam9xe()     (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
 144 #define cpu_is_at91sam9260()    (at91_soc_initdata.type == AT91_SOC_SAM9260)
 145 #define cpu_is_at91sam9g20()    (at91_soc_initdata.type == AT91_SOC_SAM9G20)
 146 #else
 147 #define cpu_is_at91sam9xe()     (0)
 148 #define cpu_is_at91sam9260()    (0)
 149 #define cpu_is_at91sam9g20()    (0)
 150 #endif
 151
 152 #ifdef CONFIG_SOC_AT91SAM9261
 153 #define cpu_is_at91sam9261()    (at91_soc_initdata.type == AT91_SOC_SAM9261)
 154 #define cpu_is_at91sam9g10()    (at91_soc_initdata.type == AT91_SOC_SAM9G10)
 155 #else
 156 #define cpu_is_at91sam9261()    (0)
 157 #define cpu_is_at91sam9g10()    (0)
 158 #endif
 159
 160 #ifdef CONFIG_SOC_AT91SAM9263
 161 #define cpu_is_at91sam9263()    (at91_soc_initdata.type == AT91_SOC_SAM9263)
 162 #else
 163 #define cpu_is_at91sam9263()    (0)
 164 #endif
 165
 166 #ifdef CONFIG_SOC_AT91SAM9RL
 167 #define cpu_is_at91sam9rl()     (at91_soc_initdata.type == AT91_SOC_SAM9RL)
 168 #else
 169 #define cpu_is_at91sam9rl()     (0)
 170 #endif
 171
 172 #ifdef CONFIG_SOC_AT91SAM9G45
 173 #define cpu_is_at91sam9g45()    (at91_soc_initdata.type == AT91_SOC_SAM9G45)
 174 #define cpu_is_at91sam9g45es()  (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
 175 #define cpu_is_at91sam9m10()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
 176 #define cpu_is_at91sam9g46()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
 177 #define cpu_is_at91sam9m11()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
 178 #else
 179 #define cpu_is_at91sam9g45()    (0)
 180 #define cpu_is_at91sam9g45es()  (0)
 181 #define cpu_is_at91sam9m10()    (0)
 182 #define cpu_is_at91sam9g46()    (0)
 183 #define cpu_is_at91sam9m11()    (0)
 184 #endif
 185
 186 #ifdef CONFIG_SOC_AT91SAM9X5
 187 #define cpu_is_at91sam9x5()     (at91_soc_initdata.type == AT91_SOC_SAM9X5)
 188 #define cpu_is_at91sam9g15()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
 189 #define cpu_is_at91sam9g35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
 190 #define cpu_is_at91sam9x35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
 191 #define cpu_is_at91sam9g25()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
 192 #define cpu_is_at91sam9x25()    (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
 193 #else
 194 #define cpu_is_at91sam9x5()     (0)
 195 #define cpu_is_at91sam9g15()    (0)
 196 #define cpu_is_at91sam9g35()    (0)
 197 #define cpu_is_at91sam9x35()    (0)
 198 #define cpu_is_at91sam9g25()    (0)
 199 #define cpu_is_at91sam9x25()    (0)
 200 #endif
 201
 202 #ifdef CONFIG_SOC_AT91SAM9N12
 203 #define cpu_is_at91sam9n12()    (at91_soc_initdata.type == AT91_SOC_SAM9N12)
 204 #else
 205 #define cpu_is_at91sam9n12()    (0)
 206 #endif
 207
 208 #ifdef CONFIG_SOC_SAMA5D3
 209 #define cpu_is_sama5d3()        (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
 210 #else
 211 #define cpu_is_sama5d3()        (0)
 212 #endif
 213
 214 /*
 215  * Since this is ARM, we will never run on any AVR32 CPU. But these
 216  * definitions may reduce clutter in common drivers.
 217  */
 218 #define cpu_is_at32ap7000()     (0)
 219 #endif /* __ASSEMBLY__ */
 220
 221 #endif /* __MACH_CPU_H__ */