arch/arm/mach-at91/at91sam9g45_devices.c

   1 /*
   2  *  On-Chip devices setup code for the AT91SAM9G45 family
   3  *
   4  *  Copyright (C) 2009 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12 #include <asm/mach/arch.h>
  13 #include <asm/mach/map.h>
  14
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17 #include <linux/clk.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c-gpio.h>
  20 #include <linux/atmel-mci.h>
  21 #include <linux/platform_data/crypto-atmel.h>
  22
  23 #include <linux/platform_data/at91_adc.h>
  24
  25 #include <linux/fb.h>
  26 #include <video/atmel_lcdc.h>
  27
  28 #include <mach/at91_adc.h>
  29 #include <mach/at91sam9g45.h>
  30 #include <mach/at91sam9g45_matrix.h>
  31 #include <mach/at91_matrix.h>
  32 #include <mach/at91sam9_smc.h>
  33 #include <linux/platform_data/dma-atmel.h>
  34 #include <mach/atmel-mci.h>
  35 #include <mach/hardware.h>
  36
  37 #include <media/atmel-isi.h>
  38
  39 #include "board.h"
  40 #include "generic.h"
  41 #include "clock.h"
  42
  43
  44 /* --------------------------------------------------------------------
  45  *  HDMAC - AHB DMA Controller
  46  * -------------------------------------------------------------------- */
  47
  48 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
  49 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
  50
  51 static struct resource hdmac_resources[] = {
  52         [0] = {
  53                 .start  = AT91SAM9G45_BASE_DMA,
  54                 .end    = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
  55                 .flags  = IORESOURCE_MEM,
  56         },
  57         [1] = {
  58                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
  59                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
  60                 .flags  = IORESOURCE_IRQ,
  61         },
  62 };
  63
  64 static struct platform_device at_hdmac_device = {
  65         .name           = "at91sam9g45_dma",
  66         .id             = -1,
  67         .dev            = {
  68                                 .dma_mask               = &hdmac_dmamask,
  69                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  70         },
  71         .resource       = hdmac_resources,
  72         .num_resources  = ARRAY_SIZE(hdmac_resources),
  73 };
  74
  75 void __init at91_add_device_hdmac(void)
  76 {
  77         platform_device_register(&at_hdmac_device);
  78 }
  79 #else
  80 void __init at91_add_device_hdmac(void) {}
  81 #endif
  82
  83
  84 /* --------------------------------------------------------------------
  85  *  USB Host (OHCI)
  86  * -------------------------------------------------------------------- */
  87
  88 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  89 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  90 static struct at91_usbh_data usbh_ohci_data;
  91
  92 static struct resource usbh_ohci_resources[] = {
  93         [0] = {
  94                 .start  = AT91SAM9G45_OHCI_BASE,
  95                 .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
  96                 .flags  = IORESOURCE_MEM,
  97         },
  98         [1] = {
  99                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
 100                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
 101                 .flags  = IORESOURCE_IRQ,
 102         },
 103 };
 104
 105 static struct platform_device at91_usbh_ohci_device = {
 106         .name           = "at91_ohci",
 107         .id             = -1,
 108         .dev            = {
 109                                 .dma_mask               = &ohci_dmamask,
 110                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 111                                 .platform_data          = &usbh_ohci_data,
 112         },
 113         .resource       = usbh_ohci_resources,
 114         .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
 115 };
 116
 117 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 118 {
 119         int i;
 120
 121         if (!data)
 122                 return;
 123
 124         /* Enable VBus control for UHP ports */
 125         for (i = 0; i < data->ports; i++) {
 126                 if (gpio_is_valid(data->vbus_pin[i]))
 127                         at91_set_gpio_output(data->vbus_pin[i],
 128                                              data->vbus_pin_active_low[i]);
 129         }
 130
 131         /* Enable overcurrent notification */
 132         for (i = 0; i < data->ports; i++) {
 133                 if (gpio_is_valid(data->overcurrent_pin[i]))
 134                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
 135         }
 136
 137         usbh_ohci_data = *data;
 138         platform_device_register(&at91_usbh_ohci_device);
 139 }
 140 #else
 141 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
 142 #endif
 143
 144
 145 /* --------------------------------------------------------------------
 146  *  USB Host HS (EHCI)
 147  *  Needs an OHCI host for low and full speed management
 148  * -------------------------------------------------------------------- */
 149
 150 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
 151 static u64 ehci_dmamask = DMA_BIT_MASK(32);
 152 static struct at91_usbh_data usbh_ehci_data;
 153
 154 static struct resource usbh_ehci_resources[] = {
 155         [0] = {
 156                 .start  = AT91SAM9G45_EHCI_BASE,
 157                 .end    = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
 158                 .flags  = IORESOURCE_MEM,
 159         },
 160         [1] = {
 161                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
 162                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
 163                 .flags  = IORESOURCE_IRQ,
 164         },
 165 };
 166
 167 static struct platform_device at91_usbh_ehci_device = {
 168         .name           = "atmel-ehci",
 169         .id             = -1,
 170         .dev            = {
 171                                 .dma_mask               = &ehci_dmamask,
 172                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 173                                 .platform_data          = &usbh_ehci_data,
 174         },
 175         .resource       = usbh_ehci_resources,
 176         .num_resources  = ARRAY_SIZE(usbh_ehci_resources),
 177 };
 178
 179 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
 180 {
 181         int i;
 182
 183         if (!data)
 184                 return;
 185
 186         /* Enable VBus control for UHP ports */
 187         for (i = 0; i < data->ports; i++) {
 188                 if (gpio_is_valid(data->vbus_pin[i]))
 189                         at91_set_gpio_output(data->vbus_pin[i],
 190                                              data->vbus_pin_active_low[i]);
 191         }
 192
 193         usbh_ehci_data = *data;
 194         platform_device_register(&at91_usbh_ehci_device);
 195 }
 196 #else
 197 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
 198 #endif
 199
 200
 201 /* --------------------------------------------------------------------
 202  *  USB HS Device (Gadget)
 203  * -------------------------------------------------------------------- */
 204
 205 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
 206 static struct resource usba_udc_resources[] = {
 207         [0] = {
 208                 .start  = AT91SAM9G45_UDPHS_FIFO,
 209                 .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
 210                 .flags  = IORESOURCE_MEM,
 211         },
 212         [1] = {
 213                 .start  = AT91SAM9G45_BASE_UDPHS,
 214                 .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         [2] = {
 218                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
 219                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
 220                 .flags  = IORESOURCE_IRQ,
 221         },
 222 };
 223
 224 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
 225         [idx] = {                                               \
 226                 .name           = nam,                          \
 227                 .index          = idx,                          \
 228                 .fifo_size      = maxpkt,                       \
 229                 .nr_banks       = maxbk,                        \
 230                 .can_dma        = dma,                          \
 231                 .can_isoc       = isoc,                         \
 232         }
 233
 234 static struct usba_ep_data usba_udc_ep[] __initdata = {
 235         EP("ep0", 0, 64, 1, 0, 0),
 236         EP("ep1", 1, 1024, 2, 1, 1),
 237         EP("ep2", 2, 1024, 2, 1, 1),
 238         EP("ep3", 3, 1024, 3, 1, 0),
 239         EP("ep4", 4, 1024, 3, 1, 0),
 240         EP("ep5", 5, 1024, 3, 1, 1),
 241         EP("ep6", 6, 1024, 3, 1, 1),
 242 };
 243
 244 #undef EP
 245
 246 /*
 247  * pdata doesn't have room for any endpoints, so we need to
 248  * append room for the ones we need right after it.
 249  */
 250 static struct {
 251         struct usba_platform_data pdata;
 252         struct usba_ep_data ep[7];
 253 } usba_udc_data;
 254
 255 static struct platform_device at91_usba_udc_device = {
 256         .name           = "atmel_usba_udc",
 257         .id             = -1,
 258         .dev            = {
 259                                 .platform_data  = &usba_udc_data.pdata,
 260         },
 261         .resource       = usba_udc_resources,
 262         .num_resources  = ARRAY_SIZE(usba_udc_resources),
 263 };
 264
 265 void __init at91_add_device_usba(struct usba_platform_data *data)
 266 {
 267         usba_udc_data.pdata.vbus_pin = -EINVAL;
 268         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
 269         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 270
 271         if (data && gpio_is_valid(data->vbus_pin)) {
 272                 at91_set_gpio_input(data->vbus_pin, 0);
 273                 at91_set_deglitch(data->vbus_pin, 1);
 274                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
 275         }
 276
 277         /* Pullup pin is handled internally by USB device peripheral */
 278
 279         platform_device_register(&at91_usba_udc_device);
 280 }
 281 #else
 282 void __init at91_add_device_usba(struct usba_platform_data *data) {}
 283 #endif
 284
 285
 286 /* --------------------------------------------------------------------
 287  *  Ethernet
 288  * -------------------------------------------------------------------- */
 289
 290 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 291 static u64 eth_dmamask = DMA_BIT_MASK(32);
 292 static struct macb_platform_data eth_data;
 293
 294 static struct resource eth_resources[] = {
 295         [0] = {
 296                 .start  = AT91SAM9G45_BASE_EMAC,
 297                 .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
 298                 .flags  = IORESOURCE_MEM,
 299         },
 300         [1] = {
 301                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
 302                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
 303                 .flags  = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct platform_device at91sam9g45_eth_device = {
 308         .name           = "macb",
 309         .id             = -1,
 310         .dev            = {
 311                                 .dma_mask               = &eth_dmamask,
 312                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 313                                 .platform_data          = &eth_data,
 314         },
 315         .resource       = eth_resources,
 316         .num_resources  = ARRAY_SIZE(eth_resources),
 317 };
 318
 319 void __init at91_add_device_eth(struct macb_platform_data *data)
 320 {
 321         if (!data)
 322                 return;
 323
 324         if (gpio_is_valid(data->phy_irq_pin)) {
 325                 at91_set_gpio_input(data->phy_irq_pin, 0);
 326                 at91_set_deglitch(data->phy_irq_pin, 1);
 327         }
 328
 329         /* Pins used for MII and RMII */
 330         at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
 331         at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
 332         at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
 333         at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
 334         at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
 335         at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
 336         at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
 337         at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
 338         at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
 339         at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
 340
 341         if (!data->is_rmii) {
 342                 at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
 343                 at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
 344                 at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
 345                 at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
 346                 at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
 347                 at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
 348                 at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
 349                 at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
 350         }
 351
 352         eth_data = *data;
 353         platform_device_register(&at91sam9g45_eth_device);
 354 }
 355 #else
 356 void __init at91_add_device_eth(struct macb_platform_data *data) {}
 357 #endif
 358
 359
 360 /* --------------------------------------------------------------------
 361  *  MMC / SD
 362  * -------------------------------------------------------------------- */
 363
 364 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 365 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 366 static struct mci_platform_data mmc0_data, mmc1_data;
 367
 368 static struct resource mmc0_resources[] = {
 369         [0] = {
 370                 .start  = AT91SAM9G45_BASE_MCI0,
 371                 .end    = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
 372                 .flags  = IORESOURCE_MEM,
 373         },
 374         [1] = {
 375                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
 376                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379 };
 380
 381 static struct platform_device at91sam9g45_mmc0_device = {
 382         .name           = "atmel_mci",
 383         .id             = 0,
 384         .dev            = {
 385                                 .dma_mask               = &mmc_dmamask,
 386                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 387                                 .platform_data          = &mmc0_data,
 388         },
 389         .resource       = mmc0_resources,
 390         .num_resources  = ARRAY_SIZE(mmc0_resources),
 391 };
 392
 393 static struct resource mmc1_resources[] = {
 394         [0] = {
 395                 .start  = AT91SAM9G45_BASE_MCI1,
 396                 .end    = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
 397                 .flags  = IORESOURCE_MEM,
 398         },
 399         [1] = {
 400                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
 401                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
 402                 .flags  = IORESOURCE_IRQ,
 403         },
 404 };
 405
 406 static struct platform_device at91sam9g45_mmc1_device = {
 407         .name           = "atmel_mci",
 408         .id             = 1,
 409         .dev            = {
 410                                 .dma_mask               = &mmc_dmamask,
 411                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 412                                 .platform_data          = &mmc1_data,
 413         },
 414         .resource       = mmc1_resources,
 415         .num_resources  = ARRAY_SIZE(mmc1_resources),
 416 };
 417
 418 /* Consider only one slot : slot 0 */
 419 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 420 {
 421
 422         if (!data)
 423                 return;
 424
 425         /* Must have at least one usable slot */
 426         if (!data->slot[0].bus_width)
 427                 return;
 428
 429 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
 430         {
 431         struct at_dma_slave     *atslave;
 432         struct mci_dma_data     *alt_atslave;
 433
 434         alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
 435         atslave = &alt_atslave->sdata;
 436
 437         /* DMA slave channel configuration */
 438         atslave->dma_dev = &at_hdmac_device.dev;
 439         atslave->cfg = ATC_FIFOCFG_HALFFIFO
 440                         | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
 441         if (mmc_id == 0)        /* MCI0 */
 442                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
 443                               | ATC_DST_PER(AT_DMA_ID_MCI0);
 444
 445         else                    /* MCI1 */
 446                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
 447                               | ATC_DST_PER(AT_DMA_ID_MCI1);
 448
 449         data->dma_slave = alt_atslave;
 450         }
 451 #endif
 452
 453
 454         /* input/irq */
 455         if (gpio_is_valid(data->slot[0].detect_pin)) {
 456                 at91_set_gpio_input(data->slot[0].detect_pin, 1);
 457                 at91_set_deglitch(data->slot[0].detect_pin, 1);
 458         }
 459         if (gpio_is_valid(data->slot[0].wp_pin))
 460                 at91_set_gpio_input(data->slot[0].wp_pin, 1);
 461
 462         if (mmc_id == 0) {              /* MCI0 */
 463
 464                 /* CLK */
 465                 at91_set_A_periph(AT91_PIN_PA0, 0);
 466
 467                 /* CMD */
 468                 at91_set_A_periph(AT91_PIN_PA1, 1);
 469
 470                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 471                 at91_set_A_periph(AT91_PIN_PA2, 1);
 472                 if (data->slot[0].bus_width == 4) {
 473                         at91_set_A_periph(AT91_PIN_PA3, 1);
 474                         at91_set_A_periph(AT91_PIN_PA4, 1);
 475                         at91_set_A_periph(AT91_PIN_PA5, 1);
 476                         if (data->slot[0].bus_width == 8) {
 477                                 at91_set_A_periph(AT91_PIN_PA6, 1);
 478                                 at91_set_A_periph(AT91_PIN_PA7, 1);
 479                                 at91_set_A_periph(AT91_PIN_PA8, 1);
 480                                 at91_set_A_periph(AT91_PIN_PA9, 1);
 481                         }
 482                 }
 483
 484                 mmc0_data = *data;
 485                 platform_device_register(&at91sam9g45_mmc0_device);
 486
 487         } else {                        /* MCI1 */
 488
 489                 /* CLK */
 490                 at91_set_A_periph(AT91_PIN_PA31, 0);
 491
 492                 /* CMD */
 493                 at91_set_A_periph(AT91_PIN_PA22, 1);
 494
 495                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 496                 at91_set_A_periph(AT91_PIN_PA23, 1);
 497                 if (data->slot[0].bus_width == 4) {
 498                         at91_set_A_periph(AT91_PIN_PA24, 1);
 499                         at91_set_A_periph(AT91_PIN_PA25, 1);
 500                         at91_set_A_periph(AT91_PIN_PA26, 1);
 501                         if (data->slot[0].bus_width == 8) {
 502                                 at91_set_A_periph(AT91_PIN_PA27, 1);
 503                                 at91_set_A_periph(AT91_PIN_PA28, 1);
 504                                 at91_set_A_periph(AT91_PIN_PA29, 1);
 505                                 at91_set_A_periph(AT91_PIN_PA30, 1);
 506                         }
 507                 }
 508
 509                 mmc1_data = *data;
 510                 platform_device_register(&at91sam9g45_mmc1_device);
 511
 512         }
 513 }
 514 #else
 515 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 516 #endif
 517
 518
 519 /* --------------------------------------------------------------------
 520  *  NAND / SmartMedia
 521  * -------------------------------------------------------------------- */
 522
 523 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 524 static struct atmel_nand_data nand_data;
 525
 526 #define NAND_BASE       AT91_CHIPSELECT_3
 527
 528 static struct resource nand_resources[] = {
 529         [0] = {
 530                 .start  = NAND_BASE,
 531                 .end    = NAND_BASE + SZ_256M - 1,
 532                 .flags  = IORESOURCE_MEM,
 533         },
 534         [1] = {
 535                 .start  = AT91SAM9G45_BASE_ECC,
 536                 .end    = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
 537                 .flags  = IORESOURCE_MEM,
 538         }
 539 };
 540
 541 static struct platform_device at91sam9g45_nand_device = {
 542         .name           = "atmel_nand",
 543         .id             = -1,
 544         .dev            = {
 545                                 .platform_data  = &nand_data,
 546         },
 547         .resource       = nand_resources,
 548         .num_resources  = ARRAY_SIZE(nand_resources),
 549 };
 550
 551 void __init at91_add_device_nand(struct atmel_nand_data *data)
 552 {
 553         unsigned long csa;
 554
 555         if (!data)
 556                 return;
 557
 558         csa = at91_matrix_read(AT91_MATRIX_EBICSA);
 559         at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 560
 561         /* enable pin */
 562         if (gpio_is_valid(data->enable_pin))
 563                 at91_set_gpio_output(data->enable_pin, 1);
 564
 565         /* ready/busy pin */
 566         if (gpio_is_valid(data->rdy_pin))
 567                 at91_set_gpio_input(data->rdy_pin, 1);
 568
 569         /* card detect pin */
 570         if (gpio_is_valid(data->det_pin))
 571                 at91_set_gpio_input(data->det_pin, 1);
 572
 573         nand_data = *data;
 574         platform_device_register(&at91sam9g45_nand_device);
 575 }
 576 #else
 577 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 578 #endif
 579
 580
 581 /* --------------------------------------------------------------------
 582  *  TWI (i2c)
 583  * -------------------------------------------------------------------- */
 584
 585 /*
 586  * Prefer the GPIO code since the TWI controller isn't robust
 587  * (gets overruns and underruns under load) and can only issue
 588  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 589  */
 590 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 591 static struct i2c_gpio_platform_data pdata_i2c0 = {
 592         .sda_pin                = AT91_PIN_PA20,
 593         .sda_is_open_drain      = 1,
 594         .scl_pin                = AT91_PIN_PA21,
 595         .scl_is_open_drain      = 1,
 596         .udelay                 = 5,            /* ~100 kHz */
 597 };
 598
 599 static struct platform_device at91sam9g45_twi0_device = {
 600         .name                   = "i2c-gpio",
 601         .id                     = 0,
 602         .dev.platform_data      = &pdata_i2c0,
 603 };
 604
 605 static struct i2c_gpio_platform_data pdata_i2c1 = {
 606         .sda_pin                = AT91_PIN_PB10,
 607         .sda_is_open_drain      = 1,
 608         .scl_pin                = AT91_PIN_PB11,
 609         .scl_is_open_drain      = 1,
 610         .udelay                 = 5,            /* ~100 kHz */
 611 };
 612
 613 static struct platform_device at91sam9g45_twi1_device = {
 614         .name                   = "i2c-gpio",
 615         .id                     = 1,
 616         .dev.platform_data      = &pdata_i2c1,
 617 };
 618
 619 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 620 {
 621         i2c_register_board_info(i2c_id, devices, nr_devices);
 622
 623         if (i2c_id == 0) {
 624                 at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
 625                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 626
 627                 at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
 628                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 629
 630                 platform_device_register(&at91sam9g45_twi0_device);
 631         } else {
 632                 at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
 633                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 634
 635                 at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
 636                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 637
 638                 platform_device_register(&at91sam9g45_twi1_device);
 639         }
 640 }
 641
 642 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 643 static struct resource twi0_resources[] = {
 644         [0] = {
 645                 .start  = AT91SAM9G45_BASE_TWI0,
 646                 .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
 647                 .flags  = IORESOURCE_MEM,
 648         },
 649         [1] = {
 650                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
 651                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
 652                 .flags  = IORESOURCE_IRQ,
 653         },
 654 };
 655
 656 static struct platform_device at91sam9g45_twi0_device = {
 657         .name           = "i2c-at91sam9g10",
 658         .id             = 0,
 659         .resource       = twi0_resources,
 660         .num_resources  = ARRAY_SIZE(twi0_resources),
 661 };
 662
 663 static struct resource twi1_resources[] = {
 664         [0] = {
 665                 .start  = AT91SAM9G45_BASE_TWI1,
 666                 .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
 667                 .flags  = IORESOURCE_MEM,
 668         },
 669         [1] = {
 670                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
 671                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
 672                 .flags  = IORESOURCE_IRQ,
 673         },
 674 };
 675
 676 static struct platform_device at91sam9g45_twi1_device = {
 677         .name           = "i2c-at91sam9g10",
 678         .id             = 1,
 679         .resource       = twi1_resources,
 680         .num_resources  = ARRAY_SIZE(twi1_resources),
 681 };
 682
 683 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 684 {
 685         i2c_register_board_info(i2c_id, devices, nr_devices);
 686
 687         /* pins used for TWI interface */
 688         if (i2c_id == 0) {
 689                 at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
 690                 at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
 691
 692                 platform_device_register(&at91sam9g45_twi0_device);
 693         } else {
 694                 at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
 695                 at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
 696
 697                 platform_device_register(&at91sam9g45_twi1_device);
 698         }
 699 }
 700 #else
 701 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
 702 #endif
 703
 704
 705 /* --------------------------------------------------------------------
 706  *  SPI
 707  * -------------------------------------------------------------------- */
 708
 709 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 710 static u64 spi_dmamask = DMA_BIT_MASK(32);
 711
 712 static struct resource spi0_resources[] = {
 713         [0] = {
 714                 .start  = AT91SAM9G45_BASE_SPI0,
 715                 .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
 716                 .flags  = IORESOURCE_MEM,
 717         },
 718         [1] = {
 719                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
 720                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
 721                 .flags  = IORESOURCE_IRQ,
 722         },
 723 };
 724
 725 static struct platform_device at91sam9g45_spi0_device = {
 726         .name           = "atmel_spi",
 727         .id             = 0,
 728         .dev            = {
 729                                 .dma_mask               = &spi_dmamask,
 730                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 731         },
 732         .resource       = spi0_resources,
 733         .num_resources  = ARRAY_SIZE(spi0_resources),
 734 };
 735
 736 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
 737
 738 static struct resource spi1_resources[] = {
 739         [0] = {
 740                 .start  = AT91SAM9G45_BASE_SPI1,
 741                 .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
 742                 .flags  = IORESOURCE_MEM,
 743         },
 744         [1] = {
 745                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
 746                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
 747                 .flags  = IORESOURCE_IRQ,
 748         },
 749 };
 750
 751 static struct platform_device at91sam9g45_spi1_device = {
 752         .name           = "atmel_spi",
 753         .id             = 1,
 754         .dev            = {
 755                                 .dma_mask               = &spi_dmamask,
 756                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 757         },
 758         .resource       = spi1_resources,
 759         .num_resources  = ARRAY_SIZE(spi1_resources),
 760 };
 761
 762 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
 763
 764 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 765 {
 766         int i;
 767         unsigned long cs_pin;
 768         short enable_spi0 = 0;
 769         short enable_spi1 = 0;
 770
 771         /* Choose SPI chip-selects */
 772         for (i = 0; i < nr_devices; i++) {
 773                 if (devices[i].controller_data)
 774                         cs_pin = (unsigned long) devices[i].controller_data;
 775                 else if (devices[i].bus_num == 0)
 776                         cs_pin = spi0_standard_cs[devices[i].chip_select];
 777                 else
 778                         cs_pin = spi1_standard_cs[devices[i].chip_select];
 779
 780                 if (!gpio_is_valid(cs_pin))
 781                         continue;
 782
 783                 if (devices[i].bus_num == 0)
 784                         enable_spi0 = 1;
 785                 else
 786                         enable_spi1 = 1;
 787
 788                 /* enable chip-select pin */
 789                 at91_set_gpio_output(cs_pin, 1);
 790
 791                 /* pass chip-select pin to driver */
 792                 devices[i].controller_data = (void *) cs_pin;
 793         }
 794
 795         spi_register_board_info(devices, nr_devices);
 796
 797         /* Configure SPI bus(es) */
 798         if (enable_spi0) {
 799                 at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
 800                 at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
 801                 at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
 802
 803                 platform_device_register(&at91sam9g45_spi0_device);
 804         }
 805         if (enable_spi1) {
 806                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
 807                 at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
 808                 at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
 809
 810                 platform_device_register(&at91sam9g45_spi1_device);
 811         }
 812 }
 813 #else
 814 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 815 #endif
 816
 817
 818 /* --------------------------------------------------------------------
 819  *  AC97
 820  * -------------------------------------------------------------------- */
 821
 822 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 823 static u64 ac97_dmamask = DMA_BIT_MASK(32);
 824 static struct ac97c_platform_data ac97_data;
 825
 826 static struct resource ac97_resources[] = {
 827         [0] = {
 828                 .start  = AT91SAM9G45_BASE_AC97C,
 829                 .end    = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
 830                 .flags  = IORESOURCE_MEM,
 831         },
 832         [1] = {
 833                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
 834                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
 835                 .flags  = IORESOURCE_IRQ,
 836         },
 837 };
 838
 839 static struct platform_device at91sam9g45_ac97_device = {
 840         .name           = "atmel_ac97c",
 841         .id             = 0,
 842         .dev            = {
 843                                 .dma_mask               = &ac97_dmamask,
 844                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 845                                 .platform_data          = &ac97_data,
 846         },
 847         .resource       = ac97_resources,
 848         .num_resources  = ARRAY_SIZE(ac97_resources),
 849 };
 850
 851 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 852 {
 853         if (!data)
 854                 return;
 855
 856         at91_set_A_periph(AT91_PIN_PD8, 0);     /* AC97FS */
 857         at91_set_A_periph(AT91_PIN_PD9, 0);     /* AC97CK */
 858         at91_set_A_periph(AT91_PIN_PD7, 0);     /* AC97TX */
 859         at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
 860
 861         /* reset */
 862         if (gpio_is_valid(data->reset_pin))
 863                 at91_set_gpio_output(data->reset_pin, 0);
 864
 865         ac97_data = *data;
 866         platform_device_register(&at91sam9g45_ac97_device);
 867 }
 868 #else
 869 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 870 #endif
 871
 872 /* --------------------------------------------------------------------
 873  *  Image Sensor Interface
 874  * -------------------------------------------------------------------- */
 875 #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
 876 static u64 isi_dmamask = DMA_BIT_MASK(32);
 877 static struct isi_platform_data isi_data;
 878
 879 struct resource isi_resources[] = {
 880         [0] = {
 881                 .start  = AT91SAM9G45_BASE_ISI,
 882                 .end    = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
 883                 .flags  = IORESOURCE_MEM,
 884         },
 885         [1] = {
 886                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
 887                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
 888                 .flags  = IORESOURCE_IRQ,
 889         },
 890 };
 891
 892 static struct platform_device at91sam9g45_isi_device = {
 893         .name           = "atmel_isi",
 894         .id             = 0,
 895         .dev            = {
 896                         .dma_mask               = &isi_dmamask,
 897                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 898                         .platform_data          = &isi_data,
 899         },
 900         .resource       = isi_resources,
 901         .num_resources  = ARRAY_SIZE(isi_resources),
 902 };
 903
 904 static struct clk_lookup isi_mck_lookups[] = {
 905         CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
 906 };
 907
 908 void __init at91_add_device_isi(struct isi_platform_data *data,
 909                 bool use_pck_as_mck)
 910 {
 911         struct clk *pck;
 912         struct clk *parent;
 913
 914         if (!data)
 915                 return;
 916         isi_data = *data;
 917
 918         at91_set_A_periph(AT91_PIN_PB20, 0);    /* ISI_D0 */
 919         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ISI_D1 */
 920         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ISI_D2 */
 921         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ISI_D3 */
 922         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ISI_D4 */
 923         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ISI_D5 */
 924         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ISI_D6 */
 925         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ISI_D7 */
 926         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ISI_PCK */
 927         at91_set_A_periph(AT91_PIN_PB30, 0);    /* ISI_HSYNC */
 928         at91_set_A_periph(AT91_PIN_PB29, 0);    /* ISI_VSYNC */
 929         at91_set_B_periph(AT91_PIN_PB8, 0);     /* ISI_PD8 */
 930         at91_set_B_periph(AT91_PIN_PB9, 0);     /* ISI_PD9 */
 931         at91_set_B_periph(AT91_PIN_PB10, 0);    /* ISI_PD10 */
 932         at91_set_B_periph(AT91_PIN_PB11, 0);    /* ISI_PD11 */
 933
 934         platform_device_register(&at91sam9g45_isi_device);
 935
 936         if (use_pck_as_mck) {
 937                 at91_set_B_periph(AT91_PIN_PB31, 0);    /* ISI_MCK (PCK1) */
 938
 939                 pck = clk_get(NULL, "pck1");
 940                 parent = clk_get(NULL, "plla");
 941
 942                 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
 943
 944                 if (clk_set_parent(pck, parent)) {
 945                         pr_err("Failed to set PCK's parent\n");
 946                 } else {
 947                         /* Register PCK as ISI_MCK */
 948                         isi_mck_lookups[0].clk = pck;
 949                         clkdev_add_table(isi_mck_lookups,
 950                                         ARRAY_SIZE(isi_mck_lookups));
 951                 }
 952
 953                 clk_put(pck);
 954                 clk_put(parent);
 955         }
 956 }
 957 #else
 958 void __init at91_add_device_isi(struct isi_platform_data *data,
 959                 bool use_pck_as_mck) {}
 960 #endif
 961
 962
 963 /* --------------------------------------------------------------------
 964  *  LCD Controller
 965  * -------------------------------------------------------------------- */
 966
 967 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 968 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 969 static struct atmel_lcdfb_pdata lcdc_data;
 970
 971 static struct resource lcdc_resources[] = {
 972         [0] = {
 973                 .start  = AT91SAM9G45_LCDC_BASE,
 974                 .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
 975                 .flags  = IORESOURCE_MEM,
 976         },
 977         [1] = {
 978                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
 979                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
 980                 .flags  = IORESOURCE_IRQ,
 981         },
 982 };
 983
 984 static struct platform_device at91_lcdc_device = {
 985         .id             = 0,
 986         .dev            = {
 987                                 .dma_mask               = &lcdc_dmamask,
 988                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 989                                 .platform_data          = &lcdc_data,
 990         },
 991         .resource       = lcdc_resources,
 992         .num_resources  = ARRAY_SIZE(lcdc_resources),
 993 };
 994
 995 void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
 996 {
 997         if (!data)
 998                 return;
 999
1000         if (cpu_is_at91sam9g45es())
1001                 at91_lcdc_device.name = "at91sam9g45es-lcdfb";
1002         else
1003                 at91_lcdc_device.name = "at91sam9g45-lcdfb";
1004
1005         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
1006
1007         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
1008         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
1009         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
1010         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
1011         at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
1012         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
1013         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
1014         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
1015         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
1016         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
1017         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
1018         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
1019         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
1020         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
1021         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
1022         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
1023         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
1024         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
1025         at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
1026         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
1027         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
1028         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
1029         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
1030         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
1031         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
1032         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
1033         at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
1034         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
1035         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
1036
1037         lcdc_data = *data;
1038         platform_device_register(&at91_lcdc_device);
1039 }
1040 #else
1041 void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
1042 #endif
1043
1044
1045 /* --------------------------------------------------------------------
1046  *  Timer/Counter block
1047  * -------------------------------------------------------------------- */
1048
1049 #ifdef CONFIG_ATMEL_TCLIB
1050 static struct resource tcb0_resources[] = {
1051         [0] = {
1052                 .start  = AT91SAM9G45_BASE_TCB0,
1053                 .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1054                 .flags  = IORESOURCE_MEM,
1055         },
1056         [1] = {
1057                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1058                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1059                 .flags  = IORESOURCE_IRQ,
1060         },
1061 };
1062
1063 static struct platform_device at91sam9g45_tcb0_device = {
1064         .name           = "atmel_tcb",
1065         .id             = 0,
1066         .resource       = tcb0_resources,
1067         .num_resources  = ARRAY_SIZE(tcb0_resources),
1068 };
1069
1070 /* TCB1 begins with TC3 */
1071 static struct resource tcb1_resources[] = {
1072         [0] = {
1073                 .start  = AT91SAM9G45_BASE_TCB1,
1074                 .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1075                 .flags  = IORESOURCE_MEM,
1076         },
1077         [1] = {
1078                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1079                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1080                 .flags  = IORESOURCE_IRQ,
1081         },
1082 };
1083
1084 static struct platform_device at91sam9g45_tcb1_device = {
1085         .name           = "atmel_tcb",
1086         .id             = 1,
1087         .resource       = tcb1_resources,
1088         .num_resources  = ARRAY_SIZE(tcb1_resources),
1089 };
1090
1091 static void __init at91_add_device_tc(void)
1092 {
1093         platform_device_register(&at91sam9g45_tcb0_device);
1094         platform_device_register(&at91sam9g45_tcb1_device);
1095 }
1096 #else
1097 static void __init at91_add_device_tc(void) { }
1098 #endif
1099
1100
1101 /* --------------------------------------------------------------------
1102  *  RTC
1103  * -------------------------------------------------------------------- */
1104
1105 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1106 static struct resource rtc_resources[] = {
1107         [0] = {
1108                 .start  = AT91SAM9G45_BASE_RTC,
1109                 .end    = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1110                 .flags  = IORESOURCE_MEM,
1111         },
1112         [1] = {
1113                 .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
1114                 .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
1115                 .flags  = IORESOURCE_IRQ,
1116         },
1117 };
1118
1119 static struct platform_device at91sam9g45_rtc_device = {
1120         .name           = "at91_rtc",
1121         .id             = -1,
1122         .resource       = rtc_resources,
1123         .num_resources  = ARRAY_SIZE(rtc_resources),
1124 };
1125
1126 static void __init at91_add_device_rtc(void)
1127 {
1128         platform_device_register(&at91sam9g45_rtc_device);
1129 }
1130 #else
1131 static void __init at91_add_device_rtc(void) {}
1132 #endif
1133
1134
1135 /* --------------------------------------------------------------------
1136  *  Touchscreen
1137  * -------------------------------------------------------------------- */
1138
1139 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1140 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1141 static struct at91_tsadcc_data tsadcc_data;
1142
1143 static struct resource tsadcc_resources[] = {
1144         [0] = {
1145                 .start  = AT91SAM9G45_BASE_TSC,
1146                 .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1147                 .flags  = IORESOURCE_MEM,
1148         },
1149         [1] = {
1150                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1151                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1152                 .flags  = IORESOURCE_IRQ,
1153         }
1154 };
1155
1156 static struct platform_device at91sam9g45_tsadcc_device = {
1157         .name           = "atmel_tsadcc",
1158         .id             = -1,
1159         .dev            = {
1160                                 .dma_mask               = &tsadcc_dmamask,
1161                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1162                                 .platform_data          = &tsadcc_data,
1163         },
1164         .resource       = tsadcc_resources,
1165         .num_resources  = ARRAY_SIZE(tsadcc_resources),
1166 };
1167
1168 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1169 {
1170         if (!data)
1171                 return;
1172
1173         at91_set_gpio_input(AT91_PIN_PD20, 0);  /* AD0_XR */
1174         at91_set_gpio_input(AT91_PIN_PD21, 0);  /* AD1_XL */
1175         at91_set_gpio_input(AT91_PIN_PD22, 0);  /* AD2_YT */
1176         at91_set_gpio_input(AT91_PIN_PD23, 0);  /* AD3_TB */
1177
1178         tsadcc_data = *data;
1179         platform_device_register(&at91sam9g45_tsadcc_device);
1180 }
1181 #else
1182 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1183 #endif
1184
1185
1186 /* --------------------------------------------------------------------
1187  *  ADC
1188  * -------------------------------------------------------------------- */
1189
1190 #if IS_ENABLED(CONFIG_AT91_ADC)
1191 static struct at91_adc_data adc_data;
1192
1193 static struct resource adc_resources[] = {
1194         [0] = {
1195                 .start  = AT91SAM9G45_BASE_TSC,
1196                 .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1197                 .flags  = IORESOURCE_MEM,
1198         },
1199         [1] = {
1200                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1201                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1202                 .flags  = IORESOURCE_IRQ,
1203         }
1204 };
1205
1206 static struct platform_device at91_adc_device = {
1207         .name           = "at91sam9g45-adc",
1208         .id             = -1,
1209         .dev            = {
1210                                 .platform_data  = &adc_data,
1211         },
1212         .resource       = adc_resources,
1213         .num_resources  = ARRAY_SIZE(adc_resources),
1214 };
1215
1216 static struct at91_adc_trigger at91_adc_triggers[] = {
1217         [0] = {
1218                 .name = "external-rising",
1219                 .value = 1,
1220                 .is_external = true,
1221         },
1222         [1] = {
1223                 .name = "external-falling",
1224                 .value = 2,
1225                 .is_external = true,
1226         },
1227         [2] = {
1228                 .name = "external-any",
1229                 .value = 3,
1230                 .is_external = true,
1231         },
1232         [3] = {
1233                 .name = "continuous",
1234                 .value = 6,
1235                 .is_external = false,
1236         },
1237 };
1238
1239 static struct at91_adc_reg_desc at91_adc_register_g45 = {
1240         .channel_base = AT91_ADC_CHR(0),
1241         .drdy_mask = AT91_ADC_DRDY,
1242         .status_register = AT91_ADC_SR,
1243         .trigger_register = 0x08,
1244 };
1245
1246 void __init at91_add_device_adc(struct at91_adc_data *data)
1247 {
1248         if (!data)
1249                 return;
1250
1251         if (test_bit(0, &data->channels_used))
1252                 at91_set_gpio_input(AT91_PIN_PD20, 0);
1253         if (test_bit(1, &data->channels_used))
1254                 at91_set_gpio_input(AT91_PIN_PD21, 0);
1255         if (test_bit(2, &data->channels_used))
1256                 at91_set_gpio_input(AT91_PIN_PD22, 0);
1257         if (test_bit(3, &data->channels_used))
1258                 at91_set_gpio_input(AT91_PIN_PD23, 0);
1259         if (test_bit(4, &data->channels_used))
1260                 at91_set_gpio_input(AT91_PIN_PD24, 0);
1261         if (test_bit(5, &data->channels_used))
1262                 at91_set_gpio_input(AT91_PIN_PD25, 0);
1263         if (test_bit(6, &data->channels_used))
1264                 at91_set_gpio_input(AT91_PIN_PD26, 0);
1265         if (test_bit(7, &data->channels_used))
1266                 at91_set_gpio_input(AT91_PIN_PD27, 0);
1267
1268         if (data->use_external_triggers)
1269                 at91_set_A_periph(AT91_PIN_PD28, 0);
1270
1271         data->num_channels = 8;
1272         data->startup_time = 40;
1273         data->registers = &at91_adc_register_g45;
1274         data->trigger_number = 4;
1275         data->trigger_list = at91_adc_triggers;
1276
1277         adc_data = *data;
1278         platform_device_register(&at91_adc_device);
1279 }
1280 #else
1281 void __init at91_add_device_adc(struct at91_adc_data *data) {}
1282 #endif
1283
1284 /* --------------------------------------------------------------------
1285  *  RTT
1286  * -------------------------------------------------------------------- */
1287
1288 static struct resource rtt_resources[] = {
1289         {
1290                 .start  = AT91SAM9G45_BASE_RTT,
1291                 .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1292                 .flags  = IORESOURCE_MEM,
1293         }, {
1294                 .flags  = IORESOURCE_MEM,
1295         }, {
1296                 .flags  = IORESOURCE_IRQ,
1297         }
1298 };
1299
1300 static struct platform_device at91sam9g45_rtt_device = {
1301         .name           = "at91_rtt",
1302         .id             = 0,
1303         .resource       = rtt_resources,
1304 };
1305
1306 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1307 static void __init at91_add_device_rtt_rtc(void)
1308 {
1309         at91sam9g45_rtt_device.name = "rtc-at91sam9";
1310         /*
1311          * The second resource is needed:
1312          * GPBR will serve as the storage for RTC time offset
1313          */
1314         at91sam9g45_rtt_device.num_resources = 3;
1315         rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1316                                  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1317         rtt_resources[1].end = rtt_resources[1].start + 3;
1318         rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1319         rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1320 }
1321 #else
1322 static void __init at91_add_device_rtt_rtc(void)
1323 {
1324         /* Only one resource is needed: RTT not used as RTC */
1325         at91sam9g45_rtt_device.num_resources = 1;
1326 }
1327 #endif
1328
1329 static void __init at91_add_device_rtt(void)
1330 {
1331         at91_add_device_rtt_rtc();
1332         platform_device_register(&at91sam9g45_rtt_device);
1333 }
1334
1335
1336 /* --------------------------------------------------------------------
1337  *  TRNG
1338  * -------------------------------------------------------------------- */
1339
1340 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1341 static struct resource trng_resources[] = {
1342         {
1343                 .start  = AT91SAM9G45_BASE_TRNG,
1344                 .end    = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1345                 .flags  = IORESOURCE_MEM,
1346         },
1347 };
1348
1349 static struct platform_device at91sam9g45_trng_device = {
1350         .name           = "atmel-trng",
1351         .id             = -1,
1352         .resource       = trng_resources,
1353         .num_resources  = ARRAY_SIZE(trng_resources),
1354 };
1355
1356 static void __init at91_add_device_trng(void)
1357 {
1358         platform_device_register(&at91sam9g45_trng_device);
1359 }
1360 #else
1361 static void __init at91_add_device_trng(void) {}
1362 #endif
1363
1364 /* --------------------------------------------------------------------
1365  *  Watchdog
1366  * -------------------------------------------------------------------- */
1367
1368 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1369 static struct resource wdt_resources[] = {
1370         {
1371                 .start  = AT91SAM9G45_BASE_WDT,
1372                 .end    = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1373                 .flags  = IORESOURCE_MEM,
1374         }
1375 };
1376
1377 static struct platform_device at91sam9g45_wdt_device = {
1378         .name           = "at91_wdt",
1379         .id             = -1,
1380         .resource       = wdt_resources,
1381         .num_resources  = ARRAY_SIZE(wdt_resources),
1382 };
1383
1384 static void __init at91_add_device_watchdog(void)
1385 {
1386         platform_device_register(&at91sam9g45_wdt_device);
1387 }
1388 #else
1389 static void __init at91_add_device_watchdog(void) {}
1390 #endif
1391
1392
1393 /* --------------------------------------------------------------------
1394  *  PWM
1395  * --------------------------------------------------------------------*/
1396
1397 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1398 static u32 pwm_mask;
1399
1400 static struct resource pwm_resources[] = {
1401         [0] = {
1402                 .start  = AT91SAM9G45_BASE_PWMC,
1403                 .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1404                 .flags  = IORESOURCE_MEM,
1405         },
1406         [1] = {
1407                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1408                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1409                 .flags  = IORESOURCE_IRQ,
1410         },
1411 };
1412
1413 static struct platform_device at91sam9g45_pwm0_device = {
1414         .name   = "atmel_pwm",
1415         .id     = -1,
1416         .dev    = {
1417                 .platform_data          = &pwm_mask,
1418         },
1419         .resource       = pwm_resources,
1420         .num_resources  = ARRAY_SIZE(pwm_resources),
1421 };
1422
1423 void __init at91_add_device_pwm(u32 mask)
1424 {
1425         if (mask & (1 << AT91_PWM0))
1426                 at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
1427
1428         if (mask & (1 << AT91_PWM1))
1429                 at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
1430
1431         if (mask & (1 << AT91_PWM2))
1432                 at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
1433
1434         if (mask & (1 << AT91_PWM3))
1435                 at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
1436
1437         pwm_mask = mask;
1438
1439         platform_device_register(&at91sam9g45_pwm0_device);
1440 }
1441 #else
1442 void __init at91_add_device_pwm(u32 mask) {}
1443 #endif
1444
1445
1446 /* --------------------------------------------------------------------
1447  *  SSC -- Synchronous Serial Controller
1448  * -------------------------------------------------------------------- */
1449
1450 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1451 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1452
1453 static struct resource ssc0_resources[] = {
1454         [0] = {
1455                 .start  = AT91SAM9G45_BASE_SSC0,
1456                 .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1457                 .flags  = IORESOURCE_MEM,
1458         },
1459         [1] = {
1460                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1461                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1462                 .flags  = IORESOURCE_IRQ,
1463         },
1464 };
1465
1466 static struct platform_device at91sam9g45_ssc0_device = {
1467         .name   = "at91sam9g45_ssc",
1468         .id     = 0,
1469         .dev    = {
1470                 .dma_mask               = &ssc0_dmamask,
1471                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1472         },
1473         .resource       = ssc0_resources,
1474         .num_resources  = ARRAY_SIZE(ssc0_resources),
1475 };
1476
1477 static inline void configure_ssc0_pins(unsigned pins)
1478 {
1479         if (pins & ATMEL_SSC_TF)
1480                 at91_set_A_periph(AT91_PIN_PD1, 1);
1481         if (pins & ATMEL_SSC_TK)
1482                 at91_set_A_periph(AT91_PIN_PD0, 1);
1483         if (pins & ATMEL_SSC_TD)
1484                 at91_set_A_periph(AT91_PIN_PD2, 1);
1485         if (pins & ATMEL_SSC_RD)
1486                 at91_set_A_periph(AT91_PIN_PD3, 1);
1487         if (pins & ATMEL_SSC_RK)
1488                 at91_set_A_periph(AT91_PIN_PD4, 1);
1489         if (pins & ATMEL_SSC_RF)
1490                 at91_set_A_periph(AT91_PIN_PD5, 1);
1491 }
1492
1493 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1494
1495 static struct resource ssc1_resources[] = {
1496         [0] = {
1497                 .start  = AT91SAM9G45_BASE_SSC1,
1498                 .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1499                 .flags  = IORESOURCE_MEM,
1500         },
1501         [1] = {
1502                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1503                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1504                 .flags  = IORESOURCE_IRQ,
1505         },
1506 };
1507
1508 static struct platform_device at91sam9g45_ssc1_device = {
1509         .name   = "at91sam9g45_ssc",
1510         .id     = 1,
1511         .dev    = {
1512                 .dma_mask               = &ssc1_dmamask,
1513                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1514         },
1515         .resource       = ssc1_resources,
1516         .num_resources  = ARRAY_SIZE(ssc1_resources),
1517 };
1518
1519 static inline void configure_ssc1_pins(unsigned pins)
1520 {
1521         if (pins & ATMEL_SSC_TF)
1522                 at91_set_A_periph(AT91_PIN_PD14, 1);
1523         if (pins & ATMEL_SSC_TK)
1524                 at91_set_A_periph(AT91_PIN_PD12, 1);
1525         if (pins & ATMEL_SSC_TD)
1526                 at91_set_A_periph(AT91_PIN_PD10, 1);
1527         if (pins & ATMEL_SSC_RD)
1528                 at91_set_A_periph(AT91_PIN_PD11, 1);
1529         if (pins & ATMEL_SSC_RK)
1530                 at91_set_A_periph(AT91_PIN_PD13, 1);
1531         if (pins & ATMEL_SSC_RF)
1532                 at91_set_A_periph(AT91_PIN_PD15, 1);
1533 }
1534
1535 /*
1536  * SSC controllers are accessed through library code, instead of any
1537  * kind of all-singing/all-dancing driver.  For example one could be
1538  * used by a particular I2S audio codec's driver, while another one
1539  * on the same system might be used by a custom data capture driver.
1540  */
1541 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1542 {
1543         struct platform_device *pdev;
1544
1545         /*
1546          * NOTE: caller is responsible for passing information matching
1547          * "pins" to whatever will be using each particular controller.
1548          */
1549         switch (id) {
1550         case AT91SAM9G45_ID_SSC0:
1551                 pdev = &at91sam9g45_ssc0_device;
1552                 configure_ssc0_pins(pins);
1553                 break;
1554         case AT91SAM9G45_ID_SSC1:
1555                 pdev = &at91sam9g45_ssc1_device;
1556                 configure_ssc1_pins(pins);
1557                 break;
1558         default:
1559                 return;
1560         }
1561
1562         platform_device_register(pdev);
1563 }
1564
1565 #else
1566 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1567 #endif
1568
1569
1570 /* --------------------------------------------------------------------
1571  *  UART
1572  * -------------------------------------------------------------------- */
1573
1574 #if defined(CONFIG_SERIAL_ATMEL)
1575 static struct resource dbgu_resources[] = {
1576         [0] = {
1577                 .start  = AT91SAM9G45_BASE_DBGU,
1578                 .end    = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1579                 .flags  = IORESOURCE_MEM,
1580         },
1581         [1] = {
1582                 .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
1583                 .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
1584                 .flags  = IORESOURCE_IRQ,
1585         },
1586 };
1587
1588 static struct atmel_uart_data dbgu_data = {
1589         .use_dma_tx     = 0,
1590         .use_dma_rx     = 0,
1591         .rts_gpio       = -EINVAL,
1592 };
1593
1594 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1595
1596 static struct platform_device at91sam9g45_dbgu_device = {
1597         .name           = "atmel_usart",
1598         .id             = 0,
1599         .dev            = {
1600                                 .dma_mask               = &dbgu_dmamask,
1601                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1602                                 .platform_data          = &dbgu_data,
1603         },
1604         .resource       = dbgu_resources,
1605         .num_resources  = ARRAY_SIZE(dbgu_resources),
1606 };
1607
1608 static inline void configure_dbgu_pins(void)
1609 {
1610         at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
1611         at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
1612 }
1613
1614 static struct resource uart0_resources[] = {
1615         [0] = {
1616                 .start  = AT91SAM9G45_BASE_US0,
1617                 .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1618                 .flags  = IORESOURCE_MEM,
1619         },
1620         [1] = {
1621                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1622                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1623                 .flags  = IORESOURCE_IRQ,
1624         },
1625 };
1626
1627 static struct atmel_uart_data uart0_data = {
1628         .use_dma_tx     = 1,
1629         .use_dma_rx     = 1,
1630         .rts_gpio       = -EINVAL,
1631 };
1632
1633 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1634
1635 static struct platform_device at91sam9g45_uart0_device = {
1636         .name           = "atmel_usart",
1637         .id             = 1,
1638         .dev            = {
1639                                 .dma_mask               = &uart0_dmamask,
1640                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1641                                 .platform_data          = &uart0_data,
1642         },
1643         .resource       = uart0_resources,
1644         .num_resources  = ARRAY_SIZE(uart0_resources),
1645 };
1646
1647 static inline void configure_usart0_pins(unsigned pins)
1648 {
1649         at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
1650         at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
1651
1652         if (pins & ATMEL_UART_RTS)
1653                 at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
1654         if (pins & ATMEL_UART_CTS)
1655                 at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
1656 }
1657
1658 static struct resource uart1_resources[] = {
1659         [0] = {
1660                 .start  = AT91SAM9G45_BASE_US1,
1661                 .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1662                 .flags  = IORESOURCE_MEM,
1663         },
1664         [1] = {
1665                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1666                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1667                 .flags  = IORESOURCE_IRQ,
1668         },
1669 };
1670
1671 static struct atmel_uart_data uart1_data = {
1672         .use_dma_tx     = 1,
1673         .use_dma_rx     = 1,
1674         .rts_gpio       = -EINVAL,
1675 };
1676
1677 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1678
1679 static struct platform_device at91sam9g45_uart1_device = {
1680         .name           = "atmel_usart",
1681         .id             = 2,
1682         .dev            = {
1683                                 .dma_mask               = &uart1_dmamask,
1684                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1685                                 .platform_data          = &uart1_data,
1686         },
1687         .resource       = uart1_resources,
1688         .num_resources  = ARRAY_SIZE(uart1_resources),
1689 };
1690
1691 static inline void configure_usart1_pins(unsigned pins)
1692 {
1693         at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
1694         at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
1695
1696         if (pins & ATMEL_UART_RTS)
1697                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
1698         if (pins & ATMEL_UART_CTS)
1699                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
1700 }
1701
1702 static struct resource uart2_resources[] = {
1703         [0] = {
1704                 .start  = AT91SAM9G45_BASE_US2,
1705                 .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1706                 .flags  = IORESOURCE_MEM,
1707         },
1708         [1] = {
1709                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1710                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1711                 .flags  = IORESOURCE_IRQ,
1712         },
1713 };
1714
1715 static struct atmel_uart_data uart2_data = {
1716         .use_dma_tx     = 1,
1717         .use_dma_rx     = 1,
1718         .rts_gpio       = -EINVAL,
1719 };
1720
1721 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1722
1723 static struct platform_device at91sam9g45_uart2_device = {
1724         .name           = "atmel_usart",
1725         .id             = 3,
1726         .dev            = {
1727                                 .dma_mask               = &uart2_dmamask,
1728                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1729                                 .platform_data          = &uart2_data,
1730         },
1731         .resource       = uart2_resources,
1732         .num_resources  = ARRAY_SIZE(uart2_resources),
1733 };
1734
1735 static inline void configure_usart2_pins(unsigned pins)
1736 {
1737         at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
1738         at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
1739
1740         if (pins & ATMEL_UART_RTS)
1741                 at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
1742         if (pins & ATMEL_UART_CTS)
1743                 at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
1744 }
1745
1746 static struct resource uart3_resources[] = {
1747         [0] = {
1748                 .start  = AT91SAM9G45_BASE_US3,
1749                 .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1750                 .flags  = IORESOURCE_MEM,
1751         },
1752         [1] = {
1753                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1754                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1755                 .flags  = IORESOURCE_IRQ,
1756         },
1757 };
1758
1759 static struct atmel_uart_data uart3_data = {
1760         .use_dma_tx     = 1,
1761         .use_dma_rx     = 1,
1762         .rts_gpio       = -EINVAL,
1763 };
1764
1765 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1766
1767 static struct platform_device at91sam9g45_uart3_device = {
1768         .name           = "atmel_usart",
1769         .id             = 4,
1770         .dev            = {
1771                                 .dma_mask               = &uart3_dmamask,
1772                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1773                                 .platform_data          = &uart3_data,
1774         },
1775         .resource       = uart3_resources,
1776         .num_resources  = ARRAY_SIZE(uart3_resources),
1777 };
1778
1779 static inline void configure_usart3_pins(unsigned pins)
1780 {
1781         at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
1782         at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
1783
1784         if (pins & ATMEL_UART_RTS)
1785                 at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
1786         if (pins & ATMEL_UART_CTS)
1787                 at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
1788 }
1789
1790 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1791
1792 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1793 {
1794         struct platform_device *pdev;
1795         struct atmel_uart_data *pdata;
1796
1797         switch (id) {
1798                 case 0:         /* DBGU */
1799                         pdev = &at91sam9g45_dbgu_device;
1800                         configure_dbgu_pins();
1801                         break;
1802                 case AT91SAM9G45_ID_US0:
1803                         pdev = &at91sam9g45_uart0_device;
1804                         configure_usart0_pins(pins);
1805                         break;
1806                 case AT91SAM9G45_ID_US1:
1807                         pdev = &at91sam9g45_uart1_device;
1808                         configure_usart1_pins(pins);
1809                         break;
1810                 case AT91SAM9G45_ID_US2:
1811                         pdev = &at91sam9g45_uart2_device;
1812                         configure_usart2_pins(pins);
1813                         break;
1814                 case AT91SAM9G45_ID_US3:
1815                         pdev = &at91sam9g45_uart3_device;
1816                         configure_usart3_pins(pins);
1817                         break;
1818                 default:
1819                         return;
1820         }
1821         pdata = pdev->dev.platform_data;
1822         pdata->num = portnr;            /* update to mapped ID */
1823
1824         if (portnr < ATMEL_MAX_UART)
1825                 at91_uarts[portnr] = pdev;
1826 }
1827
1828 void __init at91_add_device_serial(void)
1829 {
1830         int i;
1831
1832         for (i = 0; i < ATMEL_MAX_UART; i++) {
1833                 if (at91_uarts[i])
1834                         platform_device_register(at91_uarts[i]);
1835         }
1836 }
1837 #else
1838 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1839 void __init at91_add_device_serial(void) {}
1840 #endif
1841
1842 /* --------------------------------------------------------------------
1843  *  SHA1/SHA256
1844  * -------------------------------------------------------------------- */
1845
1846 #if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1847 static struct resource sha_resources[] = {
1848         {
1849                 .start  = AT91SAM9G45_BASE_SHA,
1850                 .end    = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1851                 .flags  = IORESOURCE_MEM,
1852         },
1853         [1] = {
1854                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1855                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1856                 .flags  = IORESOURCE_IRQ,
1857         },
1858 };
1859
1860 static struct platform_device at91sam9g45_sha_device = {
1861         .name   = "atmel_sha",
1862         .id             = -1,
1863         .resource       = sha_resources,
1864         .num_resources  = ARRAY_SIZE(sha_resources),
1865 };
1866
1867 static void __init at91_add_device_sha(void)
1868 {
1869         platform_device_register(&at91sam9g45_sha_device);
1870 }
1871 #else
1872 static void __init at91_add_device_sha(void) {}
1873 #endif
1874
1875 /* --------------------------------------------------------------------
1876  *  DES/TDES
1877  * -------------------------------------------------------------------- */
1878
1879 #if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1880 static struct resource tdes_resources[] = {
1881         [0] = {
1882                 .start  = AT91SAM9G45_BASE_TDES,
1883                 .end    = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1884                 .flags  = IORESOURCE_MEM,
1885         },
1886         [1] = {
1887                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1888                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1889                 .flags  = IORESOURCE_IRQ,
1890         },
1891 };
1892
1893 static struct platform_device at91sam9g45_tdes_device = {
1894         .name   = "atmel_tdes",
1895         .id             = -1,
1896         .resource       = tdes_resources,
1897         .num_resources  = ARRAY_SIZE(tdes_resources),
1898 };
1899
1900 static void __init at91_add_device_tdes(void)
1901 {
1902         platform_device_register(&at91sam9g45_tdes_device);
1903 }
1904 #else
1905 static void __init at91_add_device_tdes(void) {}
1906 #endif
1907
1908 /* --------------------------------------------------------------------
1909  *  AES
1910  * -------------------------------------------------------------------- */
1911
1912 #if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1913 static struct crypto_platform_data aes_data;
1914 static struct crypto_dma_data alt_atslave;
1915 static u64 aes_dmamask = DMA_BIT_MASK(32);
1916
1917 static struct resource aes_resources[] = {
1918         [0] = {
1919                 .start  = AT91SAM9G45_BASE_AES,
1920                 .end    = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1921                 .flags  = IORESOURCE_MEM,
1922         },
1923         [1] = {
1924                 .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1925                 .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1926                 .flags  = IORESOURCE_IRQ,
1927         },
1928 };
1929
1930 static struct platform_device at91sam9g45_aes_device = {
1931         .name   = "atmel_aes",
1932         .id             = -1,
1933         .dev    = {
1934                 .dma_mask               = &aes_dmamask,
1935                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1936                 .platform_data          = &aes_data,
1937         },
1938         .resource       = aes_resources,
1939         .num_resources  = ARRAY_SIZE(aes_resources),
1940 };
1941
1942 static void __init at91_add_device_aes(void)
1943 {
1944         struct at_dma_slave     *atslave;
1945
1946         /* DMA TX slave channel configuration */
1947         atslave = &alt_atslave.txdata;
1948         atslave->dma_dev = &at_hdmac_device.dev;
1949         atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_SRC_H2SEL_HW |
1950                                                 ATC_SRC_PER(AT_DMA_ID_AES_RX);
1951
1952         /* DMA RX slave channel configuration */
1953         atslave = &alt_atslave.rxdata;
1954         atslave->dma_dev = &at_hdmac_device.dev;
1955         atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_DST_H2SEL_HW |
1956                                                 ATC_DST_PER(AT_DMA_ID_AES_TX);
1957
1958         aes_data.dma_slave = &alt_atslave;
1959         platform_device_register(&at91sam9g45_aes_device);
1960 }
1961 #else
1962 static void __init at91_add_device_aes(void) {}
1963 #endif
1964
1965 /* -------------------------------------------------------------------- */
1966 /*
1967  * These devices are always present and don't need any board-specific
1968  * setup.
1969  */
1970 static int __init at91_add_standard_devices(void)
1971 {
1972         if (of_have_populated_dt())
1973                 return 0;
1974
1975         at91_add_device_hdmac();
1976         at91_add_device_rtc();
1977         at91_add_device_rtt();
1978         at91_add_device_trng();
1979         at91_add_device_watchdog();
1980         at91_add_device_tc();
1981         at91_add_device_sha();
1982         at91_add_device_tdes();
1983         at91_add_device_aes();
1984         return 0;
1985 }
1986
1987 arch_initcall(at91_add_standard_devices);