1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
10 #include <linux/linkage.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
14 #include <asm/assembler.h>
15 #include <asm/ptrace.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/memory.h>
19 #include <asm/thread_info.h>
25 * Kernel startup entry point.
26 * ---------------------------
28 * This is normally called from the decompressor code. The requirements
29 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
32 * See linux/arch/arm/tools/mach-types for the complete list of machine
39 #ifdef CONFIG_CPU_THUMBONLY
46 THUMB( badr r9, 1f ) @ Kernel is always entered in ARM.
47 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
48 THUMB( .thumb ) @ switch to Thumb now.
52 #ifdef CONFIG_ARM_VIRT_EXT
55 @ ensure svc mode and all interrupts masked
56 safe_svcmode_maskall r9
58 #if defined(CONFIG_CPU_CP15)
59 mrc p15, 0, r9, c0, c0 @ get processor id
60 #elif defined(CONFIG_CPU_V7M)
61 ldr r9, =BASEADDR_V7M_SCB
62 ldr r9, [r9, V7M_SCB_CPUID]
64 ldr r9, =CONFIG_PROCESSOR_ID
66 bl __lookup_processor_type @ r5=procinfo r9=cpuid
67 movs r10, r5 @ invalid processor (r5=0)?
68 beq __error_p @ yes, error 'p'
74 badr lr, 1f @ return (PIC) address
75 ldr r12, [r10, #PROCINFO_INITFUNC]
78 1: ldr lr, =__mmap_switched
84 ENTRY(secondary_startup)
86 * Common entry point for secondary CPUs.
88 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
89 * the processor type - there is no need to check the machine type
90 * as it has already been validated by the primary processor.
92 #ifdef CONFIG_ARM_VIRT_EXT
93 bl __hyp_stub_install_secondary
95 safe_svcmode_maskall r9
97 #ifndef CONFIG_CPU_CP15
98 ldr r9, =CONFIG_PROCESSOR_ID
100 mrc p15, 0, r9, c0, c0 @ get processor id
102 bl __lookup_processor_type @ r5=procinfo r9=cpuid
103 movs r10, r5 @ invalid processor?
104 beq __error_p @ yes, error 'p'
106 ldr r7, __secondary_data
108 #ifdef CONFIG_ARM_MPU
109 bl __secondary_setup_mpu @ Initialize the MPU
112 badr lr, 1f @ return (PIC) address
113 ldr r12, [r10, #PROCINFO_INITFUNC]
116 1: bl __after_proc_init
117 ldr sp, [r7, #12] @ set up the stack pointer
119 b secondary_start_kernel
120 ENDPROC(secondary_startup)
122 .type __secondary_data, %object
125 #endif /* CONFIG_SMP */
128 * Set the Control Register and Read the process ID.
132 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
133 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
134 #ifdef CONFIG_ARM_MPU
135 M_CLASS(ldr r3, [r12, 0x50])
136 AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
137 and r3, r3, #(MMFR0_PMSA) @ PMSA field
138 teq r3, #(MMFR0_PMSAv7) @ PMSA v7
140 teq r3, #(MMFR0_PMSAv8) @ PMSA v8
142 * Memory region attributes for PMSAv8:
146 * DEVICE_nGnRnE 000 00000000
147 * NORMAL 001 11111111
149 ldreq r3, =PMSAv8_MAIR(0x00, PMSAv8_RGN_DEVICE_nGnRnE) | \
150 PMSAv8_MAIR(0xff, PMSAv8_RGN_NORMAL)
151 AR_CLASS(mcreq p15, 0, r3, c10, c2, 0) @ MAIR 0
152 M_CLASS(streq r3, [r12, #PMSAv8_MAIR0])
154 AR_CLASS(mcreq p15, 0, r3, c10, c2, 1) @ MAIR 1
155 M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
159 #ifdef CONFIG_CPU_CP15
161 * CP15 system control register value returned in r0 from
162 * the CPU init function.
165 #ifdef CONFIG_ARM_MPU
166 biceq r0, r0, #CR_BR @ Disable the 'default mem-map'
167 orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on)
169 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
174 #ifdef CONFIG_CPU_DCACHE_DISABLE
177 #ifdef CONFIG_CPU_BPREDICT_DISABLE
180 #ifdef CONFIG_CPU_ICACHE_DISABLE
183 mcr p15, 0, r0, c1, c0, 0 @ write control reg
185 #elif defined (CONFIG_CPU_V7M)
186 #ifdef CONFIG_ARM_MPU
187 ldreq r3, [r12, MPU_CTRL]
188 biceq r3, #MPU_CTRL_PRIVDEFENA
189 orreq r3, #MPU_CTRL_ENABLE
190 streq r3, [r12, MPU_CTRL]
193 /* For V7M systems we want to modify the CCR similarly to the SCTLR */
194 #ifdef CONFIG_CPU_DCACHE_DISABLE
195 bic r0, r0, #V7M_SCB_CCR_DC
197 #ifdef CONFIG_CPU_BPREDICT_DISABLE
198 bic r0, r0, #V7M_SCB_CCR_BP
200 #ifdef CONFIG_CPU_ICACHE_DISABLE
201 bic r0, r0, #V7M_SCB_CCR_IC
203 str r0, [r12, V7M_SCB_CCR]
204 #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
206 ENDPROC(__after_proc_init)
209 #ifdef CONFIG_ARM_MPU
212 #ifndef CONFIG_CPU_V7M
213 /* Set which MPU region should be programmed */
214 .macro set_region_nr tmp, rgnr, unused
215 mov \tmp, \rgnr @ Use static region numbers
216 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
219 /* Setup a single MPU region, either D or I side (D-side for unified) */
220 .macro setup_region bar, acr, sr, side = PMSAv7_DATA_SIDE, unused
221 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
222 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
223 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
226 .macro set_region_nr tmp, rgnr, base
228 str \tmp, [\base, #PMSAv7_RNR]
231 .macro setup_region bar, acr, sr, unused, base
234 str \bar, [\base, #PMSAv7_RBAR]
235 str \acr, [\base, #PMSAv7_RASR]
240 * Setup the MPU and initial MPU Regions. We create the following regions:
241 * Region 0: Use this for probing the MPU details, so leave disabled.
242 * Region 1: Background region - covers the whole of RAM as strongly ordered
243 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
244 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
246 * r6: Value to be written to DRSR (and IRSR if required) for PMSAv7_RAM_REGION
252 /* Probe for v7 PMSA compliance */
253 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
254 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
256 AR_CLASS(mrc p15, 0, r0, c0, c1, 4) @ Read ID_MMFR0
257 M_CLASS(ldr r0, [r12, 0x50])
258 and r0, r0, #(MMFR0_PMSA) @ PMSA field
259 teq r0, #(MMFR0_PMSAv7) @ PMSA v7
261 teq r0, #(MMFR0_PMSAv8) @ PMSA v8
267 ENTRY(__setup_pmsa_v7)
268 /* Calculate the size of a region covering just the kernel */
269 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
270 ldr r6, =(_end) @ Cover whole kernel
271 sub r6, r6, r5 @ Minimum size of region to map
272 clz r6, r6 @ Region size must be 2^N...
273 rsb r6, r6, #31 @ ...so round up region size
274 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
275 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
277 /* Determine whether the D/I-side memory map is unified. We set the
278 * flags here and continue to use them for the rest of this function */
279 AR_CLASS(mrc p15, 0, r0, c0, c0, 4) @ MPUIR
280 M_CLASS(ldr r0, [r12, #MPU_TYPE])
281 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
283 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
285 /* Setup second region first to free up r6 */
286 set_region_nr r0, #PMSAv7_RAM_REGION, r12
288 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
289 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
290 ldr r5,=(PMSAv7_AP_PL1RW_PL0RW | PMSAv7_RGN_NORMAL)
292 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
293 beq 1f @ Memory-map not unified
294 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
297 /* First/background region */
298 set_region_nr r0, #PMSAv7_BG_REGION, r12
300 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
301 mov r0, #0 @ BG region starts at 0x0
302 ldr r5,=(PMSAv7_ACR_XN | PMSAv7_RGN_STRONGLY_ORDERED | PMSAv7_AP_PL1RW_PL0NA)
303 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled
305 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
306 beq 2f @ Memory-map not unified
307 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
310 #ifdef CONFIG_XIP_KERNEL
311 set_region_nr r0, #PMSAv7_ROM_REGION, r12
314 ldr r5,=(PMSAv7_AP_PL1RO_PL0NA | PMSAv7_RGN_NORMAL)
316 ldr r0, =CONFIG_XIP_PHYS_ADDR @ ROM start
317 ldr r6, =(_exiprom) @ ROM end
318 sub r6, r6, r0 @ Minimum size of region to map
319 clz r6, r6 @ Region size must be 2^N...
320 rsb r6, r6, #31 @ ...so round up region size
321 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
322 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
324 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
325 beq 3f @ Memory-map not unified
326 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
330 ENDPROC(__setup_pmsa_v7)
332 ENTRY(__setup_pmsa_v8)
334 AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
335 M_CLASS(str r0, [r12, #PMSAv8_RNR])
338 #ifdef CONFIG_XIP_KERNEL
339 ldr r5, =CONFIG_XIP_PHYS_ADDR @ ROM start
340 ldr r6, =(_exiprom) @ ROM end
342 bic r6, r6, #(PMSAv8_MINALIGN - 1)
344 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
345 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
347 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
348 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
349 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)])
350 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
353 ldr r5, =KERNEL_START
356 bic r6, r6, #(PMSAv8_MINALIGN - 1)
358 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED)
359 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
361 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
362 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
363 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)])
364 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
366 /* Setup Background: 0x0 - min(KERNEL_START, XIP_PHYS_ADDR) */
367 #ifdef CONFIG_XIP_KERNEL
368 ldr r6, =KERNEL_START
369 ldr r5, =CONFIG_XIP_PHYS_ADDR
373 ldr r6, =KERNEL_START
380 bic r6, r6, #(PMSAv8_MINALIGN - 1)
382 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
383 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
385 AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2
386 AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2
387 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)])
388 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
391 /* Setup Background: max(KERNEL_END, _exiprom) - 0xffffffff */
392 #ifdef CONFIG_XIP_KERNEL
401 bic r6, r6, #(PMSAv8_MINALIGN - 1)
403 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
404 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
406 AR_CLASS(mcr p15, 0, r5, c6, c9, 4) @ PRBAR3
407 AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3
408 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)])
409 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
411 #ifdef CONFIG_XIP_KERNEL
412 /* Setup Background: min(_exiprom, KERNEL_END) - max(KERNEL_START, XIP_PHYS_ADDR) */
418 ldr r6, =KERNEL_START
419 ldr r0, =CONFIG_XIP_PHYS_ADDR
424 bic r6, r6, #(PMSAv8_MINALIGN - 1)
426 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN)
427 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
429 #ifdef CONFIG_CPU_V7M
430 /* There is no alias for n == 4 */
432 str r0, [r12, #PMSAv8_RNR] @ PRSEL
435 str r5, [r12, #PMSAv8_RBAR_A(0)]
436 str r6, [r12, #PMSAv8_RLAR_A(0)]
438 mcr p15, 0, r5, c6, c10, 0 @ PRBAR4
439 mcr p15, 0, r6, c6, c10, 1 @ PRLAR4
443 ENDPROC(__setup_pmsa_v8)
447 * r6: pointer at mpu_rgn_info
451 ENTRY(__secondary_setup_mpu)
452 /* Use MPU region info supplied by __cpu_up */
453 ldr r6, [r7] @ get secondary_data.mpu_rgn_info
455 /* Probe for v7 PMSA compliance */
456 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
457 and r0, r0, #(MMFR0_PMSA) @ PMSA field
458 teq r0, #(MMFR0_PMSAv7) @ PMSA v7
459 beq __secondary_setup_pmsa_v7
460 teq r0, #(MMFR0_PMSAv8) @ PMSA v8
461 beq __secondary_setup_pmsa_v8
463 ENDPROC(__secondary_setup_mpu)
466 * r6: pointer at mpu_rgn_info
468 ENTRY(__secondary_setup_pmsa_v7)
469 /* Determine whether the D/I-side memory map is unified. We set the
470 * flags here and continue to use them for the rest of this function */
471 mrc p15, 0, r0, c0, c0, 4 @ MPUIR
472 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
475 ldr r4, [r6, #MPU_RNG_INFO_USED]
476 mov r5, #MPU_RNG_SIZE
477 add r3, r6, #MPU_RNG_INFO_RNGS
481 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
482 sub r3, r3, #MPU_RNG_SIZE
488 ldr r0, [r3, #MPU_RGN_DRBAR]
489 ldr r6, [r3, #MPU_RGN_DRSR]
490 ldr r5, [r3, #MPU_RGN_DRACR]
492 setup_region r0, r5, r6, PMSAv7_DATA_SIDE
494 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE
497 mrc p15, 0, r0, c0, c0, 4 @ Reevaluate the MPUIR
502 ENDPROC(__secondary_setup_pmsa_v7)
504 ENTRY(__secondary_setup_pmsa_v8)
505 ldr r4, [r6, #MPU_RNG_INFO_USED]
506 #ifndef CONFIG_XIP_KERNEL
509 mov r5, #MPU_RNG_SIZE
510 add r3, r6, #MPU_RNG_INFO_RNGS
514 sub r3, r3, #MPU_RNG_SIZE
517 mcr p15, 0, r4, c6, c2, 1 @ PRSEL
520 ldr r5, [r3, #MPU_RGN_PRBAR]
521 ldr r6, [r3, #MPU_RGN_PRLAR]
523 mcr p15, 0, r5, c6, c3, 0 @ PRBAR
524 mcr p15, 0, r6, c6, c3, 1 @ PRLAR
530 ENDPROC(__secondary_setup_pmsa_v8)
531 #endif /* CONFIG_SMP */
532 #endif /* CONFIG_ARM_MPU */
533 #include "head-common.S"