arch/arm/include/asm/cputype.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_ARM_CPUTYPE_H
   3 #define __ASM_ARM_CPUTYPE_H
   4
   5 #include <linux/stringify.h>
   6 #include <linux/kernel.h>
   7
   8 #define CPUID_ID        0
   9 #define CPUID_CACHETYPE 1
  10 #define CPUID_TCM       2
  11 #define CPUID_TLBTYPE   3
  12 #define CPUID_MPUIR     4
  13 #define CPUID_MPIDR     5
  14 #define CPUID_REVIDR    6
  15
  16 #ifdef CONFIG_CPU_V7M
  17 #define CPUID_EXT_PFR0  0x40
  18 #define CPUID_EXT_PFR1  0x44
  19 #define CPUID_EXT_DFR0  0x48
  20 #define CPUID_EXT_AFR0  0x4c
  21 #define CPUID_EXT_MMFR0 0x50
  22 #define CPUID_EXT_MMFR1 0x54
  23 #define CPUID_EXT_MMFR2 0x58
  24 #define CPUID_EXT_MMFR3 0x5c
  25 #define CPUID_EXT_ISAR0 0x60
  26 #define CPUID_EXT_ISAR1 0x64
  27 #define CPUID_EXT_ISAR2 0x68
  28 #define CPUID_EXT_ISAR3 0x6c
  29 #define CPUID_EXT_ISAR4 0x70
  30 #define CPUID_EXT_ISAR5 0x74
  31 #else
  32 #define CPUID_EXT_PFR0  "c1, 0"
  33 #define CPUID_EXT_PFR1  "c1, 1"
  34 #define CPUID_EXT_DFR0  "c1, 2"
  35 #define CPUID_EXT_AFR0  "c1, 3"
  36 #define CPUID_EXT_MMFR0 "c1, 4"
  37 #define CPUID_EXT_MMFR1 "c1, 5"
  38 #define CPUID_EXT_MMFR2 "c1, 6"
  39 #define CPUID_EXT_MMFR3 "c1, 7"
  40 #define CPUID_EXT_ISAR0 "c2, 0"
  41 #define CPUID_EXT_ISAR1 "c2, 1"
  42 #define CPUID_EXT_ISAR2 "c2, 2"
  43 #define CPUID_EXT_ISAR3 "c2, 3"
  44 #define CPUID_EXT_ISAR4 "c2, 4"
  45 #define CPUID_EXT_ISAR5 "c2, 5"
  46 #endif
  47
  48 #define MPIDR_SMP_BITMASK (0x3 << 30)
  49 #define MPIDR_SMP_VALUE (0x2 << 30)
  50
  51 #define MPIDR_MT_BITMASK (0x1 << 24)
  52
  53 #define MPIDR_HWID_BITMASK 0xFFFFFF
  54
  55 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  56
  57 #define MPIDR_LEVEL_BITS 8
  58 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  59 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
  60
  61 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  62         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  63
  64 #define ARM_CPU_IMP_ARM                 0x41
  65 #define ARM_CPU_IMP_DEC                 0x44
  66 #define ARM_CPU_IMP_INTEL               0x69
  67
  68 /* ARM implemented processors */
  69 #define ARM_CPU_PART_ARM1136            0x4100b360
  70 #define ARM_CPU_PART_ARM1156            0x4100b560
  71 #define ARM_CPU_PART_ARM1176            0x4100b760
  72 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  73 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  74 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  75 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  76 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  77 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  78 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  79 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  80 #define ARM_CPU_PART_MASK               0xff00fff0
  81
  82 /* DEC implemented cores */
  83 #define ARM_CPU_PART_SA1100             0x4400a110
  84
  85 /* Intel implemented cores */
  86 #define ARM_CPU_PART_SA1110             0x6900b110
  87 #define ARM_CPU_REV_SA1110_A0           0
  88 #define ARM_CPU_REV_SA1110_B0           4
  89 #define ARM_CPU_REV_SA1110_B1           5
  90 #define ARM_CPU_REV_SA1110_B2           6
  91 #define ARM_CPU_REV_SA1110_B4           8
  92
  93 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  94 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  95 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  96 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  97
  98 /* Qualcomm implemented cores */
  99 #define ARM_CPU_PART_SCORPION           0x510002d0
 100
 101 extern unsigned int processor_id;
 102
 103 #ifdef CONFIG_CPU_CP15
 104 #define read_cpuid(reg)                                                 \
 105         ({                                                              \
 106                 unsigned int __val;                                     \
 107                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
 108                     : "=r" (__val)                                      \
 109                     :                                                   \
 110                     : "cc");                                            \
 111                 __val;                                                  \
 112         })
 113
 114 /*
 115  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 116  * any is_smp() tests, which can cause undefined instruction aborts on
 117  * ARM1136 r0 due to the missing extended CP15 registers.
 118  */
 119 #define read_cpuid_ext(ext_reg)                                         \
 120         ({                                                              \
 121                 unsigned int __val;                                     \
 122                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 123                     : "=r" (__val)                                      \
 124                     :                                                   \
 125                     : "memory");                                        \
 126                 __val;                                                  \
 127         })
 128
 129 #elif defined(CONFIG_CPU_V7M)
 130
 131 #include <asm/io.h>
 132 #include <asm/v7m.h>
 133
 134 #define read_cpuid(reg)                                                 \
 135         ({                                                              \
 136                 WARN_ON_ONCE(1);                                        \
 137                 0;                                                      \
 138         })
 139
 140 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 141 {
 142         return readl(BASEADDR_V7M_SCB + offset);
 143 }
 144
 145 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 146
 147 /*
 148  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 149  * have cp15 so warn on other usages.
 150  */
 151 #define read_cpuid(reg)                                                 \
 152         ({                                                              \
 153                 WARN_ON_ONCE(1);                                        \
 154                 0;                                                      \
 155         })
 156
 157 #define read_cpuid_ext(reg) read_cpuid(reg)
 158
 159 #endif /* ifdef CONFIG_CPU_CP15 / else */
 160
 161 #ifdef CONFIG_CPU_CP15
 162 /*
 163  * The CPU ID never changes at run time, so we might as well tell the
 164  * compiler that it's constant.  Use this function to read the CPU ID
 165  * rather than directly reading processor_id or read_cpuid() directly.
 166  */
 167 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 168 {
 169         return read_cpuid(CPUID_ID);
 170 }
 171
 172 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 173 {
 174         return read_cpuid(CPUID_CACHETYPE);
 175 }
 176
 177 #elif defined(CONFIG_CPU_V7M)
 178
 179 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 180 {
 181         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 182 }
 183
 184 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 185 {
 186         return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
 187 }
 188
 189 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 190
 191 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 192 {
 193         return processor_id;
 194 }
 195
 196 #endif /* ifdef CONFIG_CPU_CP15 / else */
 197
 198 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 199 {
 200         return (read_cpuid_id() & 0xFF000000) >> 24;
 201 }
 202
 203 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
 204 {
 205         return read_cpuid_id() & 0x0000000f;
 206 }
 207
 208 /*
 209  * The CPU part number is meaningless without referring to the CPU
 210  * implementer: implementers are free to define their own part numbers
 211  * which are permitted to clash with other implementer part numbers.
 212  */
 213 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 214 {
 215         return read_cpuid_id() & ARM_CPU_PART_MASK;
 216 }
 217
 218 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 219 {
 220         return read_cpuid_id() & 0xFFF0;
 221 }
 222
 223 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 224 {
 225         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 226 }
 227
 228 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 229 {
 230         return read_cpuid(CPUID_TCM);
 231 }
 232
 233 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 234 {
 235         return read_cpuid(CPUID_MPIDR);
 236 }
 237
 238 /* StrongARM-11x0 CPUs */
 239 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
 240 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
 241
 242 /*
 243  * Intel's XScale3 core supports some v6 features (supersections, L2)
 244  * but advertises itself as v5 as it does not support the v6 ISA.  For
 245  * this reason, we need a way to explicitly test for this type of CPU.
 246  */
 247 #ifndef CONFIG_CPU_XSC3
 248 #define cpu_is_xsc3()   0
 249 #else
 250 static inline int cpu_is_xsc3(void)
 251 {
 252         unsigned int id;
 253         id = read_cpuid_id() & 0xffffe000;
 254         /* It covers both Intel ID and Marvell ID */
 255         if ((id == 0x69056000) || (id == 0x56056000))
 256                 return 1;
 257
 258         return 0;
 259 }
 260 #endif
 261
 262 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
 263     !defined(CONFIG_CPU_MOHAWK)
 264 #define cpu_is_xscale_family() 0
 265 #else
 266 static inline int cpu_is_xscale_family(void)
 267 {
 268         unsigned int id;
 269         id = read_cpuid_id() & 0xffffe000;
 270
 271         switch (id) {
 272         case 0x69052000: /* Intel XScale 1 */
 273         case 0x69054000: /* Intel XScale 2 */
 274         case 0x69056000: /* Intel XScale 3 */
 275         case 0x56056000: /* Marvell XScale 3 */
 276         case 0x56158000: /* Marvell Mohawk */
 277                 return 1;
 278         }
 279
 280         return 0;
 281 }
 282 #endif
 283
 284 /*
 285  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 286  * but require a specical sequence for enabling coprocessors.
 287  * For this reason, we need a way to distinguish them.
 288  */
 289 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 290 static inline int cpu_is_pj4(void)
 291 {
 292         unsigned int id;
 293
 294         id = read_cpuid_id();
 295         if ((id & 0xff0fff00) == 0x560f5800)
 296                 return 1;
 297
 298         return 0;
 299 }
 300 #else
 301 #define cpu_is_pj4()    0
 302 #endif
 303
 304 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 305                                                                   int field)
 306 {
 307         int feature = (features >> field) & 15;
 308
 309         /* feature registers are signed values */
 310         if (feature > 7)
 311                 feature -= 16;
 312
 313         return feature;
 314 }
 315
 316 #define cpuid_feature_extract(reg, field) \
 317         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 318
 319 #endif