arch/arm/include/asm/cputype.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_ARM_CPUTYPE_H
   3 #define __ASM_ARM_CPUTYPE_H
   4
   5 #include <linux/stringify.h>
   6 #include <linux/kernel.h>
   7
   8 #define CPUID_ID        0
   9 #define CPUID_CACHETYPE 1
  10 #define CPUID_TCM       2
  11 #define CPUID_TLBTYPE   3
  12 #define CPUID_MPUIR     4
  13 #define CPUID_MPIDR     5
  14 #define CPUID_REVIDR    6
  15
  16 #ifdef CONFIG_CPU_V7M
  17 #define CPUID_EXT_PFR0  0x40
  18 #define CPUID_EXT_PFR1  0x44
  19 #define CPUID_EXT_DFR0  0x48
  20 #define CPUID_EXT_AFR0  0x4c
  21 #define CPUID_EXT_MMFR0 0x50
  22 #define CPUID_EXT_MMFR1 0x54
  23 #define CPUID_EXT_MMFR2 0x58
  24 #define CPUID_EXT_MMFR3 0x5c
  25 #define CPUID_EXT_ISAR0 0x60
  26 #define CPUID_EXT_ISAR1 0x64
  27 #define CPUID_EXT_ISAR2 0x68
  28 #define CPUID_EXT_ISAR3 0x6c
  29 #define CPUID_EXT_ISAR4 0x70
  30 #define CPUID_EXT_ISAR5 0x74
  31 #else
  32 #define CPUID_EXT_PFR0  "c1, 0"
  33 #define CPUID_EXT_PFR1  "c1, 1"
  34 #define CPUID_EXT_DFR0  "c1, 2"
  35 #define CPUID_EXT_AFR0  "c1, 3"
  36 #define CPUID_EXT_MMFR0 "c1, 4"
  37 #define CPUID_EXT_MMFR1 "c1, 5"
  38 #define CPUID_EXT_MMFR2 "c1, 6"
  39 #define CPUID_EXT_MMFR3 "c1, 7"
  40 #define CPUID_EXT_ISAR0 "c2, 0"
  41 #define CPUID_EXT_ISAR1 "c2, 1"
  42 #define CPUID_EXT_ISAR2 "c2, 2"
  43 #define CPUID_EXT_ISAR3 "c2, 3"
  44 #define CPUID_EXT_ISAR4 "c2, 4"
  45 #define CPUID_EXT_ISAR5 "c2, 5"
  46 #endif
  47
  48 #define MPIDR_SMP_BITMASK (0x3 << 30)
  49 #define MPIDR_SMP_VALUE (0x2 << 30)
  50
  51 #define MPIDR_MT_BITMASK (0x1 << 24)
  52
  53 #define MPIDR_HWID_BITMASK 0xFFFFFF
  54
  55 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  56
  57 #define MPIDR_LEVEL_BITS 8
  58 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  59 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
  60
  61 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  62         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  63
  64 #define ARM_CPU_IMP_ARM                 0x41
  65 #define ARM_CPU_IMP_DEC                 0x44
  66 #define ARM_CPU_IMP_INTEL               0x69
  67
  68 /* ARM implemented processors */
  69 #define ARM_CPU_PART_ARM1136            0x4100b360
  70 #define ARM_CPU_PART_ARM1156            0x4100b560
  71 #define ARM_CPU_PART_ARM1176            0x4100b760
  72 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  73 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  74 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  75 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  76 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  77 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  78 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  79 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  80 #define ARM_CPU_PART_CORTEX_A53         0x4100d030
  81 #define ARM_CPU_PART_CORTEX_A57         0x4100d070
  82 #define ARM_CPU_PART_CORTEX_A72         0x4100d080
  83 #define ARM_CPU_PART_CORTEX_A73         0x4100d090
  84 #define ARM_CPU_PART_CORTEX_A75         0x4100d0a0
  85 #define ARM_CPU_PART_MASK               0xff00fff0
  86
  87 /* Broadcom cores */
  88 #define ARM_CPU_PART_BRAHMA_B15         0x420000f0
  89
  90 /* DEC implemented cores */
  91 #define ARM_CPU_PART_SA1100             0x4400a110
  92
  93 /* Intel implemented cores */
  94 #define ARM_CPU_PART_SA1110             0x6900b110
  95 #define ARM_CPU_REV_SA1110_A0           0
  96 #define ARM_CPU_REV_SA1110_B0           4
  97 #define ARM_CPU_REV_SA1110_B1           5
  98 #define ARM_CPU_REV_SA1110_B2           6
  99 #define ARM_CPU_REV_SA1110_B4           8
 100
 101 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
 102 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
 103 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
 104 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
 105
 106 /* Qualcomm implemented cores */
 107 #define ARM_CPU_PART_SCORPION           0x510002d0
 108
 109 extern unsigned int processor_id;
 110
 111 #ifdef CONFIG_CPU_CP15
 112 #define read_cpuid(reg)                                                 \
 113         ({                                                              \
 114                 unsigned int __val;                                     \
 115                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
 116                     : "=r" (__val)                                      \
 117                     :                                                   \
 118                     : "cc");                                            \
 119                 __val;                                                  \
 120         })
 121
 122 /*
 123  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 124  * any is_smp() tests, which can cause undefined instruction aborts on
 125  * ARM1136 r0 due to the missing extended CP15 registers.
 126  */
 127 #define read_cpuid_ext(ext_reg)                                         \
 128         ({                                                              \
 129                 unsigned int __val;                                     \
 130                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 131                     : "=r" (__val)                                      \
 132                     :                                                   \
 133                     : "memory");                                        \
 134                 __val;                                                  \
 135         })
 136
 137 #elif defined(CONFIG_CPU_V7M)
 138
 139 #include <asm/io.h>
 140 #include <asm/v7m.h>
 141
 142 #define read_cpuid(reg)                                                 \
 143         ({                                                              \
 144                 WARN_ON_ONCE(1);                                        \
 145                 0;                                                      \
 146         })
 147
 148 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 149 {
 150         return readl(BASEADDR_V7M_SCB + offset);
 151 }
 152
 153 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 154
 155 /*
 156  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 157  * have cp15 so warn on other usages.
 158  */
 159 #define read_cpuid(reg)                                                 \
 160         ({                                                              \
 161                 WARN_ON_ONCE(1);                                        \
 162                 0;                                                      \
 163         })
 164
 165 #define read_cpuid_ext(reg) read_cpuid(reg)
 166
 167 #endif /* ifdef CONFIG_CPU_CP15 / else */
 168
 169 #ifdef CONFIG_CPU_CP15
 170 /*
 171  * The CPU ID never changes at run time, so we might as well tell the
 172  * compiler that it's constant.  Use this function to read the CPU ID
 173  * rather than directly reading processor_id or read_cpuid() directly.
 174  */
 175 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 176 {
 177         return read_cpuid(CPUID_ID);
 178 }
 179
 180 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 181 {
 182         return read_cpuid(CPUID_CACHETYPE);
 183 }
 184
 185 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
 186 {
 187         return read_cpuid(CPUID_MPUIR);
 188 }
 189
 190 #elif defined(CONFIG_CPU_V7M)
 191
 192 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 193 {
 194         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 195 }
 196
 197 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 198 {
 199         return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
 200 }
 201
 202 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
 203 {
 204         return readl(BASEADDR_V7M_SCB + MPU_TYPE);
 205 }
 206
 207 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 208
 209 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 210 {
 211         return processor_id;
 212 }
 213
 214 #endif /* ifdef CONFIG_CPU_CP15 / else */
 215
 216 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 217 {
 218         return (read_cpuid_id() & 0xFF000000) >> 24;
 219 }
 220
 221 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
 222 {
 223         return read_cpuid_id() & 0x0000000f;
 224 }
 225
 226 /*
 227  * The CPU part number is meaningless without referring to the CPU
 228  * implementer: implementers are free to define their own part numbers
 229  * which are permitted to clash with other implementer part numbers.
 230  */
 231 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 232 {
 233         return read_cpuid_id() & ARM_CPU_PART_MASK;
 234 }
 235
 236 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 237 {
 238         return read_cpuid_id() & 0xFFF0;
 239 }
 240
 241 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 242 {
 243         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 244 }
 245
 246 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 247 {
 248         return read_cpuid(CPUID_TCM);
 249 }
 250
 251 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 252 {
 253         return read_cpuid(CPUID_MPIDR);
 254 }
 255
 256 /* StrongARM-11x0 CPUs */
 257 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
 258 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
 259
 260 /*
 261  * Intel's XScale3 core supports some v6 features (supersections, L2)
 262  * but advertises itself as v5 as it does not support the v6 ISA.  For
 263  * this reason, we need a way to explicitly test for this type of CPU.
 264  */
 265 #ifndef CONFIG_CPU_XSC3
 266 #define cpu_is_xsc3()   0
 267 #else
 268 static inline int cpu_is_xsc3(void)
 269 {
 270         unsigned int id;
 271         id = read_cpuid_id() & 0xffffe000;
 272         /* It covers both Intel ID and Marvell ID */
 273         if ((id == 0x69056000) || (id == 0x56056000))
 274                 return 1;
 275
 276         return 0;
 277 }
 278 #endif
 279
 280 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
 281     !defined(CONFIG_CPU_MOHAWK)
 282 #define cpu_is_xscale_family() 0
 283 #else
 284 static inline int cpu_is_xscale_family(void)
 285 {
 286         unsigned int id;
 287         id = read_cpuid_id() & 0xffffe000;
 288
 289         switch (id) {
 290         case 0x69052000: /* Intel XScale 1 */
 291         case 0x69054000: /* Intel XScale 2 */
 292         case 0x69056000: /* Intel XScale 3 */
 293         case 0x56056000: /* Marvell XScale 3 */
 294         case 0x56158000: /* Marvell Mohawk */
 295                 return 1;
 296         }
 297
 298         return 0;
 299 }
 300 #endif
 301
 302 /*
 303  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 304  * but require a specical sequence for enabling coprocessors.
 305  * For this reason, we need a way to distinguish them.
 306  */
 307 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 308 static inline int cpu_is_pj4(void)
 309 {
 310         unsigned int id;
 311
 312         id = read_cpuid_id();
 313         if ((id & 0xff0fff00) == 0x560f5800)
 314                 return 1;
 315
 316         return 0;
 317 }
 318 #else
 319 #define cpu_is_pj4()    0
 320 #endif
 321
 322 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 323                                                                   int field)
 324 {
 325         int feature = (features >> field) & 15;
 326
 327         /* feature registers are signed values */
 328         if (feature > 7)
 329                 feature -= 16;
 330
 331         return feature;
 332 }
 333
 334 #define cpuid_feature_extract(reg, field) \
 335         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 336
 337 #endif