arch/arm/boot/dts/zynq-7000.dtsi

   1 /*
   2  *  Copyright (C) 2011 - 2014 Xilinx
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         compatible = "xlnx,zynq-7000";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         compatible = "arm,cortex-a9";
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         clocks = <&clkc 3>;
  27                         clock-latency = <1000>;
  28                         cpu0-supply = <&regulator_vccpint>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 666667  1000000
  32                                 333334  1000000
  33                                 222223  1000000
  34                         >;
  35                 };
  36
  37                 cpu@1 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         reg = <1>;
  41                         clocks = <&clkc 3>;
  42                 };
  43         };
  44
  45         pmu {
  46                 compatible = "arm,cortex-a9-pmu";
  47                 interrupts = <0 5 4>, <0 6 4>;
  48                 interrupt-parent = <&intc>;
  49                 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
  50         };
  51
  52         regulator_vccpint: fixedregulator@0 {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "VCCPINT";
  55                 regulator-min-microvolt = <1000000>;
  56                 regulator-max-microvolt = <1000000>;
  57                 regulator-boot-on;
  58                 regulator-always-on;
  59         };
  60
  61         amba {
  62                 compatible = "simple-bus";
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 adc@f8007100 {
  69                         compatible = "xlnx,zynq-xadc-1.00.a";
  70                         reg = <0xf8007100 0x20>;
  71                         interrupts = <0 7 4>;
  72                         interrupt-parent = <&intc>;
  73                         clocks = <&clkc 12>;
  74                 };
  75
  76                 can0: can@e0008000 {
  77                         compatible = "xlnx,zynq-can-1.0";
  78                         status = "disabled";
  79                         clocks = <&clkc 19>, <&clkc 36>;
  80                         clock-names = "can_clk", "pclk";
  81                         reg = <0xe0008000 0x1000>;
  82                         interrupts = <0 28 4>;
  83                         interrupt-parent = <&intc>;
  84                         tx-fifo-depth = <0x40>;
  85                         rx-fifo-depth = <0x40>;
  86                 };
  87
  88                 can1: can@e0009000 {
  89                         compatible = "xlnx,zynq-can-1.0";
  90                         status = "disabled";
  91                         clocks = <&clkc 20>, <&clkc 37>;
  92                         clock-names = "can_clk", "pclk";
  93                         reg = <0xe0009000 0x1000>;
  94                         interrupts = <0 51 4>;
  95                         interrupt-parent = <&intc>;
  96                         tx-fifo-depth = <0x40>;
  97                         rx-fifo-depth = <0x40>;
  98                 };
  99
 100                 gpio0: gpio@e000a000 {
 101                         compatible = "xlnx,zynq-gpio-1.0";
 102                         #gpio-cells = <2>;
 103                         clocks = <&clkc 42>;
 104                         gpio-controller;
 105                         interrupt-parent = <&intc>;
 106                         interrupts = <0 20 4>;
 107                         reg = <0xe000a000 0x1000>;
 108                 };
 109
 110                 i2c0: i2c@e0004000 {
 111                         compatible = "cdns,i2c-r1p10";
 112                         status = "disabled";
 113                         clocks = <&clkc 38>;
 114                         interrupt-parent = <&intc>;
 115                         interrupts = <0 25 4>;
 116                         reg = <0xe0004000 0x1000>;
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                 };
 120
 121                 i2c1: i2c@e0005000 {
 122                         compatible = "cdns,i2c-r1p10";
 123                         status = "disabled";
 124                         clocks = <&clkc 39>;
 125                         interrupt-parent = <&intc>;
 126                         interrupts = <0 48 4>;
 127                         reg = <0xe0005000 0x1000>;
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                 };
 131
 132                 intc: interrupt-controller@f8f01000 {
 133                         compatible = "arm,cortex-a9-gic";
 134                         #interrupt-cells = <3>;
 135                         interrupt-controller;
 136                         reg = <0xF8F01000 0x1000>,
 137                               <0xF8F00100 0x100>;
 138                 };
 139
 140                 L2: cache-controller {
 141                         compatible = "arm,pl310-cache";
 142                         reg = <0xF8F02000 0x1000>;
 143                         arm,data-latency = <3 2 2>;
 144                         arm,tag-latency = <2 2 2>;
 145                         cache-unified;
 146                         cache-level = <2>;
 147                 };
 148
 149                 uart0: serial@e0000000 {
 150                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 151                         status = "disabled";
 152                         clocks = <&clkc 23>, <&clkc 40>;
 153                         clock-names = "uart_clk", "pclk";
 154                         reg = <0xE0000000 0x1000>;
 155                         interrupts = <0 27 4>;
 156                 };
 157
 158                 uart1: serial@e0001000 {
 159                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 160                         status = "disabled";
 161                         clocks = <&clkc 24>, <&clkc 41>;
 162                         clock-names = "uart_clk", "pclk";
 163                         reg = <0xE0001000 0x1000>;
 164                         interrupts = <0 50 4>;
 165                 };
 166
 167                 spi0: spi@e0006000 {
 168                         compatible = "xlnx,zynq-spi-r1p6";
 169                         reg = <0xe0006000 0x1000>;
 170                         status = "disabled";
 171                         interrupt-parent = <&intc>;
 172                         interrupts = <0 26 4>;
 173                         clocks = <&clkc 25>, <&clkc 34>;
 174                         clock-names = "ref_clk", "pclk";
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                 };
 178
 179                 spi1: spi@e0007000 {
 180                         compatible = "xlnx,zynq-spi-r1p6";
 181                         reg = <0xe0007000 0x1000>;
 182                         status = "disabled";
 183                         interrupt-parent = <&intc>;
 184                         interrupts = <0 49 4>;
 185                         clocks = <&clkc 26>, <&clkc 35>;
 186                         clock-names = "ref_clk", "pclk";
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                 };
 190
 191                 gem0: ethernet@e000b000 {
 192                         compatible = "cdns,gem";
 193                         reg = <0xe000b000 0x4000>;
 194                         status = "disabled";
 195                         interrupts = <0 22 4>;
 196                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 197                         clock-names = "pclk", "hclk", "tx_clk";
 198                 };
 199
 200                 gem1: ethernet@e000c000 {
 201                         compatible = "cdns,gem";
 202                         reg = <0xe000c000 0x4000>;
 203                         status = "disabled";
 204                         interrupts = <0 45 4>;
 205                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 206                         clock-names = "pclk", "hclk", "tx_clk";
 207                 };
 208
 209                 sdhci0: sdhci@e0100000 {
 210                         compatible = "arasan,sdhci-8.9a";
 211                         status = "disabled";
 212                         clock-names = "clk_xin", "clk_ahb";
 213                         clocks = <&clkc 21>, <&clkc 32>;
 214                         interrupt-parent = <&intc>;
 215                         interrupts = <0 24 4>;
 216                         reg = <0xe0100000 0x1000>;
 217                 } ;
 218
 219                 sdhci1: sdhci@e0101000 {
 220                         compatible = "arasan,sdhci-8.9a";
 221                         status = "disabled";
 222                         clock-names = "clk_xin", "clk_ahb";
 223                         clocks = <&clkc 22>, <&clkc 33>;
 224                         interrupt-parent = <&intc>;
 225                         interrupts = <0 47 4>;
 226                         reg = <0xe0101000 0x1000>;
 227                 } ;
 228
 229                 slcr: slcr@f8000000 {
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         compatible = "xlnx,zynq-slcr", "syscon";
 233                         reg = <0xF8000000 0x1000>;
 234                         ranges;
 235                         clkc: clkc@100 {
 236                                 #clock-cells = <1>;
 237                                 compatible = "xlnx,ps7-clkc";
 238                                 ps-clk-frequency = <33333333>;
 239                                 fclk-enable = <0>;
 240                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 241                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 242                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 243                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 244                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 245                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 246                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 247                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 248                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 249                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 250                                                 "dbg_trc", "dbg_apb";
 251                                 reg = <0x100 0x100>;
 252                         };
 253                 };
 254
 255                 dmac_s: dmac@f8003000 {
 256                         compatible = "arm,pl330", "arm,primecell";
 257                         reg = <0xf8003000 0x1000>;
 258                         interrupt-parent = <&intc>;
 259                         interrupts = <0 13 4>,
 260                                      <0 14 4>, <0 15 4>,
 261                                      <0 16 4>, <0 17 4>,
 262                                      <0 40 4>, <0 41 4>,
 263                                      <0 42 4>, <0 43 4>;
 264                         #dma-cells = <1>;
 265                         #dma-channels = <8>;
 266                         #dma-requests = <4>;
 267                         clocks = <&clkc 27>;
 268                         clock-names = "apb_pclk";
 269                 };
 270
 271                 devcfg: devcfg@f8007000 {
 272                         compatible = "xlnx,zynq-devcfg-1.0";
 273                         reg = <0xf8007000 0x100>;
 274                 } ;
 275
 276                 global_timer: timer@f8f00200 {
 277                         compatible = "arm,cortex-a9-global-timer";
 278                         reg = <0xf8f00200 0x20>;
 279                         interrupts = <1 11 0x301>;
 280                         interrupt-parent = <&intc>;
 281                         clocks = <&clkc 4>;
 282                 };
 283
 284                 ttc0: timer@f8001000 {
 285                         interrupt-parent = <&intc>;
 286                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 287                         compatible = "cdns,ttc";
 288                         clocks = <&clkc 6>;
 289                         reg = <0xF8001000 0x1000>;
 290                 };
 291
 292                 ttc1: timer@f8002000 {
 293                         interrupt-parent = <&intc>;
 294                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 295                         compatible = "cdns,ttc";
 296                         clocks = <&clkc 6>;
 297                         reg = <0xF8002000 0x1000>;
 298                 };
 299
 300                 scutimer: timer@f8f00600 {
 301                         interrupt-parent = <&intc>;
 302                         interrupts = <1 13 0x301>;
 303                         compatible = "arm,cortex-a9-twd-timer";
 304                         reg = <0xf8f00600 0x20>;
 305                         clocks = <&clkc 4>;
 306                 } ;
 307         };
 308 };