arch/arm/boot/dts/uniphier-pxs2.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier PXs2 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 / {
  12         compatible = "socionext,uniphier-pxs2";
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         reg = <0>;
  24                         clocks = <&sys_clk 32>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                         operating-points-v2 = <&cpu_opp>;
  28                         #cooling-cells = <2>;
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clocks = <&sys_clk 32>;
  36                         enable-method = "psci";
  37                         next-level-cache = <&l2>;
  38                         operating-points-v2 = <&cpu_opp>;
  39                 };
  40
  41                 cpu2: cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <2>;
  45                         clocks = <&sys_clk 32>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                         operating-points-v2 = <&cpu_opp>;
  49                 };
  50
  51                 cpu3: cpu@3 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         reg = <3>;
  55                         clocks = <&sys_clk 32>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&l2>;
  58                         operating-points-v2 = <&cpu_opp>;
  59                 };
  60         };
  61
  62         cpu_opp: opp-table {
  63                 compatible = "operating-points-v2";
  64                 opp-shared;
  65
  66                 opp-100000000 {
  67                         opp-hz = /bits/ 64 <100000000>;
  68                         clock-latency-ns = <300>;
  69                 };
  70                 opp-150000000 {
  71                         opp-hz = /bits/ 64 <150000000>;
  72                         clock-latency-ns = <300>;
  73                 };
  74                 opp-200000000 {
  75                         opp-hz = /bits/ 64 <200000000>;
  76                         clock-latency-ns = <300>;
  77                 };
  78                 opp-300000000 {
  79                         opp-hz = /bits/ 64 <300000000>;
  80                         clock-latency-ns = <300>;
  81                 };
  82                 opp-400000000 {
  83                         opp-hz = /bits/ 64 <400000000>;
  84                         clock-latency-ns = <300>;
  85                 };
  86                 opp-600000000 {
  87                         opp-hz = /bits/ 64 <600000000>;
  88                         clock-latency-ns = <300>;
  89                 };
  90                 opp-800000000 {
  91                         opp-hz = /bits/ 64 <800000000>;
  92                         clock-latency-ns = <300>;
  93                 };
  94                 opp-1200000000 {
  95                         opp-hz = /bits/ 64 <1200000000>;
  96                         clock-latency-ns = <300>;
  97                 };
  98         };
  99
 100         psci {
 101                 compatible = "arm,psci-0.2";
 102                 method = "smc";
 103         };
 104
 105         clocks {
 106                 refclk: ref {
 107                         compatible = "fixed-clock";
 108                         #clock-cells = <0>;
 109                         clock-frequency = <25000000>;
 110                 };
 111
 112                 arm_timer_clk: arm-timer {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-clock";
 115                         clock-frequency = <50000000>;
 116                 };
 117         };
 118
 119         thermal-zones {
 120                 cpu-thermal {
 121                         polling-delay-passive = <250>;  /* 250ms */
 122                         polling-delay = <1000>;         /* 1000ms */
 123                         thermal-sensors = <&pvtctl>;
 124
 125                         trips {
 126                                 cpu_crit: cpu-crit {
 127                                         temperature = <95000>;  /* 95C */
 128                                         hysteresis = <2000>;
 129                                         type = "critical";
 130                                 };
 131                                 cpu_alert: cpu-alert {
 132                                         temperature = <85000>;  /* 85C */
 133                                         hysteresis = <2000>;
 134                                         type = "passive";
 135                                 };
 136                         };
 137
 138                         cooling-maps {
 139                                 map {
 140                                         trip = <&cpu_alert>;
 141                                         cooling-device = <&cpu0
 142                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 143                                 };
 144                         };
 145                 };
 146         };
 147
 148         soc {
 149                 compatible = "simple-bus";
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges;
 153                 interrupt-parent = <&intc>;
 154
 155                 l2: l2-cache@500c0000 {
 156                         compatible = "socionext,uniphier-system-cache";
 157                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 158                               <0x506c0000 0x400>;
 159                         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 160                         cache-unified;
 161                         cache-size = <(1280 * 1024)>;
 162                         cache-sets = <512>;
 163                         cache-line-size = <128>;
 164                         cache-level = <2>;
 165                 };
 166
 167                 serial0: serial@54006800 {
 168                         compatible = "socionext,uniphier-uart";
 169                         status = "disabled";
 170                         reg = <0x54006800 0x40>;
 171                         interrupts = <0 33 4>;
 172                         pinctrl-names = "default";
 173                         pinctrl-0 = <&pinctrl_uart0>;
 174                         clocks = <&peri_clk 0>;
 175                         resets = <&peri_rst 0>;
 176                 };
 177
 178                 serial1: serial@54006900 {
 179                         compatible = "socionext,uniphier-uart";
 180                         status = "disabled";
 181                         reg = <0x54006900 0x40>;
 182                         interrupts = <0 35 4>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_uart1>;
 185                         clocks = <&peri_clk 1>;
 186                         resets = <&peri_rst 1>;
 187                 };
 188
 189                 serial2: serial@54006a00 {
 190                         compatible = "socionext,uniphier-uart";
 191                         status = "disabled";
 192                         reg = <0x54006a00 0x40>;
 193                         interrupts = <0 37 4>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_uart2>;
 196                         clocks = <&peri_clk 2>;
 197                         resets = <&peri_rst 2>;
 198                 };
 199
 200                 serial3: serial@54006b00 {
 201                         compatible = "socionext,uniphier-uart";
 202                         status = "disabled";
 203                         reg = <0x54006b00 0x40>;
 204                         interrupts = <0 177 4>;
 205                         pinctrl-names = "default";
 206                         pinctrl-0 = <&pinctrl_uart3>;
 207                         clocks = <&peri_clk 3>;
 208                         resets = <&peri_rst 3>;
 209                 };
 210
 211                 gpio: gpio@55000000 {
 212                         compatible = "socionext,uniphier-gpio";
 213                         reg = <0x55000000 0x200>;
 214                         interrupt-parent = <&aidet>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                         gpio-controller;
 218                         #gpio-cells = <2>;
 219                         gpio-ranges = <&pinctrl 0 0 0>,
 220                                       <&pinctrl 96 0 0>;
 221                         gpio-ranges-group-names = "gpio_range0",
 222                                                   "gpio_range1";
 223                         ngpios = <232>;
 224                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 225                                                      <21 217 3>;
 226                 };
 227
 228                 audio@56000000 {
 229                         compatible = "socionext,uniphier-pxs2-aio";
 230                         reg = <0x56000000 0x80000>;
 231                         interrupts = <0 144 4>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&pinctrl_ain1>,
 234                                     <&pinctrl_ain2>,
 235                                     <&pinctrl_ainiec1>,
 236                                     <&pinctrl_aout2>,
 237                                     <&pinctrl_aout3>,
 238                                     <&pinctrl_aoutiec1>,
 239                                     <&pinctrl_aoutiec2>;
 240                         clock-names = "aio";
 241                         clocks = <&sys_clk 40>;
 242                         reset-names = "aio";
 243                         resets = <&sys_rst 40>;
 244                         #sound-dai-cells = <1>;
 245                         socionext,syscon = <&soc_glue>;
 246
 247                         i2s_port0: port@0 {
 248                                 i2s_hdmi: endpoint {
 249                                 };
 250                         };
 251
 252                         i2s_port1: port@1 {
 253                                 i2s_line: endpoint {
 254                                 };
 255                         };
 256
 257                         i2s_port2: port@2 {
 258                                 i2s_aux: endpoint {
 259                                 };
 260                         };
 261
 262                         spdif_port0: port@3 {
 263                                 spdif_hiecout1: endpoint {
 264                                 };
 265                         };
 266
 267                         spdif_port1: port@4 {
 268                                 spdif_iecout1: endpoint {
 269                                 };
 270                         };
 271
 272                         comp_spdif_port0: port@5 {
 273                                 comp_spdif_hiecout1: endpoint {
 274                                 };
 275                         };
 276
 277                         comp_spdif_port1: port@6 {
 278                                 comp_spdif_iecout1: endpoint {
 279                                 };
 280                         };
 281                 };
 282
 283                 i2c0: i2c@58780000 {
 284                         compatible = "socionext,uniphier-fi2c";
 285                         status = "disabled";
 286                         reg = <0x58780000 0x80>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         interrupts = <0 41 4>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&pinctrl_i2c0>;
 292                         clocks = <&peri_clk 4>;
 293                         resets = <&peri_rst 4>;
 294                         clock-frequency = <100000>;
 295                 };
 296
 297                 i2c1: i2c@58781000 {
 298                         compatible = "socionext,uniphier-fi2c";
 299                         status = "disabled";
 300                         reg = <0x58781000 0x80>;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         interrupts = <0 42 4>;
 304                         pinctrl-names = "default";
 305                         pinctrl-0 = <&pinctrl_i2c1>;
 306                         clocks = <&peri_clk 5>;
 307                         resets = <&peri_rst 5>;
 308                         clock-frequency = <100000>;
 309                 };
 310
 311                 i2c2: i2c@58782000 {
 312                         compatible = "socionext,uniphier-fi2c";
 313                         status = "disabled";
 314                         reg = <0x58782000 0x80>;
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         interrupts = <0 43 4>;
 318                         pinctrl-names = "default";
 319                         pinctrl-0 = <&pinctrl_i2c2>;
 320                         clocks = <&peri_clk 6>;
 321                         resets = <&peri_rst 6>;
 322                         clock-frequency = <100000>;
 323                 };
 324
 325                 i2c3: i2c@58783000 {
 326                         compatible = "socionext,uniphier-fi2c";
 327                         status = "disabled";
 328                         reg = <0x58783000 0x80>;
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         interrupts = <0 44 4>;
 332                         pinctrl-names = "default";
 333                         pinctrl-0 = <&pinctrl_i2c3>;
 334                         clocks = <&peri_clk 7>;
 335                         resets = <&peri_rst 7>;
 336                         clock-frequency = <100000>;
 337                 };
 338
 339                 /* chip-internal connection for DMD */
 340                 i2c4: i2c@58784000 {
 341                         compatible = "socionext,uniphier-fi2c";
 342                         reg = <0x58784000 0x80>;
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         interrupts = <0 45 4>;
 346                         clocks = <&peri_clk 8>;
 347                         resets = <&peri_rst 8>;
 348                         clock-frequency = <400000>;
 349                 };
 350
 351                 /* chip-internal connection for STM */
 352                 i2c5: i2c@58785000 {
 353                         compatible = "socionext,uniphier-fi2c";
 354                         reg = <0x58785000 0x80>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         interrupts = <0 25 4>;
 358                         clocks = <&peri_clk 9>;
 359                         resets = <&peri_rst 9>;
 360                         clock-frequency = <400000>;
 361                 };
 362
 363                 /* chip-internal connection for HDMI */
 364                 i2c6: i2c@58786000 {
 365                         compatible = "socionext,uniphier-fi2c";
 366                         reg = <0x58786000 0x80>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         interrupts = <0 26 4>;
 370                         clocks = <&peri_clk 10>;
 371                         resets = <&peri_rst 10>;
 372                         clock-frequency = <400000>;
 373                 };
 374
 375                 system_bus: system-bus@58c00000 {
 376                         compatible = "socionext,uniphier-system-bus";
 377                         status = "disabled";
 378                         reg = <0x58c00000 0x400>;
 379                         #address-cells = <2>;
 380                         #size-cells = <1>;
 381                         pinctrl-names = "default";
 382                         pinctrl-0 = <&pinctrl_system_bus>;
 383                 };
 384
 385                 smpctrl@59801000 {
 386                         compatible = "socionext,uniphier-smpctrl";
 387                         reg = <0x59801000 0x400>;
 388                 };
 389
 390                 sdctrl@59810000 {
 391                         compatible = "socionext,uniphier-pxs2-sdctrl",
 392                                      "simple-mfd", "syscon";
 393                         reg = <0x59810000 0x400>;
 394
 395                         sd_clk: clock {
 396                                 compatible = "socionext,uniphier-pxs2-sd-clock";
 397                                 #clock-cells = <1>;
 398                         };
 399
 400                         sd_rst: reset {
 401                                 compatible = "socionext,uniphier-pxs2-sd-reset";
 402                                 #reset-cells = <1>;
 403                         };
 404                 };
 405
 406                 perictrl@59820000 {
 407                         compatible = "socionext,uniphier-pxs2-perictrl",
 408                                      "simple-mfd", "syscon";
 409                         reg = <0x59820000 0x200>;
 410
 411                         peri_clk: clock {
 412                                 compatible = "socionext,uniphier-pxs2-peri-clock";
 413                                 #clock-cells = <1>;
 414                         };
 415
 416                         peri_rst: reset {
 417                                 compatible = "socionext,uniphier-pxs2-peri-reset";
 418                                 #reset-cells = <1>;
 419                         };
 420                 };
 421
 422                 soc_glue: soc-glue@5f800000 {
 423                         compatible = "socionext,uniphier-pxs2-soc-glue",
 424                                      "simple-mfd", "syscon";
 425                         reg = <0x5f800000 0x2000>;
 426
 427                         pinctrl: pinctrl {
 428                                 compatible = "socionext,uniphier-pxs2-pinctrl";
 429                         };
 430                 };
 431
 432                 soc-glue@5f900000 {
 433                         compatible = "socionext,uniphier-pxs2-soc-glue-debug",
 434                                      "simple-mfd";
 435                         #address-cells = <1>;
 436                         #size-cells = <1>;
 437                         ranges = <0 0x5f900000 0x2000>;
 438
 439                         efuse@100 {
 440                                 compatible = "socionext,uniphier-efuse";
 441                                 reg = <0x100 0x28>;
 442                         };
 443
 444                         efuse@200 {
 445                                 compatible = "socionext,uniphier-efuse";
 446                                 reg = <0x200 0x58>;
 447                         };
 448                 };
 449
 450                 aidet: aidet@5fc20000 {
 451                         compatible = "socionext,uniphier-pxs2-aidet";
 452                         reg = <0x5fc20000 0x200>;
 453                         interrupt-controller;
 454                         #interrupt-cells = <2>;
 455                 };
 456
 457                 timer@60000200 {
 458                         compatible = "arm,cortex-a9-global-timer";
 459                         reg = <0x60000200 0x20>;
 460                         interrupts = <1 11 0xf04>;
 461                         clocks = <&arm_timer_clk>;
 462                 };
 463
 464                 timer@60000600 {
 465                         compatible = "arm,cortex-a9-twd-timer";
 466                         reg = <0x60000600 0x20>;
 467                         interrupts = <1 13 0xf04>;
 468                         clocks = <&arm_timer_clk>;
 469                 };
 470
 471                 intc: interrupt-controller@60001000 {
 472                         compatible = "arm,cortex-a9-gic";
 473                         reg = <0x60001000 0x1000>,
 474                               <0x60000100 0x100>;
 475                         #interrupt-cells = <3>;
 476                         interrupt-controller;
 477                 };
 478
 479                 sysctrl@61840000 {
 480                         compatible = "socionext,uniphier-pxs2-sysctrl",
 481                                      "simple-mfd", "syscon";
 482                         reg = <0x61840000 0x10000>;
 483
 484                         sys_clk: clock {
 485                                 compatible = "socionext,uniphier-pxs2-clock";
 486                                 #clock-cells = <1>;
 487                         };
 488
 489                         sys_rst: reset {
 490                                 compatible = "socionext,uniphier-pxs2-reset";
 491                                 #reset-cells = <1>;
 492                         };
 493
 494                         pvtctl: pvtctl {
 495                                 compatible = "socionext,uniphier-pxs2-thermal";
 496                                 interrupts = <0 3 4>;
 497                                 #thermal-sensor-cells = <0>;
 498                                 socionext,tmod-calibration = <0x0f86 0x6844>;
 499                         };
 500                 };
 501
 502                 eth: ethernet@65000000 {
 503                         compatible = "socionext,uniphier-pxs2-ave4";
 504                         status = "disabled";
 505                         reg = <0x65000000 0x8500>;
 506                         interrupts = <0 66 4>;
 507                         pinctrl-names = "default";
 508                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 509                         clock-names = "ether";
 510                         clocks = <&sys_clk 6>;
 511                         reset-names = "ether";
 512                         resets = <&sys_rst 6>;
 513                         phy-mode = "rgmii";
 514                         local-mac-address = [00 00 00 00 00 00];
 515                         socionext,syscon-phy-mode = <&soc_glue 0>;
 516
 517                         mdio: mdio {
 518                                 #address-cells = <1>;
 519                                 #size-cells = <0>;
 520                         };
 521                 };
 522
 523                 nand: nand@68000000 {
 524                         compatible = "socionext,uniphier-denali-nand-v5b";
 525                         status = "disabled";
 526                         reg-names = "nand_data", "denali_reg";
 527                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 528                         interrupts = <0 65 4>;
 529                         pinctrl-names = "default";
 530                         pinctrl-0 = <&pinctrl_nand2cs>;
 531                         clocks = <&sys_clk 2>;
 532                         resets = <&sys_rst 2>;
 533                 };
 534         };
 535 };
 536
 537 #include "uniphier-pinctrl.dtsi"