arch/arm/boot/dts/tegra30-apalis.dtsi

   1 #include "tegra30.dtsi"
   2
   3 /*
   4  * Toradex Apalis T30 Module Device Tree
   5  * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
   6  * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
   7  */
   8 / {
   9         model = "Toradex Apalis T30";
  10         compatible = "toradex,apalis_t30", "nvidia,tegra30";
  11
  12         pcie@3000 {
  13                 avdd-pexa-supply = <&vdd2_reg>;
  14                 vdd-pexa-supply = <&vdd2_reg>;
  15                 avdd-pexb-supply = <&vdd2_reg>;
  16                 vdd-pexb-supply = <&vdd2_reg>;
  17                 avdd-pex-pll-supply = <&vdd2_reg>;
  18                 avdd-plle-supply = <&ldo6_reg>;
  19                 vddio-pex-ctl-supply = <&sys_3v3_reg>;
  20                 hvdd-pex-supply = <&sys_3v3_reg>;
  21
  22                 pci@1,0 {
  23                         nvidia,num-lanes = <4>;
  24                 };
  25
  26                 pci@2,0 {
  27                         nvidia,num-lanes = <1>;
  28                 };
  29
  30                 pci@3,0 {
  31                         nvidia,num-lanes = <1>;
  32                 };
  33         };
  34
  35         host1x@50000000 {
  36                 hdmi@54280000 {
  37                         vdd-supply = <&avdd_hdmi_3v3_reg>;
  38                         pll-supply = <&avdd_hdmi_pll_1v8_reg>;
  39
  40                         nvidia,hpd-gpio =
  41                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  42                         nvidia,ddc-i2c-bus = <&hdmiddc>;
  43                 };
  44         };
  45
  46         pinmux@70000868 {
  47                 pinctrl-names = "default";
  48                 pinctrl-0 = <&state_default>;
  49
  50                 state_default: pinmux {
  51                         /* Analogue Audio (On-module) */
  52                         clk1_out_pw4 {
  53                                 nvidia,pins = "clk1_out_pw4";
  54                                 nvidia,function = "extperiph1";
  55                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  56                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  57                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  58                         };
  59                         dap3_fs_pp0 {
  60                                 nvidia,pins =   "dap3_fs_pp0",
  61                                                 "dap3_sclk_pp3",
  62                                                 "dap3_din_pp1",
  63                                                 "dap3_dout_pp2";
  64                                 nvidia,function = "i2s2";
  65                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  66                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  67                         };
  68
  69                         /* Apalis BKL1_ON */
  70                         pv2 {
  71                                 nvidia,pins = "pv2";
  72                                 nvidia,function = "rsvd4";
  73                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  75                         };
  76
  77                         /* Apalis BKL1_PWM */
  78                         uart3_rts_n_pc0 {
  79                                 nvidia,pins = "uart3_rts_n_pc0";
  80                                 nvidia,function = "pwm0";
  81                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  82                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  83                         };
  84                         /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
  85                         uart3_cts_n_pa1 {
  86                                 nvidia,pins = "uart3_cts_n_pa1";
  87                                 nvidia,function = "rsvd2";
  88                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  89                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  90                         };
  91
  92                         /* Apalis CAN1 on SPI6 */
  93                         spi2_cs0_n_px3 {
  94                                 nvidia,pins = "spi2_cs0_n_px3",
  95                                               "spi2_miso_px1",
  96                                               "spi2_mosi_px0",
  97                                               "spi2_sck_px2";
  98                                 nvidia,function = "spi6";
  99                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 100                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 101                         };
 102                         /* CAN_INT1 */
 103                         spi2_cs1_n_pw2 {
 104                                 nvidia,pins = "spi2_cs1_n_pw2";
 105                                 nvidia,function = "spi3";
 106                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 107                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 108                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 109                         };
 110
 111                         /* Apalis CAN2 on SPI4 */
 112                         gmi_a16_pj7 {
 113                                 nvidia,pins = "gmi_a16_pj7",
 114                                               "gmi_a17_pb0",
 115                                               "gmi_a18_pb1",
 116                                               "gmi_a19_pk7";
 117                                 nvidia,function = "spi4";
 118                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 119                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 120                         };
 121                         /* CAN_INT2 */
 122                         spi2_cs2_n_pw3 {
 123                                 nvidia,pins = "spi2_cs2_n_pw3";
 124                                 nvidia,function = "spi3";
 125                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 126                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 127                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 128                         };
 129
 130                         /* Apalis Digital Audio */
 131                         clk1_req_pee2 {
 132                                 nvidia,pins = "clk1_req_pee2";
 133                                 nvidia,function = "hda";
 134                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 135                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 136                         };
 137                         clk2_out_pw5 {
 138                                 nvidia,pins = "clk2_out_pw5";
 139                                 nvidia,function = "extperiph2";
 140                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 141                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 142                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 143                         };
 144                         dap1_fs_pn0 {
 145                                 nvidia,pins = "dap1_fs_pn0",
 146                                               "dap1_din_pn1",
 147                                               "dap1_dout_pn2",
 148                                               "dap1_sclk_pn3";
 149                                 nvidia,function = "hda";
 150                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 151                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 152                         };
 153
 154                         /* Apalis I2C3 */
 155                         cam_i2c_scl_pbb1 {
 156                                 nvidia,pins = "cam_i2c_scl_pbb1",
 157                                               "cam_i2c_sda_pbb2";
 158                                 nvidia,function = "i2c3";
 159                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 160                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 161                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 162                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 163                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 164                         };
 165
 166                         /* Apalis MMC1 */
 167                         sdmmc3_clk_pa6 {
 168                                 nvidia,pins = "sdmmc3_clk_pa6",
 169                                               "sdmmc3_cmd_pa7";
 170                                 nvidia,function = "sdmmc3";
 171                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 172                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 173                         };
 174                         sdmmc3_dat0_pb7 {
 175                                 nvidia,pins = "sdmmc3_dat0_pb7",
 176                                               "sdmmc3_dat1_pb6",
 177                                               "sdmmc3_dat2_pb5",
 178                                               "sdmmc3_dat3_pb4",
 179                                               "sdmmc3_dat4_pd1",
 180                                               "sdmmc3_dat5_pd0",
 181                                               "sdmmc3_dat6_pd3",
 182                                               "sdmmc3_dat7_pd4";
 183                                 nvidia,function = "sdmmc3";
 184                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 185                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 186                         };
 187                         /* Apalis MMC1_CD# */
 188                         pv3 {
 189                                 nvidia,pins = "pv3";
 190                                 nvidia,function = "rsvd2";
 191                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 192                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 193                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 194                         };
 195
 196                         /* Apalis PWM1 */
 197                         pu6 {
 198                                 nvidia,pins = "pu6";
 199                                 nvidia,function = "pwm3";
 200                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 201                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 202                         };
 203
 204                         /* Apalis PWM2 */
 205                         pu5 {
 206                                 nvidia,pins = "pu5";
 207                                 nvidia,function = "pwm2";
 208                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 209                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 210                         };
 211
 212                         /* Apalis PWM3 */
 213                         pu4 {
 214                                 nvidia,pins = "pu4";
 215                                 nvidia,function = "pwm1";
 216                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 217                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 218                         };
 219
 220                         /* Apalis PWM4 */
 221                         pu3 {
 222                                 nvidia,pins = "pu3";
 223                                 nvidia,function = "pwm0";
 224                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 225                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 226                         };
 227
 228                         /* Apalis RESET_MOCI# */
 229                         gmi_rst_n_pi4 {
 230                                 nvidia,pins = "gmi_rst_n_pi4";
 231                                 nvidia,function = "gmi";
 232                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 233                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 234                         };
 235
 236                         /* Apalis SD1 */
 237                         sdmmc1_clk_pz0 {
 238                                 nvidia,pins = "sdmmc1_clk_pz0";
 239                                 nvidia,function = "sdmmc1";
 240                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 241                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 242                         };
 243                         sdmmc1_cmd_pz1 {
 244                                 nvidia,pins = "sdmmc1_cmd_pz1",
 245                                               "sdmmc1_dat0_py7",
 246                                               "sdmmc1_dat1_py6",
 247                                               "sdmmc1_dat2_py5",
 248                                               "sdmmc1_dat3_py4";
 249                                 nvidia,function = "sdmmc1";
 250                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 251                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 252                         };
 253                         /* Apalis SD1_CD# */
 254                         clk2_req_pcc5 {
 255                                 nvidia,pins = "clk2_req_pcc5";
 256                                 nvidia,function = "rsvd2";
 257                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 258                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 259                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 260                         };
 261
 262                         /* Apalis SPI1 */
 263                         spi1_sck_px5 {
 264                                 nvidia,pins = "spi1_sck_px5",
 265                                               "spi1_mosi_px4",
 266                                               "spi1_miso_px7",
 267                                               "spi1_cs0_n_px6";
 268                                 nvidia,function = "spi1";
 269                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 270                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 271                         };
 272
 273                         /* Apalis SPI2 */
 274                         lcd_sck_pz4 {
 275                                 nvidia,pins = "lcd_sck_pz4",
 276                                               "lcd_sdout_pn5",
 277                                               "lcd_sdin_pz2",
 278                                               "lcd_cs0_n_pn4";
 279                                 nvidia,function = "spi5";
 280                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 281                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 282                         };
 283
 284                         /* Apalis UART1 */
 285                         ulpi_data0 {
 286                                 nvidia,pins = "ulpi_data0_po1",
 287                                               "ulpi_data1_po2",
 288                                               "ulpi_data2_po3",
 289                                               "ulpi_data3_po4",
 290                                               "ulpi_data4_po5",
 291                                               "ulpi_data5_po6",
 292                                               "ulpi_data6_po7",
 293                                               "ulpi_data7_po0";
 294                                 nvidia,function = "uarta";
 295                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 296                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 297                         };
 298
 299                         /* Apalis UART2 */
 300                         ulpi_clk_py0 {
 301                                 nvidia,pins = "ulpi_clk_py0",
 302                                               "ulpi_dir_py1",
 303                                               "ulpi_nxt_py2",
 304                                               "ulpi_stp_py3";
 305                                 nvidia,function = "uartd";
 306                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 307                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 308                         };
 309
 310                         /* Apalis UART3 */
 311                         uart2_rxd_pc3 {
 312                                 nvidia,pins = "uart2_rxd_pc3",
 313                                               "uart2_txd_pc2";
 314                                 nvidia,function = "uartb";
 315                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 316                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 317                         };
 318
 319                         /* Apalis UART4 */
 320                         uart3_rxd_pw7 {
 321                                 nvidia,pins = "uart3_rxd_pw7",
 322                                               "uart3_txd_pw6";
 323                                 nvidia,function = "uartc";
 324                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 325                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 326                         };
 327
 328                         /* Apalis USBO1_EN */
 329                         gen2_i2c_scl_pt5 {
 330                                 nvidia,pins = "gen2_i2c_scl_pt5";
 331                                 nvidia,function = "rsvd4";
 332                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 333                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 334                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 335                         };
 336
 337                         /* Apalis USBO1_OC# */
 338                         gen2_i2c_sda_pt6 {
 339                                 nvidia,pins = "gen2_i2c_sda_pt6";
 340                                 nvidia,function = "rsvd4";
 341                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 342                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 343                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 344                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 345                         };
 346
 347                         /* Apalis WAKE1_MICO */
 348                         pv1 {
 349                                 nvidia,pins = "pv1";
 350                                 nvidia,function = "rsvd1";
 351                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 352                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 353                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 354                         };
 355
 356                         /* eMMC (On-module) */
 357                         sdmmc4_clk_pcc4 {
 358                                 nvidia,pins = "sdmmc4_clk_pcc4",
 359                                               "sdmmc4_rst_n_pcc3";
 360                                 nvidia,function = "sdmmc4";
 361                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 362                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 363                         };
 364                         sdmmc4_dat0_paa0 {
 365                                 nvidia,pins = "sdmmc4_dat0_paa0",
 366                                               "sdmmc4_dat1_paa1",
 367                                               "sdmmc4_dat2_paa2",
 368                                               "sdmmc4_dat3_paa3",
 369                                               "sdmmc4_dat4_paa4",
 370                                               "sdmmc4_dat5_paa5",
 371                                               "sdmmc4_dat6_paa6",
 372                                               "sdmmc4_dat7_paa7";
 373                                 nvidia,function = "sdmmc4";
 374                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 375                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 376                         };
 377
 378                         /* LVDS Transceiver Configuration */
 379                         pbb0 {
 380                                 nvidia,pins = "pbb0",
 381                                               "pbb7",
 382                                               "pcc1",
 383                                               "pcc2";
 384                                 nvidia,function = "rsvd2";
 385                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 386                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 387                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 388                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 389                         };
 390                         pbb3 {
 391                                 nvidia,pins = "pbb3",
 392                                               "pbb4",
 393                                               "pbb5",
 394                                               "pbb6";
 395                                 nvidia,function = "displayb";
 396                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 397                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 398                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 399                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 400                         };
 401
 402                         /* Power I2C (On-module) */
 403                         pwr_i2c_scl_pz6 {
 404                                 nvidia,pins = "pwr_i2c_scl_pz6",
 405                                               "pwr_i2c_sda_pz7";
 406                                 nvidia,function = "i2cpwr";
 407                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 408                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 409                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 410                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 411                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 412                         };
 413
 414                         /*
 415                          * THERMD_ALERT#, unlatched I2C address pin of LM95245
 416                          * temperature sensor therefore requires disabling for
 417                          * now
 418                          */
 419                         lcd_dc1_pd2 {
 420                                 nvidia,pins = "lcd_dc1_pd2";
 421                                 nvidia,function = "rsvd3";
 422                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 423                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 424                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 425                         };
 426
 427                         /* TOUCH_PEN_INT# */
 428                         pv0 {
 429                                 nvidia,pins = "pv0";
 430                                 nvidia,function = "rsvd1";
 431                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 432                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 433                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 434                         };
 435                 };
 436         };
 437
 438         hdmiddc: i2c@7000c700 {
 439                 clock-frequency = <100000>;
 440         };
 441
 442         /*
 443          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 444          * touch screen controller
 445          */
 446         i2c@7000d000 {
 447                 status = "okay";
 448                 clock-frequency = <100000>;
 449
 450                 /* SGTL5000 audio codec */
 451                 sgtl5000: codec@a {
 452                         compatible = "fsl,sgtl5000";
 453                         reg = <0x0a>;
 454                         VDDA-supply = <&sys_3v3_reg>;
 455                         VDDIO-supply = <&sys_3v3_reg>;
 456                         clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
 457                 };
 458
 459                 pmic: tps65911@2d {
 460                         compatible = "ti,tps65911";
 461                         reg = <0x2d>;
 462
 463                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 464                         #interrupt-cells = <2>;
 465                         interrupt-controller;
 466
 467                         ti,system-power-controller;
 468
 469                         #gpio-cells = <2>;
 470                         gpio-controller;
 471
 472                         vcc1-supply = <&sys_3v3_reg>;
 473                         vcc2-supply = <&sys_3v3_reg>;
 474                         vcc3-supply = <&vio_reg>;
 475                         vcc4-supply = <&sys_3v3_reg>;
 476                         vcc5-supply = <&sys_3v3_reg>;
 477                         vcc6-supply = <&vio_reg>;
 478                         vcc7-supply = <&charge_pump_5v0_reg>;
 479                         vccio-supply = <&sys_3v3_reg>;
 480
 481                         regulators {
 482                                 /* SW1: +V1.35_VDDIO_DDR */
 483                                 vdd1_reg: vdd1 {
 484                                         regulator-name = "vddio_ddr_1v35";
 485                                         regulator-min-microvolt = <1350000>;
 486                                         regulator-max-microvolt = <1350000>;
 487                                         regulator-always-on;
 488                                 };
 489
 490                                 /* SW2: +V1.05 */
 491                                 vdd2_reg: vdd2 {
 492                                         regulator-name =
 493                                                 "vdd_pexa,vdd_pexb,vdd_sata";
 494                                         regulator-min-microvolt = <1050000>;
 495                                         regulator-max-microvolt = <1050000>;
 496                                 };
 497
 498                                 /* SW CTRL: +V1.0_VDD_CPU */
 499                                 vddctrl_reg: vddctrl {
 500                                         regulator-name = "vdd_cpu,vdd_sys";
 501                                         regulator-min-microvolt = <1150000>;
 502                                         regulator-max-microvolt = <1150000>;
 503                                         regulator-always-on;
 504                                 };
 505
 506                                 /* SWIO: +V1.8 */
 507                                 vio_reg: vio {
 508                                         regulator-name = "vdd_1v8_gen";
 509                                         regulator-min-microvolt = <1800000>;
 510                                         regulator-max-microvolt = <1800000>;
 511                                         regulator-always-on;
 512                                 };
 513
 514                                 /* LDO1: unused */
 515
 516                                 /*
 517                                  * EN_+V3.3 switching via FET:
 518                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
 519                                  * see also v3_3 fixed supply
 520                                  */
 521                                 ldo2_reg: ldo2 {
 522                                         regulator-name = "en_3v3";
 523                                         regulator-min-microvolt = <3300000>;
 524                                         regulator-max-microvolt = <3300000>;
 525                                         regulator-always-on;
 526                                 };
 527
 528                                 /* +V1.2_CSI */
 529                                 ldo3_reg: ldo3 {
 530                                         regulator-name =
 531                                                 "avdd_dsi_csi,pwrdet_mipi";
 532                                         regulator-min-microvolt = <1200000>;
 533                                         regulator-max-microvolt = <1200000>;
 534                                 };
 535
 536                                 /* +V1.2_VDD_RTC */
 537                                 ldo4_reg: ldo4 {
 538                                         regulator-name = "vdd_rtc";
 539                                         regulator-min-microvolt = <1200000>;
 540                                         regulator-max-microvolt = <1200000>;
 541                                         regulator-always-on;
 542                                 };
 543
 544                                 /*
 545                                  * +V2.8_AVDD_VDAC:
 546                                  * only required for analog RGB
 547                                  */
 548                                 ldo5_reg: ldo5 {
 549                                         regulator-name = "avdd_vdac";
 550                                         regulator-min-microvolt = <2800000>;
 551                                         regulator-max-microvolt = <2800000>;
 552                                         regulator-always-on;
 553                                 };
 554
 555                                 /*
 556                                  * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
 557                                  * but LDO6 can't set voltage in 50mV
 558                                  * granularity
 559                                  */
 560                                 ldo6_reg: ldo6 {
 561                                         regulator-name = "avdd_plle";
 562                                         regulator-min-microvolt = <1100000>;
 563                                         regulator-max-microvolt = <1100000>;
 564                                 };
 565
 566                                 /* +V1.2_AVDD_PLL */
 567                                 ldo7_reg: ldo7 {
 568                                         regulator-name = "avdd_pll";
 569                                         regulator-min-microvolt = <1200000>;
 570                                         regulator-max-microvolt = <1200000>;
 571                                         regulator-always-on;
 572                                 };
 573
 574                                 /* +V1.0_VDD_DDR_HS */
 575                                 ldo8_reg: ldo8 {
 576                                         regulator-name = "vdd_ddr_hs";
 577                                         regulator-min-microvolt = <1000000>;
 578                                         regulator-max-microvolt = <1000000>;
 579                                         regulator-always-on;
 580                                 };
 581                         };
 582                 };
 583
 584                 /* STMPE811 touch screen controller */
 585                 stmpe811@41 {
 586                         compatible = "st,stmpe811";
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589                         reg = <0x41>;
 590                         interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 591                         interrupt-parent = <&gpio>;
 592                         interrupt-controller;
 593                         id = <0>;
 594                         blocks = <0x5>;
 595                         irq-trigger = <0x1>;
 596
 597                         stmpe_touchscreen@0 {
 598                                 compatible = "st,stmpe-ts";
 599                                 reg = <0>;
 600                                 /* 3.25 MHz ADC clock speed */
 601                                 st,adc-freq = <1>;
 602                                 /* 8 sample average control */
 603                                 st,ave-ctrl = <3>;
 604                                 /* 7 length fractional part in z */
 605                                 st,fraction-z = <7>;
 606                                 /*
 607                                  * 50 mA typical 80 mA max touchscreen drivers
 608                                  * current limit value
 609                                  */
 610                                 st,i-drive = <1>;
 611                                 /* 12-bit ADC */
 612                                 st,mod-12b = <1>;
 613                                 /* internal ADC reference */
 614                                 st,ref-sel = <0>;
 615                                 /* ADC converstion time: 80 clocks */
 616                                 st,sample-time = <4>;
 617                                 /* 1 ms panel driver settling time */
 618                                 st,settling = <3>;
 619                                 /* 5 ms touch detect interrupt delay */
 620                                 st,touch-det-delay = <5>;
 621                         };
 622                 };
 623
 624                 /*
 625                  * LM95245 temperature sensor
 626                  * Note: OVERT_N directly connected to PMIC PWRDN
 627                  */
 628                 temp-sensor@4c {
 629                         compatible = "national,lm95245";
 630                         reg = <0x4c>;
 631                 };
 632
 633                 /* SW: +V1.2_VDD_CORE */
 634                 tps62362@60 {
 635                         compatible = "ti,tps62362";
 636                         reg = <0x60>;
 637
 638                         regulator-name = "tps62362-vout";
 639                         regulator-min-microvolt = <900000>;
 640                         regulator-max-microvolt = <1400000>;
 641                         regulator-boot-on;
 642                         regulator-always-on;
 643                         ti,vsel0-state-low;
 644                         /* VSEL1: EN_CORE_DVFS_N low for DVFS */
 645                         ti,vsel1-state-low;
 646                 };
 647         };
 648
 649         /* SPI4: CAN2 */
 650         spi@7000da00 {
 651                 status = "okay";
 652                 spi-max-frequency = <10000000>;
 653
 654                 can@1 {
 655                         compatible = "microchip,mcp2515";
 656                         reg = <1>;
 657                         clocks = <&clk16m>;
 658                         interrupt-parent = <&gpio>;
 659                         interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
 660                         spi-max-frequency = <10000000>;
 661                 };
 662         };
 663
 664         /* SPI6: CAN1 */
 665         spi@7000de00 {
 666                 status = "okay";
 667                 spi-max-frequency = <10000000>;
 668
 669                 can@0 {
 670                         compatible = "microchip,mcp2515";
 671                         reg = <0>;
 672                         clocks = <&clk16m>;
 673                         interrupt-parent = <&gpio>;
 674                         interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
 675                         spi-max-frequency = <10000000>;
 676                 };
 677         };
 678
 679         pmc@7000e400 {
 680                 nvidia,invert-interrupt;
 681                 nvidia,suspend-mode = <1>;
 682                 nvidia,cpu-pwr-good-time = <5000>;
 683                 nvidia,cpu-pwr-off-time = <5000>;
 684                 nvidia,core-pwr-good-time = <3845 3845>;
 685                 nvidia,core-pwr-off-time = <0>;
 686                 nvidia,core-power-req-active-high;
 687                 nvidia,sys-clock-req-active-high;
 688         };
 689
 690         ahub@70080000 {
 691                 i2s@70080500 {
 692                         status = "okay";
 693                 };
 694         };
 695
 696         /* eMMC */
 697         sdhci@78000600 {
 698                 status = "okay";
 699                 bus-width = <8>;
 700                 non-removable;
 701         };
 702
 703         clocks {
 704                 compatible = "simple-bus";
 705                 #address-cells = <1>;
 706                 #size-cells = <0>;
 707
 708                 clk32k_in: clk@0 {
 709                         compatible = "fixed-clock";
 710                         reg = <0>;
 711                         #clock-cells = <0>;
 712                         clock-frequency = <32768>;
 713                 };
 714
 715                 clk16m: clk@1 {
 716                         compatible = "fixed-clock";
 717                         reg = <1>;
 718                         #clock-cells = <0>;
 719                         clock-frequency = <16000000>;
 720                         clock-output-names = "clk16m";
 721                 };
 722         };
 723
 724         regulators {
 725                 compatible = "simple-bus";
 726                 #address-cells = <1>;
 727                 #size-cells = <0>;
 728
 729                 avdd_hdmi_pll_1v8_reg: regulator@100 {
 730                         compatible = "regulator-fixed";
 731                         reg = <100>;
 732                         regulator-name = "+V1.8_AVDD_HDMI_PLL";
 733                         regulator-min-microvolt = <1800000>;
 734                         regulator-max-microvolt = <1800000>;
 735                         enable-active-high;
 736                         gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 737                         vin-supply = <&vio_reg>;
 738                 };
 739
 740                 sys_3v3_reg: regulator@101 {
 741                         compatible = "regulator-fixed";
 742                         reg = <101>;
 743                         regulator-name = "3v3";
 744                         regulator-min-microvolt = <3300000>;
 745                         regulator-max-microvolt = <3300000>;
 746                         regulator-always-on;
 747                 };
 748
 749                 avdd_hdmi_3v3_reg: regulator@102 {
 750                         compatible = "regulator-fixed";
 751                         reg = <102>;
 752                         regulator-name = "+V3.3_AVDD_HDMI";
 753                         regulator-min-microvolt = <3300000>;
 754                         regulator-max-microvolt = <3300000>;
 755                         enable-active-high;
 756                         gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 757                         vin-supply = <&sys_3v3_reg>;
 758                 };
 759
 760                 charge_pump_5v0_reg: regulator@103 {
 761                         compatible = "regulator-fixed";
 762                         reg = <103>;
 763                         regulator-name = "5v0";
 764                         regulator-min-microvolt = <5000000>;
 765                         regulator-max-microvolt = <5000000>;
 766                         regulator-always-on;
 767                 };
 768         };
 769
 770         sound {
 771                 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
 772                              "nvidia,tegra-audio-sgtl5000";
 773                 nvidia,model = "Toradex Apalis T30";
 774                 nvidia,audio-routing =
 775                         "Headphone Jack", "HP_OUT",
 776                         "LINE_IN", "Line In Jack",
 777                         "MIC_IN", "Mic Jack";
 778                 nvidia,i2s-controller = <&tegra_i2s2>;
 779                 nvidia,audio-codec = <&sgtl5000>;
 780                 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 781                          <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
 782                          <&tegra_car TEGRA30_CLK_EXTERN1>;
 783                 clock-names = "pll_a", "pll_a_out0", "mclk";
 784         };
 785 };