arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         intc: interrupt-controller {
   8                 compatible = "arm,cortex-a9-gic";
   9                 reg = <0x50041000 0x1000
  10                        0x50040100 0x0100>;
  11                 interrupt-controller;
  12                 #interrupt-cells = <3>;
  13         };
  14
  15         apbdma: dma {
  16                 compatible = "nvidia,tegra20-apbdma";
  17                 reg = <0x6000a000 0x1200>;
  18                 interrupts = <0 104 0x04
  19                               0 105 0x04
  20                               0 106 0x04
  21                               0 107 0x04
  22                               0 108 0x04
  23                               0 109 0x04
  24                               0 110 0x04
  25                               0 111 0x04
  26                               0 112 0x04
  27                               0 113 0x04
  28                               0 114 0x04
  29                               0 115 0x04
  30                               0 116 0x04
  31                               0 117 0x04
  32                               0 118 0x04
  33                               0 119 0x04>;
  34         };
  35
  36         ahb {
  37                 compatible = "nvidia,tegra20-ahb";
  38                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
  39         };
  40
  41         gpio: gpio {
  42                 compatible = "nvidia,tegra20-gpio";
  43                 reg = <0x6000d000 0x1000>;
  44                 interrupts = <0 32 0x04
  45                               0 33 0x04
  46                               0 34 0x04
  47                               0 35 0x04
  48                               0 55 0x04
  49                               0 87 0x04
  50                               0 89 0x04>;
  51                 #gpio-cells = <2>;
  52                 gpio-controller;
  53                 #interrupt-cells = <2>;
  54                 interrupt-controller;
  55         };
  56
  57         pinmux: pinmux {
  58                 compatible = "nvidia,tegra20-pinmux";
  59                 reg = <0x70000014 0x10   /* Tri-state registers */
  60                        0x70000080 0x20   /* Mux registers */
  61                        0x700000a0 0x14   /* Pull-up/down registers */
  62                        0x70000868 0xa8>; /* Pad control registers */
  63         };
  64
  65         das {
  66                 compatible = "nvidia,tegra20-das";
  67                 reg = <0x70000c00 0x80>;
  68         };
  69
  70         tegra_i2s1: i2s@70002800 {
  71                 compatible = "nvidia,tegra20-i2s";
  72                 reg = <0x70002800 0x200>;
  73                 interrupts = <0 13 0x04>;
  74                 nvidia,dma-request-selector = <&apbdma 2>;
  75                 status = "disabled";
  76         };
  77
  78         tegra_i2s2: i2s@70002a00 {
  79                 compatible = "nvidia,tegra20-i2s";
  80                 reg = <0x70002a00 0x200>;
  81                 interrupts = <0 3 0x04>;
  82                 nvidia,dma-request-selector = <&apbdma 1>;
  83                 status = "disabled";
  84         };
  85
  86         serial@70006000 {
  87                 compatible = "nvidia,tegra20-uart";
  88                 reg = <0x70006000 0x40>;
  89                 reg-shift = <2>;
  90                 interrupts = <0 36 0x04>;
  91                 status = "disabled";
  92         };
  93
  94         serial@70006040 {
  95                 compatible = "nvidia,tegra20-uart";
  96                 reg = <0x70006040 0x40>;
  97                 reg-shift = <2>;
  98                 interrupts = <0 37 0x04>;
  99                 status = "disabled";
 100         };
 101
 102         serial@70006200 {
 103                 compatible = "nvidia,tegra20-uart";
 104                 reg = <0x70006200 0x100>;
 105                 reg-shift = <2>;
 106                 interrupts = <0 46 0x04>;
 107                 status = "disabled";
 108         };
 109
 110         serial@70006300 {
 111                 compatible = "nvidia,tegra20-uart";
 112                 reg = <0x70006300 0x100>;
 113                 reg-shift = <2>;
 114                 interrupts = <0 90 0x04>;
 115                 status = "disabled";
 116         };
 117
 118         serial@70006400 {
 119                 compatible = "nvidia,tegra20-uart";
 120                 reg = <0x70006400 0x100>;
 121                 reg-shift = <2>;
 122                 interrupts = <0 91 0x04>;
 123                 status = "disabled";
 124         };
 125
 126         pwm: pwm {
 127                 compatible = "nvidia,tegra20-pwm";
 128                 reg = <0x7000a000 0x100>;
 129                 #pwm-cells = <2>;
 130         };
 131
 132         i2c@7000c000 {
 133                 compatible = "nvidia,tegra20-i2c";
 134                 reg = <0x7000c000 0x100>;
 135                 interrupts = <0 38 0x04>;
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138                 status = "disabled";
 139         };
 140
 141         i2c@7000c400 {
 142                 compatible = "nvidia,tegra20-i2c";
 143                 reg = <0x7000c400 0x100>;
 144                 interrupts = <0 84 0x04>;
 145                 #address-cells = <1>;
 146                 #size-cells = <0>;
 147                 status = "disabled";
 148         };
 149
 150         i2c@7000c500 {
 151                 compatible = "nvidia,tegra20-i2c";
 152                 reg = <0x7000c500 0x100>;
 153                 interrupts = <0 92 0x04>;
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156                 status = "disabled";
 157         };
 158
 159         i2c@7000d000 {
 160                 compatible = "nvidia,tegra20-i2c-dvc";
 161                 reg = <0x7000d000 0x200>;
 162                 interrupts = <0 53 0x04>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 status = "disabled";
 166         };
 167
 168         pmc {
 169                 compatible = "nvidia,tegra20-pmc";
 170                 reg = <0x7000e400 0x400>;
 171         };
 172
 173         memory-controller@7000f000 {
 174                 compatible = "nvidia,tegra20-mc";
 175                 reg = <0x7000f000 0x024
 176                        0x7000f03c 0x3c4>;
 177                 interrupts = <0 77 0x04>;
 178         };
 179
 180         gart {
 181                 compatible = "nvidia,tegra20-gart";
 182                 reg = <0x7000f024 0x00000018    /* controller registers */
 183                        0x58000000 0x02000000>;  /* GART aperture */
 184         };
 185
 186         memory-controller@7000f400 {
 187                 compatible = "nvidia,tegra20-emc";
 188                 reg = <0x7000f400 0x200>;
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191         };
 192
 193         usb@c5000000 {
 194                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 195                 reg = <0xc5000000 0x4000>;
 196                 interrupts = <0 20 0x04>;
 197                 phy_type = "utmi";
 198                 nvidia,has-legacy-mode;
 199                 status = "disabled";
 200         };
 201
 202         usb@c5004000 {
 203                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 204                 reg = <0xc5004000 0x4000>;
 205                 interrupts = <0 21 0x04>;
 206                 phy_type = "ulpi";
 207                 status = "disabled";
 208         };
 209
 210         usb@c5008000 {
 211                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 212                 reg = <0xc5008000 0x4000>;
 213                 interrupts = <0 97 0x04>;
 214                 phy_type = "utmi";
 215                 status = "disabled";
 216         };
 217
 218         sdhci@c8000000 {
 219                 compatible = "nvidia,tegra20-sdhci";
 220                 reg = <0xc8000000 0x200>;
 221                 interrupts = <0 14 0x04>;
 222                 status = "disabled";
 223         };
 224
 225         sdhci@c8000200 {
 226                 compatible = "nvidia,tegra20-sdhci";
 227                 reg = <0xc8000200 0x200>;
 228                 interrupts = <0 15 0x04>;
 229                 status = "disabled";
 230         };
 231
 232         sdhci@c8000400 {
 233                 compatible = "nvidia,tegra20-sdhci";
 234                 reg = <0xc8000400 0x200>;
 235                 interrupts = <0 19 0x04>;
 236                 status = "disabled";
 237         };
 238
 239         sdhci@c8000600 {
 240                 compatible = "nvidia,tegra20-sdhci";
 241                 reg = <0xc8000600 0x200>;
 242                 interrupts = <0 31 0x04>;
 243                 status = "disabled";
 244         };
 245
 246         pmu {
 247                 compatible = "arm,cortex-a9-pmu";
 248                 interrupts = <0 56 0x04
 249                               0 57 0x04>;
 250         };
 251 };