1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/reset/tegra124-car.h>
7 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include "skeleton.dtsi"
12 compatible = "nvidia,tegra124";
13 interrupt-parent = <&lic>;
18 compatible = "nvidia,tegra124-pcie";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43 <&tegra_car TEGRA124_CLK_AFI>,
44 <&tegra_car TEGRA124_CLK_PLL_E>,
45 <&tegra_car TEGRA124_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
50 reset-names = "pex", "afi", "pcie_x";
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 bus-range = <0x00 0xff>;
64 nvidia,num-lanes = <2>;
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
71 bus-range = <0x00 0xff>;
78 nvidia,num-lanes = <1>;
83 compatible = "nvidia,tegra124-host1x", "simple-bus";
84 reg = <0x0 0x50000000 0x0 0x00034000>;
85 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
86 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
87 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
88 resets = <&tegra_car 28>;
89 reset-names = "host1x";
94 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
97 compatible = "nvidia,tegra124-dc";
98 reg = <0x0 0x54200000 0x0 0x00040000>;
99 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
101 <&tegra_car TEGRA124_CLK_PLL_P>;
102 clock-names = "dc", "parent";
103 resets = <&tegra_car 27>;
106 iommus = <&mc TEGRA_SWGROUP_DC>;
112 compatible = "nvidia,tegra124-dc";
113 reg = <0x0 0x54240000 0x0 0x00040000>;
114 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
116 <&tegra_car TEGRA124_CLK_PLL_P>;
117 clock-names = "dc", "parent";
118 resets = <&tegra_car 26>;
121 iommus = <&mc TEGRA_SWGROUP_DCB>;
127 compatible = "nvidia,tegra124-hdmi";
128 reg = <0x0 0x54280000 0x0 0x00040000>;
129 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
131 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
132 clock-names = "hdmi", "parent";
133 resets = <&tegra_car 51>;
134 reset-names = "hdmi";
139 compatible = "nvidia,tegra124-sor";
140 reg = <0x0 0x54540000 0x0 0x00040000>;
141 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
143 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
144 <&tegra_car TEGRA124_CLK_PLL_DP>,
145 <&tegra_car TEGRA124_CLK_CLK_M>;
146 clock-names = "sor", "parent", "dp", "safe";
147 resets = <&tegra_car 182>;
152 dpaux: dpaux@545c0000 {
153 compatible = "nvidia,tegra124-dpaux";
154 reg = <0x0 0x545c0000 0x0 0x00040000>;
155 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
157 <&tegra_car TEGRA124_CLK_PLL_DP>;
158 clock-names = "dpaux", "parent";
159 resets = <&tegra_car 181>;
160 reset-names = "dpaux";
165 gic: interrupt-controller@50041000 {
166 compatible = "arm,cortex-a15-gic";
167 #interrupt-cells = <3>;
168 interrupt-controller;
169 reg = <0x0 0x50041000 0x0 0x1000>,
170 <0x0 0x50042000 0x0 0x1000>,
171 <0x0 0x50044000 0x0 0x2000>,
172 <0x0 0x50046000 0x0 0x2000>;
173 interrupts = <GIC_PPI 9
174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
175 interrupt-parent = <&gic>;
179 * Please keep the following 0, notation in place as a former mainline
180 * U-Boot version was looking for that particular notation in order to
181 * perform required fix-ups on that GPU node.
184 compatible = "nvidia,gk20a";
185 reg = <0x0 0x57000000 0x0 0x01000000>,
186 <0x0 0x58000000 0x0 0x01000000>;
187 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "stall", "nonstall";
190 clocks = <&tegra_car TEGRA124_CLK_GPU>,
191 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
192 clock-names = "gpu", "pwr";
193 resets = <&tegra_car 184>;
196 iommus = <&mc TEGRA_SWGROUP_GPU>;
201 lic: interrupt-controller@60004000 {
202 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
203 reg = <0x0 0x60004000 0x0 0x100>,
204 <0x0 0x60004100 0x0 0x100>,
205 <0x0 0x60004200 0x0 0x100>,
206 <0x0 0x60004300 0x0 0x100>,
207 <0x0 0x60004400 0x0 0x100>;
208 interrupt-controller;
209 #interrupt-cells = <3>;
210 interrupt-parent = <&gic>;
214 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
215 reg = <0x0 0x60005000 0x0 0x400>;
216 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
225 tegra_car: clock@60006000 {
226 compatible = "nvidia,tegra124-car";
227 reg = <0x0 0x60006000 0x0 0x1000>;
230 nvidia,external-memory-controller = <&emc>;
233 flow-controller@60007000 {
234 compatible = "nvidia,tegra124-flowctrl";
235 reg = <0x0 0x60007000 0x0 0x1000>;
239 compatible = "nvidia,tegra124-actmon";
240 reg = <0x0 0x6000c800 0x0 0x400>;
241 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
243 <&tegra_car TEGRA124_CLK_EMC>;
244 clock-names = "actmon", "emc";
245 resets = <&tegra_car 119>;
246 reset-names = "actmon";
249 gpio: gpio@6000d000 {
250 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
251 reg = <0x0 0x6000d000 0x0 0x1000>;
252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
262 #interrupt-cells = <2>;
263 interrupt-controller;
265 gpio-ranges = <&pinmux 0 0 251>;
269 apbdma: dma@60020000 {
270 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
271 reg = <0x0 0x60020000 0x0 0x1400>;
272 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
305 resets = <&tegra_car 34>;
311 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
312 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
313 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
316 pinmux: pinmux@70000868 {
317 compatible = "nvidia,tegra124-pinmux";
318 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
319 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
320 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
324 * There are two serial driver i.e. 8250 based simple serial
325 * driver and APB DMA based serial driver for higher baudrate
326 * and performace. To enable the 8250 based driver, the compatible
327 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
328 * the APB DMA based serial driver, the compatible is
329 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
331 uarta: serial@70006000 {
332 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
333 reg = <0x0 0x70006000 0x0 0x40>;
335 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
337 resets = <&tegra_car 6>;
338 reset-names = "serial";
339 dmas = <&apbdma 8>, <&apbdma 8>;
340 dma-names = "rx", "tx";
344 uartb: serial@70006040 {
345 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
346 reg = <0x0 0x70006040 0x0 0x40>;
348 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
350 resets = <&tegra_car 7>;
351 reset-names = "serial";
352 dmas = <&apbdma 9>, <&apbdma 9>;
353 dma-names = "rx", "tx";
357 uartc: serial@70006200 {
358 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
359 reg = <0x0 0x70006200 0x0 0x40>;
361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
363 resets = <&tegra_car 55>;
364 reset-names = "serial";
365 dmas = <&apbdma 10>, <&apbdma 10>;
366 dma-names = "rx", "tx";
370 uartd: serial@70006300 {
371 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
372 reg = <0x0 0x70006300 0x0 0x40>;
374 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
376 resets = <&tegra_car 65>;
377 reset-names = "serial";
378 dmas = <&apbdma 19>, <&apbdma 19>;
379 dma-names = "rx", "tx";
384 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
385 reg = <0x0 0x7000a000 0x0 0x100>;
387 clocks = <&tegra_car TEGRA124_CLK_PWM>;
388 resets = <&tegra_car 17>;
394 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
395 reg = <0x0 0x7000c000 0x0 0x100>;
396 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;
399 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
400 clock-names = "div-clk";
401 resets = <&tegra_car 12>;
403 dmas = <&apbdma 21>, <&apbdma 21>;
404 dma-names = "rx", "tx";
409 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
410 reg = <0x0 0x7000c400 0x0 0x100>;
411 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
414 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
415 clock-names = "div-clk";
416 resets = <&tegra_car 54>;
418 dmas = <&apbdma 22>, <&apbdma 22>;
419 dma-names = "rx", "tx";
424 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
425 reg = <0x0 0x7000c500 0x0 0x100>;
426 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
429 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
430 clock-names = "div-clk";
431 resets = <&tegra_car 67>;
433 dmas = <&apbdma 23>, <&apbdma 23>;
434 dma-names = "rx", "tx";
439 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
440 reg = <0x0 0x7000c700 0x0 0x100>;
441 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
444 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
445 clock-names = "div-clk";
446 resets = <&tegra_car 103>;
448 dmas = <&apbdma 26>, <&apbdma 26>;
449 dma-names = "rx", "tx";
454 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
455 reg = <0x0 0x7000d000 0x0 0x100>;
456 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
457 #address-cells = <1>;
459 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
460 clock-names = "div-clk";
461 resets = <&tegra_car 47>;
463 dmas = <&apbdma 24>, <&apbdma 24>;
464 dma-names = "rx", "tx";
469 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
470 reg = <0x0 0x7000d100 0x0 0x100>;
471 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
472 #address-cells = <1>;
474 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
475 clock-names = "div-clk";
476 resets = <&tegra_car 166>;
478 dmas = <&apbdma 30>, <&apbdma 30>;
479 dma-names = "rx", "tx";
484 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
485 reg = <0x0 0x7000d400 0x0 0x200>;
486 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
487 #address-cells = <1>;
489 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
491 resets = <&tegra_car 41>;
493 dmas = <&apbdma 15>, <&apbdma 15>;
494 dma-names = "rx", "tx";
499 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
500 reg = <0x0 0x7000d600 0x0 0x200>;
501 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
504 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
506 resets = <&tegra_car 44>;
508 dmas = <&apbdma 16>, <&apbdma 16>;
509 dma-names = "rx", "tx";
514 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
515 reg = <0x0 0x7000d800 0x0 0x200>;
516 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
519 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
521 resets = <&tegra_car 46>;
523 dmas = <&apbdma 17>, <&apbdma 17>;
524 dma-names = "rx", "tx";
529 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
530 reg = <0x0 0x7000da00 0x0 0x200>;
531 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
532 #address-cells = <1>;
534 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
536 resets = <&tegra_car 68>;
538 dmas = <&apbdma 18>, <&apbdma 18>;
539 dma-names = "rx", "tx";
544 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
545 reg = <0x0 0x7000dc00 0x0 0x200>;
546 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
549 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
551 resets = <&tegra_car 104>;
553 dmas = <&apbdma 27>, <&apbdma 27>;
554 dma-names = "rx", "tx";
559 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
560 reg = <0x0 0x7000de00 0x0 0x200>;
561 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
562 #address-cells = <1>;
564 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
566 resets = <&tegra_car 105>;
568 dmas = <&apbdma 28>, <&apbdma 28>;
569 dma-names = "rx", "tx";
574 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
575 reg = <0x0 0x7000e000 0x0 0x100>;
576 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&tegra_car TEGRA124_CLK_RTC>;
581 compatible = "nvidia,tegra124-pmc";
582 reg = <0x0 0x7000e400 0x0 0x400>;
583 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
584 clock-names = "pclk", "clk32k_in";
588 compatible = "nvidia,tegra124-efuse";
589 reg = <0x0 0x7000f800 0x0 0x400>;
590 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
591 clock-names = "fuse";
592 resets = <&tegra_car 39>;
593 reset-names = "fuse";
596 mc: memory-controller@70019000 {
597 compatible = "nvidia,tegra124-mc";
598 reg = <0x0 0x70019000 0x0 0x1000>;
599 clocks = <&tegra_car TEGRA124_CLK_MC>;
602 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
608 compatible = "nvidia,tegra124-emc";
609 reg = <0x0 0x7001b000 0x0 0x1000>;
611 nvidia,memory-controller = <&mc>;
615 compatible = "nvidia,tegra124-ahci";
616 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
617 <0x0 0x70020000 0x0 0x7000>; /* SATA */
618 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&tegra_car TEGRA124_CLK_SATA>,
620 <&tegra_car TEGRA124_CLK_SATA_OOB>,
621 <&tegra_car TEGRA124_CLK_CML1>,
622 <&tegra_car TEGRA124_CLK_PLL_E>;
623 clock-names = "sata", "sata-oob", "cml1", "pll_e";
624 resets = <&tegra_car 124>,
627 reset-names = "sata", "sata-oob", "sata-cold";
632 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
633 reg = <0x0 0x70030000 0x0 0x10000>;
634 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&tegra_car TEGRA124_CLK_HDA>,
636 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
637 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
638 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
639 resets = <&tegra_car 125>, /* hda */
640 <&tegra_car 128>, /* hda2hdmi */
641 <&tegra_car 111>; /* hda2codec_2x */
642 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
647 compatible = "nvidia,tegra124-xusb";
648 reg = <0x0 0x70090000 0x0 0x8000>,
649 <0x0 0x70098000 0x0 0x1000>,
650 <0x0 0x70099000 0x0 0x1000>;
651 reg-names = "hcd", "fpci", "ipfs";
653 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
657 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
658 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
659 <&tegra_car TEGRA124_CLK_XUSB_SS>,
660 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
661 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
662 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
663 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
664 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
665 <&tegra_car TEGRA124_CLK_CLK_M>,
666 <&tegra_car TEGRA124_CLK_PLL_E>;
667 clock-names = "xusb_host", "xusb_host_src",
668 "xusb_falcon_src", "xusb_ss",
669 "xusb_ss_div2", "xusb_ss_src",
670 "xusb_hs_src", "xusb_fs_src",
671 "pll_u_480m", "clk_m", "pll_e";
672 resets = <&tegra_car 89>, <&tegra_car 156>,
674 reset-names = "xusb_host", "xusb_ss", "xusb_src";
676 nvidia,xusb-padctl = <&padctl>;
681 padctl: padctl@7009f000 {
682 compatible = "nvidia,tegra124-xusb-padctl";
683 reg = <0x0 0x7009f000 0x0 0x1000>;
684 resets = <&tegra_car 142>;
685 reset-names = "padctl";
815 compatible = "nvidia,tegra124-sdhci";
816 reg = <0x0 0x700b0000 0x0 0x200>;
817 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
819 resets = <&tegra_car 14>;
820 reset-names = "sdhci";
825 compatible = "nvidia,tegra124-sdhci";
826 reg = <0x0 0x700b0200 0x0 0x200>;
827 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
829 resets = <&tegra_car 9>;
830 reset-names = "sdhci";
835 compatible = "nvidia,tegra124-sdhci";
836 reg = <0x0 0x700b0400 0x0 0x200>;
837 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
839 resets = <&tegra_car 69>;
840 reset-names = "sdhci";
845 compatible = "nvidia,tegra124-sdhci";
846 reg = <0x0 0x700b0600 0x0 0x200>;
847 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
849 resets = <&tegra_car 15>;
850 reset-names = "sdhci";
854 soctherm: thermal-sensor@700e2000 {
855 compatible = "nvidia,tegra124-soctherm";
856 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
857 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
858 reg-names = "soctherm-reg", "car-reg";
859 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
861 <&tegra_car TEGRA124_CLK_SOC_THERM>;
862 clock-names = "tsensor", "soctherm";
863 resets = <&tegra_car 78>;
864 reset-names = "soctherm";
865 #thermal-sensor-cells = <1>;
868 throttle_heavy: heavy {
869 nvidia,priority = <100>;
870 nvidia,cpu-throt-percent = <85>;
872 #cooling-cells = <2>;
877 dfll: clock@70110000 {
878 compatible = "nvidia,tegra124-dfll";
879 reg = <0 0x70110000 0 0x100>, /* DFLL control */
880 <0 0x70110000 0 0x100>, /* I2C output control */
881 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
882 <0 0x70110200 0 0x100>; /* Look-up table RAM */
883 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
885 <&tegra_car TEGRA124_CLK_DFLL_REF>,
886 <&tegra_car TEGRA124_CLK_I2C5>;
887 clock-names = "soc", "ref", "i2c";
888 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
889 reset-names = "dvco";
891 clock-output-names = "dfllCPU_out";
892 nvidia,sample-rate = <12500>;
893 nvidia,droop-ctrl = <0x00000f00>;
894 nvidia,force-mode = <1>;
902 compatible = "nvidia,tegra124-ahub";
903 reg = <0x0 0x70300000 0x0 0x200>,
904 <0x0 0x70300800 0x0 0x800>,
905 <0x0 0x70300200 0x0 0x600>;
906 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
908 <&tegra_car TEGRA124_CLK_APBIF>;
909 clock-names = "d_audio", "apbif";
910 resets = <&tegra_car 106>, /* d_audio */
911 <&tegra_car 107>, /* apbif */
912 <&tegra_car 30>, /* i2s0 */
913 <&tegra_car 11>, /* i2s1 */
914 <&tegra_car 18>, /* i2s2 */
915 <&tegra_car 101>, /* i2s3 */
916 <&tegra_car 102>, /* i2s4 */
917 <&tegra_car 108>, /* dam0 */
918 <&tegra_car 109>, /* dam1 */
919 <&tegra_car 110>, /* dam2 */
920 <&tegra_car 10>, /* spdif */
921 <&tegra_car 153>, /* amx */
922 <&tegra_car 185>, /* amx1 */
923 <&tegra_car 154>, /* adx */
924 <&tegra_car 180>, /* adx1 */
925 <&tegra_car 186>, /* afc0 */
926 <&tegra_car 187>, /* afc1 */
927 <&tegra_car 188>, /* afc2 */
928 <&tegra_car 189>, /* afc3 */
929 <&tegra_car 190>, /* afc4 */
930 <&tegra_car 191>; /* afc5 */
931 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
932 "i2s3", "i2s4", "dam0", "dam1", "dam2",
933 "spdif", "amx", "amx1", "adx", "adx1",
934 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
935 dmas = <&apbdma 1>, <&apbdma 1>,
936 <&apbdma 2>, <&apbdma 2>,
937 <&apbdma 3>, <&apbdma 3>,
938 <&apbdma 4>, <&apbdma 4>,
939 <&apbdma 6>, <&apbdma 6>,
940 <&apbdma 7>, <&apbdma 7>,
941 <&apbdma 12>, <&apbdma 12>,
942 <&apbdma 13>, <&apbdma 13>,
943 <&apbdma 14>, <&apbdma 14>,
944 <&apbdma 29>, <&apbdma 29>;
945 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
946 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
947 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
950 #address-cells = <2>;
953 tegra_i2s0: i2s@70301000 {
954 compatible = "nvidia,tegra124-i2s";
955 reg = <0x0 0x70301000 0x0 0x100>;
956 nvidia,ahub-cif-ids = <4 4>;
957 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
958 resets = <&tegra_car 30>;
963 tegra_i2s1: i2s@70301100 {
964 compatible = "nvidia,tegra124-i2s";
965 reg = <0x0 0x70301100 0x0 0x100>;
966 nvidia,ahub-cif-ids = <5 5>;
967 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
968 resets = <&tegra_car 11>;
973 tegra_i2s2: i2s@70301200 {
974 compatible = "nvidia,tegra124-i2s";
975 reg = <0x0 0x70301200 0x0 0x100>;
976 nvidia,ahub-cif-ids = <6 6>;
977 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
978 resets = <&tegra_car 18>;
983 tegra_i2s3: i2s@70301300 {
984 compatible = "nvidia,tegra124-i2s";
985 reg = <0x0 0x70301300 0x0 0x100>;
986 nvidia,ahub-cif-ids = <7 7>;
987 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
988 resets = <&tegra_car 101>;
993 tegra_i2s4: i2s@70301400 {
994 compatible = "nvidia,tegra124-i2s";
995 reg = <0x0 0x70301400 0x0 0x100>;
996 nvidia,ahub-cif-ids = <8 8>;
997 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
998 resets = <&tegra_car 102>;
1000 status = "disabled";
1005 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1006 reg = <0x0 0x7d000000 0x0 0x4000>;
1007 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1010 resets = <&tegra_car 22>;
1011 reset-names = "usb";
1012 nvidia,phy = <&phy1>;
1013 status = "disabled";
1016 phy1: usb-phy@7d000000 {
1017 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1018 reg = <0x0 0x7d000000 0x0 0x4000>,
1019 <0x0 0x7d000000 0x0 0x4000>;
1021 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1022 <&tegra_car TEGRA124_CLK_PLL_U>,
1023 <&tegra_car TEGRA124_CLK_USBD>;
1024 clock-names = "reg", "pll_u", "utmi-pads";
1025 resets = <&tegra_car 22>, <&tegra_car 22>;
1026 reset-names = "usb", "utmi-pads";
1027 nvidia,hssync-start-delay = <0>;
1028 nvidia,idle-wait-delay = <17>;
1029 nvidia,elastic-limit = <16>;
1030 nvidia,term-range-adj = <6>;
1031 nvidia,xcvr-setup = <9>;
1032 nvidia,xcvr-lsfslew = <0>;
1033 nvidia,xcvr-lsrslew = <3>;
1034 nvidia,hssquelch-level = <2>;
1035 nvidia,hsdiscon-level = <5>;
1036 nvidia,xcvr-hsslew = <12>;
1037 nvidia,has-utmi-pad-registers;
1038 status = "disabled";
1042 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1043 reg = <0x0 0x7d004000 0x0 0x4000>;
1044 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1047 resets = <&tegra_car 58>;
1048 reset-names = "usb";
1049 nvidia,phy = <&phy2>;
1050 status = "disabled";
1053 phy2: usb-phy@7d004000 {
1054 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1055 reg = <0x0 0x7d004000 0x0 0x4000>,
1056 <0x0 0x7d000000 0x0 0x4000>;
1058 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1059 <&tegra_car TEGRA124_CLK_PLL_U>,
1060 <&tegra_car TEGRA124_CLK_USBD>;
1061 clock-names = "reg", "pll_u", "utmi-pads";
1062 resets = <&tegra_car 58>, <&tegra_car 22>;
1063 reset-names = "usb", "utmi-pads";
1064 nvidia,hssync-start-delay = <0>;
1065 nvidia,idle-wait-delay = <17>;
1066 nvidia,elastic-limit = <16>;
1067 nvidia,term-range-adj = <6>;
1068 nvidia,xcvr-setup = <9>;
1069 nvidia,xcvr-lsfslew = <0>;
1070 nvidia,xcvr-lsrslew = <3>;
1071 nvidia,hssquelch-level = <2>;
1072 nvidia,hsdiscon-level = <5>;
1073 nvidia,xcvr-hsslew = <12>;
1074 status = "disabled";
1078 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1079 reg = <0x0 0x7d008000 0x0 0x4000>;
1080 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1083 resets = <&tegra_car 59>;
1084 reset-names = "usb";
1085 nvidia,phy = <&phy3>;
1086 status = "disabled";
1089 phy3: usb-phy@7d008000 {
1090 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1091 reg = <0x0 0x7d008000 0x0 0x4000>,
1092 <0x0 0x7d000000 0x0 0x4000>;
1094 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1095 <&tegra_car TEGRA124_CLK_PLL_U>,
1096 <&tegra_car TEGRA124_CLK_USBD>;
1097 clock-names = "reg", "pll_u", "utmi-pads";
1098 resets = <&tegra_car 59>, <&tegra_car 22>;
1099 reset-names = "usb", "utmi-pads";
1100 nvidia,hssync-start-delay = <0>;
1101 nvidia,idle-wait-delay = <17>;
1102 nvidia,elastic-limit = <16>;
1103 nvidia,term-range-adj = <6>;
1104 nvidia,xcvr-setup = <9>;
1105 nvidia,xcvr-lsfslew = <0>;
1106 nvidia,xcvr-lsrslew = <3>;
1107 nvidia,hssquelch-level = <2>;
1108 nvidia,hsdiscon-level = <5>;
1109 nvidia,xcvr-hsslew = <12>;
1110 status = "disabled";
1114 #address-cells = <1>;
1118 device_type = "cpu";
1119 compatible = "arm,cortex-a15";
1122 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1123 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1124 <&tegra_car TEGRA124_CLK_PLL_X>,
1125 <&tegra_car TEGRA124_CLK_PLL_P>,
1127 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1128 /* FIXME: what's the actual transition time? */
1129 clock-latency = <300000>;
1133 device_type = "cpu";
1134 compatible = "arm,cortex-a15";
1139 device_type = "cpu";
1140 compatible = "arm,cortex-a15";
1145 device_type = "cpu";
1146 compatible = "arm,cortex-a15";
1152 compatible = "arm,cortex-a15-pmu";
1153 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1157 interrupt-affinity = <&{/cpus/cpu@0}>,
1165 polling-delay-passive = <1000>;
1166 polling-delay = <1000>;
1169 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1173 temperature = <103000>;
1177 cpu_throttle_trip: throttle-trip {
1178 temperature = <100000>;
1179 hysteresis = <1000>;
1186 trip = <&cpu_throttle_trip>;
1187 cooling-device = <&throttle_heavy 1 1>;
1193 polling-delay-passive = <1000>;
1194 polling-delay = <1000>;
1197 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1201 temperature = <103000>;
1209 * There are currently no cooling maps,
1210 * because there are no cooling devices.
1216 polling-delay-passive = <1000>;
1217 polling-delay = <1000>;
1220 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1224 temperature = <101000>;
1228 gpu_throttle_trip: throttle-trip {
1229 temperature = <99000>;
1230 hysteresis = <1000>;
1237 trip = <&gpu_throttle_trip>;
1238 cooling-device = <&throttle_heavy 1 1>;
1244 polling-delay-passive = <1000>;
1245 polling-delay = <1000>;
1248 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1251 pllx-shutdown-trip {
1252 temperature = <103000>;
1260 * There are currently no cooling maps,
1261 * because there are no cooling devices.
1268 compatible = "arm,armv7-timer";
1269 interrupts = <GIC_PPI 13
1270 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1272 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1276 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1277 interrupt-parent = <&gic>;