arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
  48 #include <dt-bindings/clock/sun9i-a80-de.h>
  49 #include <dt-bindings/clock/sun9i-a80-usb.h>
  50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
  51 #include <dt-bindings/reset/sun9i-a80-de.h>
  52 #include <dt-bindings/reset/sun9i-a80-usb.h>
  53
  54 / {
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57         interrupt-parent = <&gic>;
  58
  59         aliases {
  60                 ethernet0 = &gmac;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu0: cpu@0 {
  68                         compatible = "arm,cortex-a7";
  69                         device_type = "cpu";
  70                         cci-control-port = <&cci_control0>;
  71                         clock-frequency = <12000000>;
  72                         enable-method = "allwinner,sun9i-a80-smp";
  73                         reg = <0x0>;
  74                 };
  75
  76                 cpu1: cpu@1 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         cci-control-port = <&cci_control0>;
  80                         clock-frequency = <12000000>;
  81                         enable-method = "allwinner,sun9i-a80-smp";
  82                         reg = <0x1>;
  83                 };
  84
  85                 cpu2: cpu@2 {
  86                         compatible = "arm,cortex-a7";
  87                         device_type = "cpu";
  88                         cci-control-port = <&cci_control0>;
  89                         clock-frequency = <12000000>;
  90                         enable-method = "allwinner,sun9i-a80-smp";
  91                         reg = <0x2>;
  92                 };
  93
  94                 cpu3: cpu@3 {
  95                         compatible = "arm,cortex-a7";
  96                         device_type = "cpu";
  97                         cci-control-port = <&cci_control0>;
  98                         clock-frequency = <12000000>;
  99                         enable-method = "allwinner,sun9i-a80-smp";
 100                         reg = <0x3>;
 101                 };
 102
 103                 cpu4: cpu@100 {
 104                         compatible = "arm,cortex-a15";
 105                         device_type = "cpu";
 106                         cci-control-port = <&cci_control1>;
 107                         clock-frequency = <18000000>;
 108                         enable-method = "allwinner,sun9i-a80-smp";
 109                         reg = <0x100>;
 110                 };
 111
 112                 cpu5: cpu@101 {
 113                         compatible = "arm,cortex-a15";
 114                         device_type = "cpu";
 115                         cci-control-port = <&cci_control1>;
 116                         clock-frequency = <18000000>;
 117                         enable-method = "allwinner,sun9i-a80-smp";
 118                         reg = <0x101>;
 119                 };
 120
 121                 cpu6: cpu@102 {
 122                         compatible = "arm,cortex-a15";
 123                         device_type = "cpu";
 124                         cci-control-port = <&cci_control1>;
 125                         clock-frequency = <18000000>;
 126                         enable-method = "allwinner,sun9i-a80-smp";
 127                         reg = <0x102>;
 128                 };
 129
 130                 cpu7: cpu@103 {
 131                         compatible = "arm,cortex-a15";
 132                         device_type = "cpu";
 133                         cci-control-port = <&cci_control1>;
 134                         clock-frequency = <18000000>;
 135                         enable-method = "allwinner,sun9i-a80-smp";
 136                         reg = <0x103>;
 137                 };
 138         };
 139
 140         timer {
 141                 compatible = "arm,armv7-timer";
 142                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 143                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 144                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 145                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 146                 clock-frequency = <24000000>;
 147                 arm,cpu-registers-not-fw-configured;
 148         };
 149
 150         clocks {
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 /*
 154                  * map 64 bit address range down to 32 bits,
 155                  * as the peripherals are all under 512MB.
 156                  */
 157                 ranges = <0 0 0 0x20000000>;
 158
 159                 /*
 160                  * This clock is actually configurable from the PRCM address
 161                  * space. The external 24M oscillator can be turned off, and
 162                  * the clock switched to an internal 16M RC oscillator. Under
 163                  * normal operation there's no reason to do this, and the
 164                  * default is to use the external good one, so just model this
 165                  * as a fixed clock. Also it is not entirely clear if the
 166                  * osc24M mux in the PRCM affects the entire clock tree, which
 167                  * would also throw all the PLL clock rates off, or just the
 168                  * downstream clocks in the PRCM.
 169                  */
 170                 osc24M: clk-24M {
 171                         #clock-cells = <0>;
 172                         compatible = "fixed-clock";
 173                         clock-frequency = <24000000>;
 174                         clock-output-names = "osc24M";
 175                 };
 176
 177                 /*
 178                  * The 32k clock is from an external source, normally the
 179                  * AC100 codec/RTC chip. This serves as a placeholder for
 180                  * board dts files to specify the source.
 181                  */
 182                 osc32k: clk-32k {
 183                         #clock-cells = <0>;
 184                         compatible = "fixed-factor-clock";
 185                         clock-div = <1>;
 186                         clock-mult = <1>;
 187                         clock-output-names = "osc32k";
 188                 };
 189
 190                 /*
 191                  * The following two are dummy clocks, placeholders
 192                  * used in the gmac_tx clock. The gmac driver will
 193                  * choose one parent depending on the PHY interface
 194                  * mode, using clk_set_rate auto-reparenting.
 195                  *
 196                  * The actual TX clock rate is not controlled by the
 197                  * gmac_tx clock.
 198                  */
 199                 mii_phy_tx_clk: mii_phy_tx_clk {
 200                         #clock-cells = <0>;
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <25000000>;
 203                         clock-output-names = "mii_phy_tx";
 204                 };
 205
 206                 gmac_int_tx_clk: gmac_int_tx_clk {
 207                         #clock-cells = <0>;
 208                         compatible = "fixed-clock";
 209                         clock-frequency = <125000000>;
 210                         clock-output-names = "gmac_int_tx";
 211                 };
 212
 213                 gmac_tx_clk: clk@800030 {
 214                         #clock-cells = <0>;
 215                         compatible = "allwinner,sun7i-a20-gmac-clk";
 216                         reg = <0x00800030 0x4>;
 217                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 218                         clock-output-names = "gmac_tx";
 219                 };
 220
 221                 cpus_clk: clk@8001410 {
 222                         compatible = "allwinner,sun9i-a80-cpus-clk";
 223                         reg = <0x08001410 0x4>;
 224                         #clock-cells = <0>;
 225                         clocks = <&osc32k>, <&osc24M>,
 226                                  <&ccu CLK_PLL_PERIPH0>,
 227                                  <&ccu CLK_PLL_AUDIO>;
 228                         clock-output-names = "cpus";
 229                 };
 230
 231                 ahbs: clk-ahbs {
 232                         compatible = "fixed-factor-clock";
 233                         #clock-cells = <0>;
 234                         clock-div = <1>;
 235                         clock-mult = <1>;
 236                         clocks = <&cpus_clk>;
 237                         clock-output-names = "ahbs";
 238                 };
 239
 240                 apbs: clk@800141c {
 241                         compatible = "allwinner,sun8i-a23-apb0-clk";
 242                         reg = <0x0800141c 0x4>;
 243                         #clock-cells = <0>;
 244                         clocks = <&ahbs>;
 245                         clock-output-names = "apbs";
 246                 };
 247
 248                 apbs_gates: clk@8001428 {
 249                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 250                         reg = <0x08001428 0x4>;
 251                         #clock-cells = <1>;
 252                         clocks = <&apbs>;
 253                         clock-indices = <0>, <1>,
 254                                         <2>, <3>,
 255                                         <4>, <5>,
 256                                         <6>, <7>,
 257                                         <12>, <13>,
 258                                         <16>, <17>,
 259                                         <18>, <20>;
 260                         clock-output-names = "apbs_pio", "apbs_ir",
 261                                         "apbs_timer", "apbs_rsb",
 262                                         "apbs_uart", "apbs_1wire",
 263                                         "apbs_i2c0", "apbs_i2c1",
 264                                         "apbs_ps2_0", "apbs_ps2_1",
 265                                         "apbs_dma", "apbs_i2s0",
 266                                         "apbs_i2s1", "apbs_twd";
 267                 };
 268
 269                 r_1wire_clk: clk@8001450 {
 270                         reg = <0x08001450 0x4>;
 271                         #clock-cells = <0>;
 272                         compatible = "allwinner,sun4i-a10-mod0-clk";
 273                         clocks = <&osc32k>, <&osc24M>;
 274                         clock-output-names = "r_1wire";
 275                 };
 276
 277                 r_ir_clk: clk@8001454 {
 278                         reg = <0x08001454 0x4>;
 279                         #clock-cells = <0>;
 280                         compatible = "allwinner,sun4i-a10-mod0-clk";
 281                         clocks = <&osc32k>, <&osc24M>;
 282                         clock-output-names = "r_ir";
 283                 };
 284         };
 285
 286         de: display-engine {
 287                 compatible = "allwinner,sun9i-a80-display-engine";
 288                 allwinner,pipelines = <&fe0>, <&fe1>;
 289                 status = "disabled";
 290         };
 291
 292         soc@20000 {
 293                 compatible = "simple-bus";
 294                 #address-cells = <1>;
 295                 #size-cells = <1>;
 296                 /*
 297                  * map 64 bit address range down to 32 bits,
 298                  * as the peripherals are all under 512MB.
 299                  */
 300                 ranges = <0 0 0 0x20000000>;
 301
 302                 sram_b: sram@20000 {
 303                         /* 256 KiB secure SRAM at 0x20000 */
 304                         compatible = "mmio-sram";
 305                         reg = <0x00020000 0x40000>;
 306
 307                         #address-cells = <1>;
 308                         #size-cells = <1>;
 309                         ranges = <0 0x00020000 0x40000>;
 310
 311                         smp-sram@1000 {
 312                                 /*
 313                                  * This is checked by BROM to determine if
 314                                  * cpu0 should jump to SMP entry vector
 315                                  */
 316                                 compatible = "allwinner,sun9i-a80-smp-sram";
 317                                 reg = <0x1000 0x8>;
 318                         };
 319                 };
 320
 321                 gmac: ethernet@830000 {
 322                         compatible = "allwinner,sun7i-a20-gmac";
 323                         reg = <0x00830000 0x1054>;
 324                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 325                         interrupt-names = "macirq";
 326                         clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
 327                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 328                         resets = <&ccu RST_BUS_GMAC>;
 329                         reset-names = "stmmaceth";
 330                         snps,pbl = <2>;
 331                         snps,fixed-burst;
 332                         snps,force_sf_dma_mode;
 333                         status = "disabled";
 334
 335                         mdio: mdio {
 336                                 compatible = "snps,dwmac-mdio";
 337                                 #address-cells = <1>;
 338                                 #size-cells = <0>;
 339                         };
 340                 };
 341
 342                 ehci0: usb@a00000 {
 343                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 344                         reg = <0x00a00000 0x100>;
 345                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&usb_clocks CLK_BUS_HCI0>;
 347                         resets = <&usb_clocks RST_USB0_HCI>;
 348                         phys = <&usbphy1>;
 349                         status = "disabled";
 350                 };
 351
 352                 ohci0: usb@a00400 {
 353                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 354                         reg = <0x00a00400 0x100>;
 355                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 356                         clocks = <&usb_clocks CLK_BUS_HCI0>,
 357                                  <&usb_clocks CLK_USB_OHCI0>;
 358                         resets = <&usb_clocks RST_USB0_HCI>;
 359                         phys = <&usbphy1>;
 360                         status = "disabled";
 361                 };
 362
 363                 usbphy1: phy@a00800 {
 364                         compatible = "allwinner,sun9i-a80-usb-phy";
 365                         reg = <0x00a00800 0x4>;
 366                         clocks = <&usb_clocks CLK_USB0_PHY>;
 367                         clock-names = "phy";
 368                         resets = <&usb_clocks RST_USB0_PHY>;
 369                         reset-names = "phy";
 370                         status = "disabled";
 371                         #phy-cells = <0>;
 372                 };
 373
 374                 ehci1: usb@a01000 {
 375                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 376                         reg = <0x00a01000 0x100>;
 377                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&usb_clocks CLK_BUS_HCI1>;
 379                         resets = <&usb_clocks RST_USB1_HCI>;
 380                         phys = <&usbphy2>;
 381                         status = "disabled";
 382                 };
 383
 384                 usbphy2: phy@a01800 {
 385                         compatible = "allwinner,sun9i-a80-usb-phy";
 386                         reg = <0x00a01800 0x4>;
 387                         clocks = <&usb_clocks CLK_USB1_HSIC>,
 388                                  <&usb_clocks CLK_USB_HSIC>,
 389                                  <&usb_clocks CLK_USB1_PHY>;
 390                         clock-names = "hsic_480M",
 391                                       "hsic_12M",
 392                                       "phy";
 393                         resets = <&usb_clocks RST_USB1_HSIC>,
 394                                  <&usb_clocks RST_USB1_PHY>;
 395                         reset-names = "hsic",
 396                                       "phy";
 397                         status = "disabled";
 398                         #phy-cells = <0>;
 399                         /* usb1 is always used with HSIC */
 400                         phy_type = "hsic";
 401                 };
 402
 403                 ehci2: usb@a02000 {
 404                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 405                         reg = <0x00a02000 0x100>;
 406                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&usb_clocks CLK_BUS_HCI2>;
 408                         resets = <&usb_clocks RST_USB2_HCI>;
 409                         phys = <&usbphy3>;
 410                         status = "disabled";
 411                 };
 412
 413                 ohci2: usb@a02400 {
 414                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 415                         reg = <0x00a02400 0x100>;
 416                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&usb_clocks CLK_BUS_HCI2>,
 418                                  <&usb_clocks CLK_USB_OHCI2>;
 419                         resets = <&usb_clocks RST_USB2_HCI>;
 420                         phys = <&usbphy3>;
 421                         status = "disabled";
 422                 };
 423
 424                 usbphy3: phy@a02800 {
 425                         compatible = "allwinner,sun9i-a80-usb-phy";
 426                         reg = <0x00a02800 0x4>;
 427                         clocks = <&usb_clocks CLK_USB2_HSIC>,
 428                                  <&usb_clocks CLK_USB_HSIC>,
 429                                  <&usb_clocks CLK_USB2_PHY>;
 430                         clock-names = "hsic_480M",
 431                                       "hsic_12M",
 432                                       "phy";
 433                         resets = <&usb_clocks RST_USB2_HSIC>,
 434                                  <&usb_clocks RST_USB2_PHY>;
 435                         reset-names = "hsic",
 436                                       "phy";
 437                         status = "disabled";
 438                         #phy-cells = <0>;
 439                 };
 440
 441                 usb_clocks: clock@a08000 {
 442                         compatible = "allwinner,sun9i-a80-usb-clks";
 443                         reg = <0x00a08000 0x8>;
 444                         clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
 445                         clock-names = "bus", "hosc";
 446                         #clock-cells = <1>;
 447                         #reset-cells = <1>;
 448                 };
 449
 450                 cpucfg@1700000 {
 451                         compatible = "allwinner,sun9i-a80-cpucfg";
 452                         reg = <0x01700000 0x100>;
 453                 };
 454
 455                 mmc0: mmc@1c0f000 {
 456                         compatible = "allwinner,sun9i-a80-mmc";
 457                         reg = <0x01c0f000 0x1000>;
 458                         clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
 459                                  <&ccu CLK_MMC0_OUTPUT>,
 460                                  <&ccu CLK_MMC0_SAMPLE>;
 461                         clock-names = "ahb", "mmc", "output", "sample";
 462                         resets = <&mmc_config_clk 0>;
 463                         reset-names = "ahb";
 464                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 465                         status = "disabled";
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                 };
 469
 470                 mmc1: mmc@1c10000 {
 471                         compatible = "allwinner,sun9i-a80-mmc";
 472                         reg = <0x01c10000 0x1000>;
 473                         clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
 474                                  <&ccu CLK_MMC1_OUTPUT>,
 475                                  <&ccu CLK_MMC1_SAMPLE>;
 476                         clock-names = "ahb", "mmc", "output", "sample";
 477                         resets = <&mmc_config_clk 1>;
 478                         reset-names = "ahb";
 479                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 480                         status = "disabled";
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                 };
 484
 485                 mmc2: mmc@1c11000 {
 486                         compatible = "allwinner,sun9i-a80-mmc";
 487                         reg = <0x01c11000 0x1000>;
 488                         clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
 489                                  <&ccu CLK_MMC2_OUTPUT>,
 490                                  <&ccu CLK_MMC2_SAMPLE>;
 491                         clock-names = "ahb", "mmc", "output", "sample";
 492                         resets = <&mmc_config_clk 2>;
 493                         reset-names = "ahb";
 494                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 495                         status = "disabled";
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                 };
 499
 500                 mmc3: mmc@1c12000 {
 501                         compatible = "allwinner,sun9i-a80-mmc";
 502                         reg = <0x01c12000 0x1000>;
 503                         clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
 504                                  <&ccu CLK_MMC3_OUTPUT>,
 505                                  <&ccu CLK_MMC3_SAMPLE>;
 506                         clock-names = "ahb", "mmc", "output", "sample";
 507                         resets = <&mmc_config_clk 3>;
 508                         reset-names = "ahb";
 509                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 510                         status = "disabled";
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                 };
 514
 515                 mmc_config_clk: clk@1c13000 {
 516                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 517                         reg = <0x01c13000 0x10>;
 518                         clocks = <&ccu CLK_BUS_MMC>;
 519                         clock-names = "ahb";
 520                         resets = <&ccu RST_BUS_MMC>;
 521                         reset-names = "ahb";
 522                         #clock-cells = <1>;
 523                         #reset-cells = <1>;
 524                         clock-output-names = "mmc0_config", "mmc1_config",
 525                                              "mmc2_config", "mmc3_config";
 526                 };
 527
 528                 gic: interrupt-controller@1c41000 {
 529                         compatible = "arm,gic-400";
 530                         reg = <0x01c41000 0x1000>,
 531                               <0x01c42000 0x2000>,
 532                               <0x01c44000 0x2000>,
 533                               <0x01c46000 0x2000>;
 534                         interrupt-controller;
 535                         #interrupt-cells = <3>;
 536                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 537                 };
 538
 539                 cci: cci@1c90000 {
 540                         compatible = "arm,cci-400";
 541                         #address-cells = <1>;
 542                         #size-cells = <1>;
 543                         reg = <0x01c90000 0x1000>;
 544                         ranges = <0x0 0x01c90000 0x10000>;
 545
 546                         cci_control0: slave-if@4000 {
 547                                 compatible = "arm,cci-400-ctrl-if";
 548                                 interface-type = "ace";
 549                                 reg = <0x4000 0x1000>;
 550                         };
 551
 552                         cci_control1: slave-if@5000 {
 553                                 compatible = "arm,cci-400-ctrl-if";
 554                                 interface-type = "ace";
 555                                 reg = <0x5000 0x1000>;
 556                         };
 557
 558                         pmu@9000 {
 559                                  compatible = "arm,cci-400-pmu,r1";
 560                                  reg = <0x9000 0x5000>;
 561                                  interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 562                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 563                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 564                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 565                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 566                         };
 567                 };
 568
 569                 de_clocks: clock@3000000 {
 570                         compatible = "allwinner,sun9i-a80-de-clks";
 571                         reg = <0x03000000 0x30>;
 572                         clocks = <&ccu CLK_DE>,
 573                                  <&ccu CLK_SDRAM>,
 574                                  <&ccu CLK_BUS_DE>;
 575                         clock-names = "mod",
 576                                       "dram",
 577                                       "bus";
 578                         resets = <&ccu RST_BUS_DE>;
 579                         #clock-cells = <1>;
 580                         #reset-cells = <1>;
 581                 };
 582
 583                 fe0: display-frontend@3100000 {
 584                         compatible = "allwinner,sun9i-a80-display-frontend";
 585                         reg = <0x03100000 0x40000>;
 586                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
 588                                  <&de_clocks CLK_DRAM_FE0>;
 589                         clock-names = "ahb", "mod",
 590                                       "ram";
 591                         resets = <&de_clocks RST_FE0>;
 592
 593                         ports {
 594                                 #address-cells = <1>;
 595                                 #size-cells = <0>;
 596
 597                                 fe0_out: port@1 {
 598                                         reg = <1>;
 599
 600                                         fe0_out_deu0: endpoint {
 601                                                 remote-endpoint = <&deu0_in_fe0>;
 602                                         };
 603                                 };
 604                         };
 605                 };
 606
 607                 fe1: display-frontend@3140000 {
 608                         compatible = "allwinner,sun9i-a80-display-frontend";
 609                         reg = <0x03140000 0x40000>;
 610                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
 612                                  <&de_clocks CLK_DRAM_FE1>;
 613                         clock-names = "ahb", "mod",
 614                                       "ram";
 615                         resets = <&de_clocks RST_FE0>;
 616
 617                         ports {
 618                                 #address-cells = <1>;
 619                                 #size-cells = <0>;
 620
 621                                 fe1_out: port@1 {
 622                                         reg = <1>;
 623
 624                                         fe1_out_deu1: endpoint {
 625                                                 remote-endpoint = <&deu1_in_fe1>;
 626                                         };
 627                                 };
 628                         };
 629                 };
 630
 631                 be0: display-backend@3200000 {
 632                         compatible = "allwinner,sun9i-a80-display-backend";
 633                         reg = <0x03200000 0x40000>;
 634                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 635                         clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
 636                                  <&de_clocks CLK_DRAM_BE0>;
 637                         clock-names = "ahb", "mod",
 638                                       "ram";
 639                         resets = <&de_clocks RST_BE0>;
 640
 641                         ports {
 642                                 #address-cells = <1>;
 643                                 #size-cells = <0>;
 644
 645                                 be0_in: port@0 {
 646                                         #address-cells = <1>;
 647                                         #size-cells = <0>;
 648                                         reg = <0>;
 649
 650                                         be0_in_deu0: endpoint@0 {
 651                                                 reg = <0>;
 652                                                 remote-endpoint = <&deu0_out_be0>;
 653                                         };
 654
 655                                         be0_in_deu1: endpoint@1 {
 656                                                 reg = <1>;
 657                                                 remote-endpoint = <&deu1_out_be0>;
 658                                         };
 659                                 };
 660
 661                                 be0_out: port@1 {
 662                                         reg = <1>;
 663
 664                                         be0_out_drc0: endpoint {
 665                                                 remote-endpoint = <&drc0_in_be0>;
 666                                         };
 667                                 };
 668                         };
 669                 };
 670
 671                 be1: display-backend@3240000 {
 672                         compatible = "allwinner,sun9i-a80-display-backend";
 673                         reg = <0x03240000 0x40000>;
 674                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 675                         clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
 676                                  <&de_clocks CLK_DRAM_BE1>;
 677                         clock-names = "ahb", "mod",
 678                                       "ram";
 679                         resets = <&de_clocks RST_BE1>;
 680
 681                         ports {
 682                                 #address-cells = <1>;
 683                                 #size-cells = <0>;
 684
 685                                 be1_in: port@0 {
 686                                         #address-cells = <1>;
 687                                         #size-cells = <0>;
 688                                         reg = <0>;
 689
 690                                         be1_in_deu0: endpoint@0 {
 691                                                 reg = <0>;
 692                                                 remote-endpoint = <&deu0_out_be1>;
 693                                         };
 694
 695                                         be1_in_deu1: endpoint@1 {
 696                                                 reg = <1>;
 697                                                 remote-endpoint = <&deu1_out_be1>;
 698                                         };
 699                                 };
 700
 701                                 be1_out: port@1 {
 702                                         reg = <1>;
 703
 704                                         be1_out_drc1: endpoint {
 705                                                 remote-endpoint = <&drc1_in_be1>;
 706                                         };
 707                                 };
 708                         };
 709                 };
 710
 711                 deu0: deu@3300000 {
 712                         compatible = "allwinner,sun9i-a80-deu";
 713                         reg = <0x03300000 0x40000>;
 714                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 715                         clocks = <&de_clocks CLK_BUS_DEU0>,
 716                                  <&de_clocks CLK_IEP_DEU0>,
 717                                  <&de_clocks CLK_DRAM_DEU0>;
 718                         clock-names = "ahb",
 719                                       "mod",
 720                                       "ram";
 721                         resets = <&de_clocks RST_DEU0>;
 722
 723                         ports {
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726
 727                                 deu0_in: port@0 {
 728                                         reg = <0>;
 729
 730                                         deu0_in_fe0: endpoint {
 731                                                 remote-endpoint = <&fe0_out_deu0>;
 732                                         };
 733                                 };
 734
 735                                 deu0_out: port@1 {
 736                                         #address-cells = <1>;
 737                                         #size-cells = <0>;
 738                                         reg = <1>;
 739
 740                                         deu0_out_be0: endpoint@0 {
 741                                                 reg = <0>;
 742                                                 remote-endpoint = <&be0_in_deu0>;
 743                                         };
 744
 745                                         deu0_out_be1: endpoint@1 {
 746                                                 reg = <1>;
 747                                                 remote-endpoint = <&be1_in_deu0>;
 748                                         };
 749                                 };
 750                         };
 751                 };
 752
 753                 deu1: deu@3340000 {
 754                         compatible = "allwinner,sun9i-a80-deu";
 755                         reg = <0x03340000 0x40000>;
 756                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&de_clocks CLK_BUS_DEU1>,
 758                                  <&de_clocks CLK_IEP_DEU1>,
 759                                  <&de_clocks CLK_DRAM_DEU1>;
 760                         clock-names = "ahb",
 761                                       "mod",
 762                                       "ram";
 763                         resets = <&de_clocks RST_DEU1>;
 764
 765                         ports {
 766                                 #address-cells = <1>;
 767                                 #size-cells = <0>;
 768
 769                                 deu1_in: port@0 {
 770                                         reg = <0>;
 771
 772                                         deu1_in_fe1: endpoint {
 773                                                 remote-endpoint = <&fe1_out_deu1>;
 774                                         };
 775                                 };
 776
 777                                 deu1_out: port@1 {
 778                                         #address-cells = <1>;
 779                                         #size-cells = <0>;
 780                                         reg = <1>;
 781
 782                                         deu1_out_be0: endpoint@0 {
 783                                                 reg = <0>;
 784                                                 remote-endpoint = <&be0_in_deu1>;
 785                                         };
 786
 787                                         deu1_out_be1: endpoint@1 {
 788                                                 reg = <1>;
 789                                                 remote-endpoint = <&be1_in_deu1>;
 790                                         };
 791                                 };
 792                         };
 793                 };
 794
 795                 drc0: drc@3400000 {
 796                         compatible = "allwinner,sun9i-a80-drc";
 797                         reg = <0x03400000 0x40000>;
 798                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 799                         clocks = <&de_clocks CLK_BUS_DRC0>,
 800                                  <&de_clocks CLK_IEP_DRC0>,
 801                                  <&de_clocks CLK_DRAM_DRC0>;
 802                         clock-names = "ahb",
 803                                       "mod",
 804                                       "ram";
 805                         resets = <&de_clocks RST_DRC0>;
 806
 807                         ports {
 808                                 #address-cells = <1>;
 809                                 #size-cells = <0>;
 810
 811                                 drc0_in: port@0 {
 812                                         reg = <0>;
 813
 814                                         drc0_in_be0: endpoint {
 815                                                 remote-endpoint = <&be0_out_drc0>;
 816                                         };
 817                                 };
 818
 819                                 drc0_out: port@1 {
 820                                         reg = <1>;
 821
 822                                         drc0_out_tcon0: endpoint {
 823                                                 remote-endpoint = <&tcon0_in_drc0>;
 824                                         };
 825                                 };
 826                         };
 827                 };
 828
 829                 drc1: drc@3440000 {
 830                         compatible = "allwinner,sun9i-a80-drc";
 831                         reg = <0x03440000 0x40000>;
 832                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 833                         clocks = <&de_clocks CLK_BUS_DRC1>,
 834                                  <&de_clocks CLK_IEP_DRC1>,
 835                                  <&de_clocks CLK_DRAM_DRC1>;
 836                         clock-names = "ahb",
 837                                       "mod",
 838                                       "ram";
 839                         resets = <&de_clocks RST_DRC1>;
 840
 841                         ports {
 842                                 #address-cells = <1>;
 843                                 #size-cells = <0>;
 844
 845                                 drc1_in: port@0 {
 846                                         reg = <0>;
 847
 848                                         drc1_in_be1: endpoint {
 849                                                 remote-endpoint = <&be1_out_drc1>;
 850                                         };
 851                                 };
 852
 853                                 drc1_out: port@1 {
 854                                         reg = <1>;
 855
 856                                         drc1_out_tcon1: endpoint {
 857                                                 remote-endpoint = <&tcon1_in_drc1>;
 858                                         };
 859                                 };
 860                         };
 861                 };
 862
 863                 tcon0: lcd-controller@3c00000 {
 864                         compatible = "allwinner,sun9i-a80-tcon-lcd";
 865                         reg = <0x03c00000 0x10000>;
 866                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 867                         clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
 868                         clock-names = "ahb", "tcon-ch0";
 869                         resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
 870                         reset-names = "lcd", "edp";
 871                         clock-output-names = "tcon0-pixel-clock";
 872                         #clock-cells = <0>;
 873
 874                         ports {
 875                                 #address-cells = <1>;
 876                                 #size-cells = <0>;
 877
 878                                 tcon0_in: port@0 {
 879                                         reg = <0>;
 880
 881                                         tcon0_in_drc0: endpoint {
 882                                                 remote-endpoint = <&drc0_out_tcon0>;
 883                                         };
 884                                 };
 885
 886                                 tcon0_out: port@1 {
 887                                         reg = <1>;
 888                                 };
 889                         };
 890                 };
 891
 892                 tcon1: lcd-controller@3c10000 {
 893                         compatible = "allwinner,sun9i-a80-tcon-tv";
 894                         reg = <0x03c10000 0x10000>;
 895                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
 897                         clock-names = "ahb", "tcon-ch1";
 898                         resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
 899                         reset-names = "lcd", "edp";
 900
 901                         ports {
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904
 905                                 tcon1_in: port@0 {
 906                                         reg = <0>;
 907
 908                                         tcon1_in_drc1: endpoint {
 909                                                 remote-endpoint = <&drc1_out_tcon1>;
 910                                         };
 911                                 };
 912
 913                                 tcon1_out: port@1 {
 914                                         reg = <1>;
 915                                 };
 916                         };
 917                 };
 918
 919                 ccu: clock@6000000 {
 920                         compatible = "allwinner,sun9i-a80-ccu";
 921                         reg = <0x06000000 0x800>;
 922                         clocks = <&osc24M>, <&osc32k>;
 923                         clock-names = "hosc", "losc";
 924                         #clock-cells = <1>;
 925                         #reset-cells = <1>;
 926                 };
 927
 928                 timer@6000c00 {
 929                         compatible = "allwinner,sun4i-a10-timer";
 930                         reg = <0x06000c00 0xa0>;
 931                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 933                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 934                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 936                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 937
 938                         clocks = <&osc24M>;
 939                 };
 940
 941                 wdt: watchdog@6000ca0 {
 942                         compatible = "allwinner,sun6i-a31-wdt";
 943                         reg = <0x06000ca0 0x20>;
 944                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 945                 };
 946
 947                 pio: pinctrl@6000800 {
 948                         compatible = "allwinner,sun9i-a80-pinctrl";
 949                         reg = <0x06000800 0x400>;
 950                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 951                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 952                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 953                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 954                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 955                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 956                         clock-names = "apb", "hosc", "losc";
 957                         gpio-controller;
 958                         interrupt-controller;
 959                         #interrupt-cells = <3>;
 960                         #gpio-cells = <3>;
 961
 962                         gmac_rgmii_pins: gmac-rgmii-pins {
 963                                 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
 964                                        "PA7", "PA8", "PA9", "PA10", "PA12",
 965                                        "PA13", "PA15", "PA16", "PA17";
 966                                 function = "gmac";
 967                                 /*
 968                                  * data lines in RGMII mode use DDR mode
 969                                  * and need a higher signal drive strength
 970                                  */
 971                                 drive-strength = <40>;
 972                         };
 973
 974                         i2c3_pins: i2c3-pins {
 975                                 pins = "PG10", "PG11";
 976                                 function = "i2c3";
 977                         };
 978
 979                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 980                                 pins = "PD0", "PD1", "PD2", "PD3",
 981                                        "PD4", "PD5", "PD6", "PD7",
 982                                        "PD8", "PD9", "PD10", "PD11",
 983                                        "PD12", "PD13", "PD14", "PD15",
 984                                        "PD16", "PD17", "PD18", "PD19",
 985                                        "PD20", "PD21", "PD22", "PD23",
 986                                        "PD24", "PD25", "PD26", "PD27";
 987                                 function = "lcd0";
 988                         };
 989
 990                         mmc0_pins: mmc0-pins {
 991                                 pins = "PF0", "PF1" ,"PF2", "PF3",
 992                                        "PF4", "PF5";
 993                                 function = "mmc0";
 994                                 drive-strength = <30>;
 995                                 bias-pull-up;
 996                         };
 997
 998                         mmc1_pins: mmc1-pins {
 999                                 pins = "PG0", "PG1" ,"PG2", "PG3",
1000                                                  "PG4", "PG5";
1001                                 function = "mmc1";
1002                                 drive-strength = <30>;
1003                                 bias-pull-up;
1004                         };
1005
1006                         mmc2_8bit_pins: mmc2-8bit-pins {
1007                                 pins = "PC6", "PC7", "PC8", "PC9",
1008                                        "PC10", "PC11", "PC12",
1009                                        "PC13", "PC14", "PC15",
1010                                        "PC16";
1011                                 function = "mmc2";
1012                                 drive-strength = <30>;
1013                                 bias-pull-up;
1014                         };
1015
1016                         uart0_ph_pins: uart0-ph-pins {
1017                                 pins = "PH12", "PH13";
1018                                 function = "uart0";
1019                         };
1020
1021                         uart4_pins: uart4-pins {
1022                                 pins = "PG12", "PG13", "PG14", "PG15";
1023                                 function = "uart4";
1024                         };
1025                 };
1026
1027                 uart0: serial@7000000 {
1028                         compatible = "snps,dw-apb-uart";
1029                         reg = <0x07000000 0x400>;
1030                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1031                         reg-shift = <2>;
1032                         reg-io-width = <4>;
1033                         clocks = <&ccu CLK_BUS_UART0>;
1034                         resets = <&ccu RST_BUS_UART0>;
1035                         status = "disabled";
1036                 };
1037
1038                 uart1: serial@7000400 {
1039                         compatible = "snps,dw-apb-uart";
1040                         reg = <0x07000400 0x400>;
1041                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1042                         reg-shift = <2>;
1043                         reg-io-width = <4>;
1044                         clocks = <&ccu CLK_BUS_UART1>;
1045                         resets = <&ccu RST_BUS_UART1>;
1046                         status = "disabled";
1047                 };
1048
1049                 uart2: serial@7000800 {
1050                         compatible = "snps,dw-apb-uart";
1051                         reg = <0x07000800 0x400>;
1052                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1053                         reg-shift = <2>;
1054                         reg-io-width = <4>;
1055                         clocks = <&ccu CLK_BUS_UART2>;
1056                         resets = <&ccu RST_BUS_UART2>;
1057                         status = "disabled";
1058                 };
1059
1060                 uart3: serial@7000c00 {
1061                         compatible = "snps,dw-apb-uart";
1062                         reg = <0x07000c00 0x400>;
1063                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1064                         reg-shift = <2>;
1065                         reg-io-width = <4>;
1066                         clocks = <&ccu CLK_BUS_UART3>;
1067                         resets = <&ccu RST_BUS_UART3>;
1068                         status = "disabled";
1069                 };
1070
1071                 uart4: serial@7001000 {
1072                         compatible = "snps,dw-apb-uart";
1073                         reg = <0x07001000 0x400>;
1074                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1075                         reg-shift = <2>;
1076                         reg-io-width = <4>;
1077                         clocks = <&ccu CLK_BUS_UART4>;
1078                         resets = <&ccu RST_BUS_UART4>;
1079                         status = "disabled";
1080                 };
1081
1082                 uart5: serial@7001400 {
1083                         compatible = "snps,dw-apb-uart";
1084                         reg = <0x07001400 0x400>;
1085                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1086                         reg-shift = <2>;
1087                         reg-io-width = <4>;
1088                         clocks = <&ccu CLK_BUS_UART5>;
1089                         resets = <&ccu RST_BUS_UART5>;
1090                         status = "disabled";
1091                 };
1092
1093                 i2c0: i2c@7002800 {
1094                         compatible = "allwinner,sun6i-a31-i2c";
1095                         reg = <0x07002800 0x400>;
1096                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1097                         clocks = <&ccu CLK_BUS_I2C0>;
1098                         resets = <&ccu RST_BUS_I2C0>;
1099                         status = "disabled";
1100                         #address-cells = <1>;
1101                         #size-cells = <0>;
1102                 };
1103
1104                 i2c1: i2c@7002c00 {
1105                         compatible = "allwinner,sun6i-a31-i2c";
1106                         reg = <0x07002c00 0x400>;
1107                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1108                         clocks = <&ccu CLK_BUS_I2C1>;
1109                         resets = <&ccu RST_BUS_I2C1>;
1110                         status = "disabled";
1111                         #address-cells = <1>;
1112                         #size-cells = <0>;
1113                 };
1114
1115                 i2c2: i2c@7003000 {
1116                         compatible = "allwinner,sun6i-a31-i2c";
1117                         reg = <0x07003000 0x400>;
1118                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1119                         clocks = <&ccu CLK_BUS_I2C2>;
1120                         resets = <&ccu RST_BUS_I2C2>;
1121                         status = "disabled";
1122                         #address-cells = <1>;
1123                         #size-cells = <0>;
1124                 };
1125
1126                 i2c3: i2c@7003400 {
1127                         compatible = "allwinner,sun6i-a31-i2c";
1128                         reg = <0x07003400 0x400>;
1129                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1130                         clocks = <&ccu CLK_BUS_I2C3>;
1131                         resets = <&ccu RST_BUS_I2C3>;
1132                         status = "disabled";
1133                         #address-cells = <1>;
1134                         #size-cells = <0>;
1135                 };
1136
1137                 i2c4: i2c@7003800 {
1138                         compatible = "allwinner,sun6i-a31-i2c";
1139                         reg = <0x07003800 0x400>;
1140                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1141                         clocks = <&ccu CLK_BUS_I2C4>;
1142                         resets = <&ccu RST_BUS_I2C4>;
1143                         status = "disabled";
1144                         #address-cells = <1>;
1145                         #size-cells = <0>;
1146                 };
1147
1148                 r_wdt: watchdog@8001000 {
1149                         compatible = "allwinner,sun6i-a31-wdt";
1150                         reg = <0x08001000 0x20>;
1151                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1152                 };
1153
1154                 prcm@8001400 {
1155                         compatible = "allwinner,sun9i-a80-prcm";
1156                         reg = <0x08001400 0x200>;
1157                 };
1158
1159                 apbs_rst: reset@80014b0 {
1160                         reg = <0x080014b0 0x4>;
1161                         compatible = "allwinner,sun6i-a31-clock-reset";
1162                         #reset-cells = <1>;
1163                 };
1164
1165                 nmi_intc: interrupt-controller@80015a0 {
1166                         compatible = "allwinner,sun9i-a80-nmi";
1167                         interrupt-controller;
1168                         #interrupt-cells = <2>;
1169                         reg = <0x080015a0 0xc>;
1170                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1171                 };
1172
1173                 r_ir: ir@8002000 {
1174                         compatible = "allwinner,sun6i-a31-ir";
1175                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1176                         pinctrl-names = "default";
1177                         pinctrl-0 = <&r_ir_pins>;
1178                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
1179                         clock-names = "apb", "ir";
1180                         resets = <&apbs_rst 1>;
1181                         reg = <0x08002000 0x40>;
1182                         status = "disabled";
1183                 };
1184
1185                 r_uart: serial@8002800 {
1186                         compatible = "snps,dw-apb-uart";
1187                         reg = <0x08002800 0x400>;
1188                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1189                         reg-shift = <2>;
1190                         reg-io-width = <4>;
1191                         clocks = <&apbs_gates 4>;
1192                         resets = <&apbs_rst 4>;
1193                         status = "disabled";
1194                 };
1195
1196                 r_pio: pinctrl@8002c00 {
1197                         compatible = "allwinner,sun9i-a80-r-pinctrl";
1198                         reg = <0x08002c00 0x400>;
1199                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1201                         clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1202                         clock-names = "apb", "hosc", "losc";
1203                         resets = <&apbs_rst 0>;
1204                         gpio-controller;
1205                         interrupt-controller;
1206                         #interrupt-cells = <3>;
1207                         #gpio-cells = <3>;
1208
1209                         r_ir_pins: r-ir-pins {
1210                                 pins = "PL6";
1211                                 function = "s_cir_rx";
1212                         };
1213
1214                         r_rsb_pins: r-rsb-pins {
1215                                 pins = "PN0", "PN1";
1216                                 function = "s_rsb";
1217                                 drive-strength = <20>;
1218                                 bias-pull-up;
1219                         };
1220                 };
1221
1222                 r_rsb: rsb@8003400 {
1223                         compatible = "allwinner,sun8i-a23-rsb";
1224                         reg = <0x08003400 0x400>;
1225                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1226                         clocks = <&apbs_gates 3>;
1227                         clock-frequency = <3000000>;
1228                         resets = <&apbs_rst 3>;
1229                         pinctrl-names = "default";
1230                         pinctrl-0 = <&r_rsb_pins>;
1231                         status = "disabled";
1232                         #address-cells = <1>;
1233                         #size-cells = <0>;
1234                 };
1235         };
1236 };