arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
  48 #include <dt-bindings/clock/sun9i-a80-de.h>
  49 #include <dt-bindings/clock/sun9i-a80-usb.h>
  50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
  51 #include <dt-bindings/reset/sun9i-a80-de.h>
  52 #include <dt-bindings/reset/sun9i-a80-usb.h>
  53
  54 / {
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57         interrupt-parent = <&gic>;
  58
  59         aliases {
  60                 ethernet0 = &gmac;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu0: cpu@0 {
  68                         compatible = "arm,cortex-a7";
  69                         device_type = "cpu";
  70                         cci-control-port = <&cci_control0>;
  71                         clock-frequency = <12000000>;
  72                         enable-method = "allwinner,sun9i-a80-smp";
  73                         reg = <0x0>;
  74                 };
  75
  76                 cpu1: cpu@1 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         cci-control-port = <&cci_control0>;
  80                         clock-frequency = <12000000>;
  81                         enable-method = "allwinner,sun9i-a80-smp";
  82                         reg = <0x1>;
  83                 };
  84
  85                 cpu2: cpu@2 {
  86                         compatible = "arm,cortex-a7";
  87                         device_type = "cpu";
  88                         cci-control-port = <&cci_control0>;
  89                         clock-frequency = <12000000>;
  90                         enable-method = "allwinner,sun9i-a80-smp";
  91                         reg = <0x2>;
  92                 };
  93
  94                 cpu3: cpu@3 {
  95                         compatible = "arm,cortex-a7";
  96                         device_type = "cpu";
  97                         cci-control-port = <&cci_control0>;
  98                         clock-frequency = <12000000>;
  99                         enable-method = "allwinner,sun9i-a80-smp";
 100                         reg = <0x3>;
 101                 };
 102
 103                 cpu4: cpu@100 {
 104                         compatible = "arm,cortex-a15";
 105                         device_type = "cpu";
 106                         cci-control-port = <&cci_control1>;
 107                         clock-frequency = <18000000>;
 108                         enable-method = "allwinner,sun9i-a80-smp";
 109                         reg = <0x100>;
 110                 };
 111
 112                 cpu5: cpu@101 {
 113                         compatible = "arm,cortex-a15";
 114                         device_type = "cpu";
 115                         cci-control-port = <&cci_control1>;
 116                         clock-frequency = <18000000>;
 117                         enable-method = "allwinner,sun9i-a80-smp";
 118                         reg = <0x101>;
 119                 };
 120
 121                 cpu6: cpu@102 {
 122                         compatible = "arm,cortex-a15";
 123                         device_type = "cpu";
 124                         cci-control-port = <&cci_control1>;
 125                         clock-frequency = <18000000>;
 126                         enable-method = "allwinner,sun9i-a80-smp";
 127                         reg = <0x102>;
 128                 };
 129
 130                 cpu7: cpu@103 {
 131                         compatible = "arm,cortex-a15";
 132                         device_type = "cpu";
 133                         cci-control-port = <&cci_control1>;
 134                         clock-frequency = <18000000>;
 135                         enable-method = "allwinner,sun9i-a80-smp";
 136                         reg = <0x103>;
 137                 };
 138         };
 139
 140         timer {
 141                 compatible = "arm,armv7-timer";
 142                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 143                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 144                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 145                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 146                 clock-frequency = <24000000>;
 147                 arm,cpu-registers-not-fw-configured;
 148         };
 149
 150         clocks {
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 /*
 154                  * map 64 bit address range down to 32 bits,
 155                  * as the peripherals are all under 512MB.
 156                  */
 157                 ranges = <0 0 0 0x20000000>;
 158
 159                 /*
 160                  * This clock is actually configurable from the PRCM address
 161                  * space. The external 24M oscillator can be turned off, and
 162                  * the clock switched to an internal 16M RC oscillator. Under
 163                  * normal operation there's no reason to do this, and the
 164                  * default is to use the external good one, so just model this
 165                  * as a fixed clock. Also it is not entirely clear if the
 166                  * osc24M mux in the PRCM affects the entire clock tree, which
 167                  * would also throw all the PLL clock rates off, or just the
 168                  * downstream clocks in the PRCM.
 169                  */
 170                 osc24M: clk-24M {
 171                         #clock-cells = <0>;
 172                         compatible = "fixed-clock";
 173                         clock-frequency = <24000000>;
 174                         clock-output-names = "osc24M";
 175                 };
 176
 177                 /*
 178                  * The 32k clock is from an external source, normally the
 179                  * AC100 codec/RTC chip. This serves as a placeholder for
 180                  * board dts files to specify the source.
 181                  */
 182                 osc32k: clk-32k {
 183                         #clock-cells = <0>;
 184                         compatible = "fixed-factor-clock";
 185                         clock-div = <1>;
 186                         clock-mult = <1>;
 187                         clock-output-names = "osc32k";
 188                 };
 189
 190                 /*
 191                  * The following two are dummy clocks, placeholders
 192                  * used in the gmac_tx clock. The gmac driver will
 193                  * choose one parent depending on the PHY interface
 194                  * mode, using clk_set_rate auto-reparenting.
 195                  *
 196                  * The actual TX clock rate is not controlled by the
 197                  * gmac_tx clock.
 198                  */
 199                 mii_phy_tx_clk: mii_phy_tx_clk {
 200                         #clock-cells = <0>;
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <25000000>;
 203                         clock-output-names = "mii_phy_tx";
 204                 };
 205
 206                 gmac_int_tx_clk: gmac_int_tx_clk {
 207                         #clock-cells = <0>;
 208                         compatible = "fixed-clock";
 209                         clock-frequency = <125000000>;
 210                         clock-output-names = "gmac_int_tx";
 211                 };
 212
 213                 gmac_tx_clk: clk@800030 {
 214                         #clock-cells = <0>;
 215                         compatible = "allwinner,sun7i-a20-gmac-clk";
 216                         reg = <0x00800030 0x4>;
 217                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 218                         clock-output-names = "gmac_tx";
 219                 };
 220
 221                 cpus_clk: clk@8001410 {
 222                         compatible = "allwinner,sun9i-a80-cpus-clk";
 223                         reg = <0x08001410 0x4>;
 224                         #clock-cells = <0>;
 225                         clocks = <&osc32k>, <&osc24M>,
 226                                  <&ccu CLK_PLL_PERIPH0>,
 227                                  <&ccu CLK_PLL_AUDIO>;
 228                         clock-output-names = "cpus";
 229                 };
 230
 231                 ahbs: clk-ahbs {
 232                         compatible = "fixed-factor-clock";
 233                         #clock-cells = <0>;
 234                         clock-div = <1>;
 235                         clock-mult = <1>;
 236                         clocks = <&cpus_clk>;
 237                         clock-output-names = "ahbs";
 238                 };
 239
 240                 apbs: clk@800141c {
 241                         compatible = "allwinner,sun8i-a23-apb0-clk";
 242                         reg = <0x0800141c 0x4>;
 243                         #clock-cells = <0>;
 244                         clocks = <&ahbs>;
 245                         clock-output-names = "apbs";
 246                 };
 247
 248                 apbs_gates: clk@8001428 {
 249                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 250                         reg = <0x08001428 0x4>;
 251                         #clock-cells = <1>;
 252                         clocks = <&apbs>;
 253                         clock-indices = <0>, <1>,
 254                                         <2>, <3>,
 255                                         <4>, <5>,
 256                                         <6>, <7>,
 257                                         <12>, <13>,
 258                                         <16>, <17>,
 259                                         <18>, <20>;
 260                         clock-output-names = "apbs_pio", "apbs_ir",
 261                                         "apbs_timer", "apbs_rsb",
 262                                         "apbs_uart", "apbs_1wire",
 263                                         "apbs_i2c0", "apbs_i2c1",
 264                                         "apbs_ps2_0", "apbs_ps2_1",
 265                                         "apbs_dma", "apbs_i2s0",
 266                                         "apbs_i2s1", "apbs_twd";
 267                 };
 268
 269                 r_1wire_clk: clk@8001450 {
 270                         reg = <0x08001450 0x4>;
 271                         #clock-cells = <0>;
 272                         compatible = "allwinner,sun4i-a10-mod0-clk";
 273                         clocks = <&osc32k>, <&osc24M>;
 274                         clock-output-names = "r_1wire";
 275                 };
 276
 277                 r_ir_clk: clk@8001454 {
 278                         reg = <0x08001454 0x4>;
 279                         #clock-cells = <0>;
 280                         compatible = "allwinner,sun4i-a10-mod0-clk";
 281                         clocks = <&osc32k>, <&osc24M>;
 282                         clock-output-names = "r_ir";
 283                 };
 284         };
 285
 286         de: display-engine {
 287                 compatible = "allwinner,sun9i-a80-display-engine";
 288                 allwinner,pipelines = <&fe0>, <&fe1>;
 289                 status = "disabled";
 290         };
 291
 292         soc@20000 {
 293                 compatible = "simple-bus";
 294                 #address-cells = <1>;
 295                 #size-cells = <1>;
 296                 /*
 297                  * map 64 bit address range down to 32 bits,
 298                  * as the peripherals are all under 512MB.
 299                  */
 300                 ranges = <0 0 0 0x20000000>;
 301
 302                 sram_b: sram@20000 {
 303                         /* 256 KiB secure SRAM at 0x20000 */
 304                         compatible = "mmio-sram";
 305                         reg = <0x00020000 0x40000>;
 306
 307                         #address-cells = <1>;
 308                         #size-cells = <1>;
 309                         ranges = <0 0x00020000 0x40000>;
 310
 311                         smp-sram@1000 {
 312                                 /*
 313                                  * This is checked by BROM to determine if
 314                                  * cpu0 should jump to SMP entry vector
 315                                  */
 316                                 compatible = "allwinner,sun9i-a80-smp-sram";
 317                                 reg = <0x1000 0x8>;
 318                         };
 319                 };
 320
 321                 gmac: ethernet@830000 {
 322                         compatible = "allwinner,sun7i-a20-gmac";
 323                         reg = <0x00830000 0x1054>;
 324                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 325                         interrupt-names = "macirq";
 326                         clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
 327                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 328                         resets = <&ccu RST_BUS_GMAC>;
 329                         reset-names = "stmmaceth";
 330                         snps,pbl = <2>;
 331                         snps,fixed-burst;
 332                         snps,force_sf_dma_mode;
 333                         status = "disabled";
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                 };
 337
 338                 ehci0: usb@a00000 {
 339                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 340                         reg = <0x00a00000 0x100>;
 341                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&usb_clocks CLK_BUS_HCI0>;
 343                         resets = <&usb_clocks RST_USB0_HCI>;
 344                         phys = <&usbphy1>;
 345                         status = "disabled";
 346                 };
 347
 348                 ohci0: usb@a00400 {
 349                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 350                         reg = <0x00a00400 0x100>;
 351                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 352                         clocks = <&usb_clocks CLK_BUS_HCI0>,
 353                                  <&usb_clocks CLK_USB_OHCI0>;
 354                         resets = <&usb_clocks RST_USB0_HCI>;
 355                         phys = <&usbphy1>;
 356                         status = "disabled";
 357                 };
 358
 359                 usbphy1: phy@a00800 {
 360                         compatible = "allwinner,sun9i-a80-usb-phy";
 361                         reg = <0x00a00800 0x4>;
 362                         clocks = <&usb_clocks CLK_USB0_PHY>;
 363                         clock-names = "phy";
 364                         resets = <&usb_clocks RST_USB0_PHY>;
 365                         reset-names = "phy";
 366                         status = "disabled";
 367                         #phy-cells = <0>;
 368                 };
 369
 370                 ehci1: usb@a01000 {
 371                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 372                         reg = <0x00a01000 0x100>;
 373                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&usb_clocks CLK_BUS_HCI1>;
 375                         resets = <&usb_clocks RST_USB1_HCI>;
 376                         phys = <&usbphy2>;
 377                         status = "disabled";
 378                 };
 379
 380                 usbphy2: phy@a01800 {
 381                         compatible = "allwinner,sun9i-a80-usb-phy";
 382                         reg = <0x00a01800 0x4>;
 383                         clocks = <&usb_clocks CLK_USB1_HSIC>,
 384                                  <&usb_clocks CLK_USB_HSIC>,
 385                                  <&usb_clocks CLK_USB1_PHY>;
 386                         clock-names = "hsic_480M",
 387                                       "hsic_12M",
 388                                       "phy";
 389                         resets = <&usb_clocks RST_USB1_HSIC>,
 390                                  <&usb_clocks RST_USB1_PHY>;
 391                         reset-names = "hsic",
 392                                       "phy";
 393                         status = "disabled";
 394                         #phy-cells = <0>;
 395                         /* usb1 is always used with HSIC */
 396                         phy_type = "hsic";
 397                 };
 398
 399                 ehci2: usb@a02000 {
 400                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 401                         reg = <0x00a02000 0x100>;
 402                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 403                         clocks = <&usb_clocks CLK_BUS_HCI2>;
 404                         resets = <&usb_clocks RST_USB2_HCI>;
 405                         phys = <&usbphy3>;
 406                         status = "disabled";
 407                 };
 408
 409                 ohci2: usb@a02400 {
 410                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 411                         reg = <0x00a02400 0x100>;
 412                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&usb_clocks CLK_BUS_HCI2>,
 414                                  <&usb_clocks CLK_USB_OHCI2>;
 415                         resets = <&usb_clocks RST_USB2_HCI>;
 416                         phys = <&usbphy3>;
 417                         status = "disabled";
 418                 };
 419
 420                 usbphy3: phy@a02800 {
 421                         compatible = "allwinner,sun9i-a80-usb-phy";
 422                         reg = <0x00a02800 0x4>;
 423                         clocks = <&usb_clocks CLK_USB2_HSIC>,
 424                                  <&usb_clocks CLK_USB_HSIC>,
 425                                  <&usb_clocks CLK_USB2_PHY>;
 426                         clock-names = "hsic_480M",
 427                                       "hsic_12M",
 428                                       "phy";
 429                         resets = <&usb_clocks RST_USB2_HSIC>,
 430                                  <&usb_clocks RST_USB2_PHY>;
 431                         reset-names = "hsic",
 432                                       "phy";
 433                         status = "disabled";
 434                         #phy-cells = <0>;
 435                 };
 436
 437                 usb_clocks: clock@a08000 {
 438                         compatible = "allwinner,sun9i-a80-usb-clks";
 439                         reg = <0x00a08000 0x8>;
 440                         clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
 441                         clock-names = "bus", "hosc";
 442                         #clock-cells = <1>;
 443                         #reset-cells = <1>;
 444                 };
 445
 446                 cpucfg@1700000 {
 447                         compatible = "allwinner,sun9i-a80-cpucfg";
 448                         reg = <0x01700000 0x100>;
 449                 };
 450
 451                 mmc0: mmc@1c0f000 {
 452                         compatible = "allwinner,sun9i-a80-mmc";
 453                         reg = <0x01c0f000 0x1000>;
 454                         clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
 455                                  <&ccu CLK_MMC0_OUTPUT>,
 456                                  <&ccu CLK_MMC0_SAMPLE>;
 457                         clock-names = "ahb", "mmc", "output", "sample";
 458                         resets = <&mmc_config_clk 0>;
 459                         reset-names = "ahb";
 460                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 461                         status = "disabled";
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                 };
 465
 466                 mmc1: mmc@1c10000 {
 467                         compatible = "allwinner,sun9i-a80-mmc";
 468                         reg = <0x01c10000 0x1000>;
 469                         clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
 470                                  <&ccu CLK_MMC1_OUTPUT>,
 471                                  <&ccu CLK_MMC1_SAMPLE>;
 472                         clock-names = "ahb", "mmc", "output", "sample";
 473                         resets = <&mmc_config_clk 1>;
 474                         reset-names = "ahb";
 475                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 476                         status = "disabled";
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                 };
 480
 481                 mmc2: mmc@1c11000 {
 482                         compatible = "allwinner,sun9i-a80-mmc";
 483                         reg = <0x01c11000 0x1000>;
 484                         clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
 485                                  <&ccu CLK_MMC2_OUTPUT>,
 486                                  <&ccu CLK_MMC2_SAMPLE>;
 487                         clock-names = "ahb", "mmc", "output", "sample";
 488                         resets = <&mmc_config_clk 2>;
 489                         reset-names = "ahb";
 490                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 491                         status = "disabled";
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                 };
 495
 496                 mmc3: mmc@1c12000 {
 497                         compatible = "allwinner,sun9i-a80-mmc";
 498                         reg = <0x01c12000 0x1000>;
 499                         clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
 500                                  <&ccu CLK_MMC3_OUTPUT>,
 501                                  <&ccu CLK_MMC3_SAMPLE>;
 502                         clock-names = "ahb", "mmc", "output", "sample";
 503                         resets = <&mmc_config_clk 3>;
 504                         reset-names = "ahb";
 505                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 506                         status = "disabled";
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                 };
 510
 511                 mmc_config_clk: clk@1c13000 {
 512                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 513                         reg = <0x01c13000 0x10>;
 514                         clocks = <&ccu CLK_BUS_MMC>;
 515                         clock-names = "ahb";
 516                         resets = <&ccu RST_BUS_MMC>;
 517                         reset-names = "ahb";
 518                         #clock-cells = <1>;
 519                         #reset-cells = <1>;
 520                         clock-output-names = "mmc0_config", "mmc1_config",
 521                                              "mmc2_config", "mmc3_config";
 522                 };
 523
 524                 gic: interrupt-controller@1c41000 {
 525                         compatible = "arm,gic-400";
 526                         reg = <0x01c41000 0x1000>,
 527                               <0x01c42000 0x2000>,
 528                               <0x01c44000 0x2000>,
 529                               <0x01c46000 0x2000>;
 530                         interrupt-controller;
 531                         #interrupt-cells = <3>;
 532                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 533                 };
 534
 535                 cci: cci@1c90000 {
 536                         compatible = "arm,cci-400";
 537                         #address-cells = <1>;
 538                         #size-cells = <1>;
 539                         reg = <0x01c90000 0x1000>;
 540                         ranges = <0x0 0x01c90000 0x10000>;
 541
 542                         cci_control0: slave-if@4000 {
 543                                 compatible = "arm,cci-400-ctrl-if";
 544                                 interface-type = "ace";
 545                                 reg = <0x4000 0x1000>;
 546                         };
 547
 548                         cci_control1: slave-if@5000 {
 549                                 compatible = "arm,cci-400-ctrl-if";
 550                                 interface-type = "ace";
 551                                 reg = <0x5000 0x1000>;
 552                         };
 553
 554                         pmu@9000 {
 555                                  compatible = "arm,cci-400-pmu,r1";
 556                                  reg = <0x9000 0x5000>;
 557                                  interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 558                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 559                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 560                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 561                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 562                         };
 563                 };
 564
 565                 de_clocks: clock@3000000 {
 566                         compatible = "allwinner,sun9i-a80-de-clks";
 567                         reg = <0x03000000 0x30>;
 568                         clocks = <&ccu CLK_DE>,
 569                                  <&ccu CLK_SDRAM>,
 570                                  <&ccu CLK_BUS_DE>;
 571                         clock-names = "mod",
 572                                       "dram",
 573                                       "bus";
 574                         resets = <&ccu RST_BUS_DE>;
 575                         #clock-cells = <1>;
 576                         #reset-cells = <1>;
 577                 };
 578
 579                 fe0: display-frontend@3100000 {
 580                         compatible = "allwinner,sun9i-a80-display-frontend";
 581                         reg = <0x03100000 0x40000>;
 582                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 583                         clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
 584                                  <&de_clocks CLK_DRAM_FE0>;
 585                         clock-names = "ahb", "mod",
 586                                       "ram";
 587                         resets = <&de_clocks RST_FE0>;
 588
 589                         ports {
 590                                 #address-cells = <1>;
 591                                 #size-cells = <0>;
 592
 593                                 fe0_out: port@1 {
 594                                         reg = <1>;
 595
 596                                         fe0_out_deu0: endpoint {
 597                                                 remote-endpoint = <&deu0_in_fe0>;
 598                                         };
 599                                 };
 600                         };
 601                 };
 602
 603                 fe1: display-frontend@3140000 {
 604                         compatible = "allwinner,sun9i-a80-display-frontend";
 605                         reg = <0x03140000 0x40000>;
 606                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
 608                                  <&de_clocks CLK_DRAM_FE1>;
 609                         clock-names = "ahb", "mod",
 610                                       "ram";
 611                         resets = <&de_clocks RST_FE0>;
 612
 613                         ports {
 614                                 #address-cells = <1>;
 615                                 #size-cells = <0>;
 616
 617                                 fe1_out: port@1 {
 618                                         reg = <1>;
 619
 620                                         fe1_out_deu1: endpoint {
 621                                                 remote-endpoint = <&deu1_in_fe1>;
 622                                         };
 623                                 };
 624                         };
 625                 };
 626
 627                 be0: display-backend@3200000 {
 628                         compatible = "allwinner,sun9i-a80-display-backend";
 629                         reg = <0x03200000 0x40000>;
 630                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
 632                                  <&de_clocks CLK_DRAM_BE0>;
 633                         clock-names = "ahb", "mod",
 634                                       "ram";
 635                         resets = <&de_clocks RST_BE0>;
 636
 637                         ports {
 638                                 #address-cells = <1>;
 639                                 #size-cells = <0>;
 640
 641                                 be0_in: port@0 {
 642                                         #address-cells = <1>;
 643                                         #size-cells = <0>;
 644                                         reg = <0>;
 645
 646                                         be0_in_deu0: endpoint@0 {
 647                                                 reg = <0>;
 648                                                 remote-endpoint = <&deu0_out_be0>;
 649                                         };
 650
 651                                         be0_in_deu1: endpoint@1 {
 652                                                 reg = <1>;
 653                                                 remote-endpoint = <&deu1_out_be0>;
 654                                         };
 655                                 };
 656
 657                                 be0_out: port@1 {
 658                                         reg = <1>;
 659
 660                                         be0_out_drc0: endpoint {
 661                                                 remote-endpoint = <&drc0_in_be0>;
 662                                         };
 663                                 };
 664                         };
 665                 };
 666
 667                 be1: display-backend@3240000 {
 668                         compatible = "allwinner,sun9i-a80-display-backend";
 669                         reg = <0x03240000 0x40000>;
 670                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 671                         clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
 672                                  <&de_clocks CLK_DRAM_BE1>;
 673                         clock-names = "ahb", "mod",
 674                                       "ram";
 675                         resets = <&de_clocks RST_BE1>;
 676
 677                         ports {
 678                                 #address-cells = <1>;
 679                                 #size-cells = <0>;
 680
 681                                 be1_in: port@0 {
 682                                         #address-cells = <1>;
 683                                         #size-cells = <0>;
 684                                         reg = <0>;
 685
 686                                         be1_in_deu0: endpoint@0 {
 687                                                 reg = <0>;
 688                                                 remote-endpoint = <&deu0_out_be1>;
 689                                         };
 690
 691                                         be1_in_deu1: endpoint@1 {
 692                                                 reg = <1>;
 693                                                 remote-endpoint = <&deu1_out_be1>;
 694                                         };
 695                                 };
 696
 697                                 be1_out: port@1 {
 698                                         reg = <1>;
 699
 700                                         be1_out_drc1: endpoint {
 701                                                 remote-endpoint = <&drc1_in_be1>;
 702                                         };
 703                                 };
 704                         };
 705                 };
 706
 707                 deu0: deu@3300000 {
 708                         compatible = "allwinner,sun9i-a80-deu";
 709                         reg = <0x03300000 0x40000>;
 710                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&de_clocks CLK_BUS_DEU0>,
 712                                  <&de_clocks CLK_IEP_DEU0>,
 713                                  <&de_clocks CLK_DRAM_DEU0>;
 714                         clock-names = "ahb",
 715                                       "mod",
 716                                       "ram";
 717                         resets = <&de_clocks RST_DEU0>;
 718
 719                         ports {
 720                                 #address-cells = <1>;
 721                                 #size-cells = <0>;
 722
 723                                 deu0_in: port@0 {
 724                                         reg = <0>;
 725
 726                                         deu0_in_fe0: endpoint {
 727                                                 remote-endpoint = <&fe0_out_deu0>;
 728                                         };
 729                                 };
 730
 731                                 deu0_out: port@1 {
 732                                         #address-cells = <1>;
 733                                         #size-cells = <0>;
 734                                         reg = <1>;
 735
 736                                         deu0_out_be0: endpoint@0 {
 737                                                 reg = <0>;
 738                                                 remote-endpoint = <&be0_in_deu0>;
 739                                         };
 740
 741                                         deu0_out_be1: endpoint@1 {
 742                                                 reg = <1>;
 743                                                 remote-endpoint = <&be1_in_deu0>;
 744                                         };
 745                                 };
 746                         };
 747                 };
 748
 749                 deu1: deu@3340000 {
 750                         compatible = "allwinner,sun9i-a80-deu";
 751                         reg = <0x03340000 0x40000>;
 752                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 753                         clocks = <&de_clocks CLK_BUS_DEU1>,
 754                                  <&de_clocks CLK_IEP_DEU1>,
 755                                  <&de_clocks CLK_DRAM_DEU1>;
 756                         clock-names = "ahb",
 757                                       "mod",
 758                                       "ram";
 759                         resets = <&de_clocks RST_DEU1>;
 760
 761                         ports {
 762                                 #address-cells = <1>;
 763                                 #size-cells = <0>;
 764
 765                                 deu1_in: port@0 {
 766                                         reg = <0>;
 767
 768                                         deu1_in_fe1: endpoint {
 769                                                 remote-endpoint = <&fe1_out_deu1>;
 770                                         };
 771                                 };
 772
 773                                 deu1_out: port@1 {
 774                                         #address-cells = <1>;
 775                                         #size-cells = <0>;
 776                                         reg = <1>;
 777
 778                                         deu1_out_be0: endpoint@0 {
 779                                                 reg = <0>;
 780                                                 remote-endpoint = <&be0_in_deu1>;
 781                                         };
 782
 783                                         deu1_out_be1: endpoint@1 {
 784                                                 reg = <1>;
 785                                                 remote-endpoint = <&be1_in_deu1>;
 786                                         };
 787                                 };
 788                         };
 789                 };
 790
 791                 drc0: drc@3400000 {
 792                         compatible = "allwinner,sun9i-a80-drc";
 793                         reg = <0x03400000 0x40000>;
 794                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&de_clocks CLK_BUS_DRC0>,
 796                                  <&de_clocks CLK_IEP_DRC0>,
 797                                  <&de_clocks CLK_DRAM_DRC0>;
 798                         clock-names = "ahb",
 799                                       "mod",
 800                                       "ram";
 801                         resets = <&de_clocks RST_DRC0>;
 802
 803                         ports {
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806
 807                                 drc0_in: port@0 {
 808                                         reg = <0>;
 809
 810                                         drc0_in_be0: endpoint {
 811                                                 remote-endpoint = <&be0_out_drc0>;
 812                                         };
 813                                 };
 814
 815                                 drc0_out: port@1 {
 816                                         reg = <1>;
 817
 818                                         drc0_out_tcon0: endpoint {
 819                                                 remote-endpoint = <&tcon0_in_drc0>;
 820                                         };
 821                                 };
 822                         };
 823                 };
 824
 825                 drc1: drc@3440000 {
 826                         compatible = "allwinner,sun9i-a80-drc";
 827                         reg = <0x03440000 0x40000>;
 828                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 829                         clocks = <&de_clocks CLK_BUS_DRC1>,
 830                                  <&de_clocks CLK_IEP_DRC1>,
 831                                  <&de_clocks CLK_DRAM_DRC1>;
 832                         clock-names = "ahb",
 833                                       "mod",
 834                                       "ram";
 835                         resets = <&de_clocks RST_DRC1>;
 836
 837                         ports {
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840
 841                                 drc1_in: port@0 {
 842                                         reg = <0>;
 843
 844                                         drc1_in_be1: endpoint {
 845                                                 remote-endpoint = <&be1_out_drc1>;
 846                                         };
 847                                 };
 848
 849                                 drc1_out: port@1 {
 850                                         reg = <1>;
 851
 852                                         drc1_out_tcon1: endpoint {
 853                                                 remote-endpoint = <&tcon1_in_drc1>;
 854                                         };
 855                                 };
 856                         };
 857                 };
 858
 859                 tcon0: lcd-controller@3c00000 {
 860                         compatible = "allwinner,sun9i-a80-tcon-lcd";
 861                         reg = <0x03c00000 0x10000>;
 862                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 863                         clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
 864                         clock-names = "ahb", "tcon-ch0";
 865                         resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
 866                         reset-names = "lcd", "edp";
 867                         clock-output-names = "tcon0-pixel-clock";
 868                         #clock-cells = <0>;
 869
 870                         ports {
 871                                 #address-cells = <1>;
 872                                 #size-cells = <0>;
 873
 874                                 tcon0_in: port@0 {
 875                                         reg = <0>;
 876
 877                                         tcon0_in_drc0: endpoint {
 878                                                 remote-endpoint = <&drc0_out_tcon0>;
 879                                         };
 880                                 };
 881
 882                                 tcon0_out: port@1 {
 883                                         reg = <1>;
 884                                 };
 885                         };
 886                 };
 887
 888                 tcon1: lcd-controller@3c10000 {
 889                         compatible = "allwinner,sun9i-a80-tcon-tv";
 890                         reg = <0x03c10000 0x10000>;
 891                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 892                         clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
 893                         clock-names = "ahb", "tcon-ch1";
 894                         resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
 895                         reset-names = "lcd", "edp";
 896
 897                         ports {
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900
 901                                 tcon1_in: port@0 {
 902                                         reg = <0>;
 903
 904                                         tcon1_in_drc1: endpoint {
 905                                                 remote-endpoint = <&drc1_out_tcon1>;
 906                                         };
 907                                 };
 908
 909                                 tcon1_out: port@1 {
 910                                         reg = <1>;
 911                                 };
 912                         };
 913                 };
 914
 915                 ccu: clock@6000000 {
 916                         compatible = "allwinner,sun9i-a80-ccu";
 917                         reg = <0x06000000 0x800>;
 918                         clocks = <&osc24M>, <&osc32k>;
 919                         clock-names = "hosc", "losc";
 920                         #clock-cells = <1>;
 921                         #reset-cells = <1>;
 922                 };
 923
 924                 timer@6000c00 {
 925                         compatible = "allwinner,sun4i-a10-timer";
 926                         reg = <0x06000c00 0xa0>;
 927                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 933
 934                         clocks = <&osc24M>;
 935                 };
 936
 937                 wdt: watchdog@6000ca0 {
 938                         compatible = "allwinner,sun6i-a31-wdt";
 939                         reg = <0x06000ca0 0x20>;
 940                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 941                 };
 942
 943                 pio: pinctrl@6000800 {
 944                         compatible = "allwinner,sun9i-a80-pinctrl";
 945                         reg = <0x06000800 0x400>;
 946                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 951                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 952                         clock-names = "apb", "hosc", "losc";
 953                         gpio-controller;
 954                         interrupt-controller;
 955                         #interrupt-cells = <3>;
 956                         #gpio-cells = <3>;
 957
 958                         gmac_rgmii_pins: gmac-rgmii-pins {
 959                                 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
 960                                        "PA7", "PA8", "PA9", "PA10", "PA12",
 961                                        "PA13", "PA15", "PA16", "PA17";
 962                                 function = "gmac";
 963                                 /*
 964                                  * data lines in RGMII mode use DDR mode
 965                                  * and need a higher signal drive strength
 966                                  */
 967                                 drive-strength = <40>;
 968                         };
 969
 970                         i2c3_pins: i2c3-pins {
 971                                 pins = "PG10", "PG11";
 972                                 function = "i2c3";
 973                         };
 974
 975                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 976                                 pins = "PD0", "PD1", "PD2", "PD3",
 977                                        "PD4", "PD5", "PD6", "PD7",
 978                                        "PD8", "PD9", "PD10", "PD11",
 979                                        "PD12", "PD13", "PD14", "PD15",
 980                                        "PD16", "PD17", "PD18", "PD19",
 981                                        "PD20", "PD21", "PD22", "PD23",
 982                                        "PD24", "PD25", "PD26", "PD27";
 983                                 function = "lcd0";
 984                         };
 985
 986                         mmc0_pins: mmc0-pins {
 987                                 pins = "PF0", "PF1" ,"PF2", "PF3",
 988                                        "PF4", "PF5";
 989                                 function = "mmc0";
 990                                 drive-strength = <30>;
 991                                 bias-pull-up;
 992                         };
 993
 994                         mmc1_pins: mmc1-pins {
 995                                 pins = "PG0", "PG1" ,"PG2", "PG3",
 996                                                  "PG4", "PG5";
 997                                 function = "mmc1";
 998                                 drive-strength = <30>;
 999                                 bias-pull-up;
1000                         };
1001
1002                         mmc2_8bit_pins: mmc2-8bit-pins {
1003                                 pins = "PC6", "PC7", "PC8", "PC9",
1004                                        "PC10", "PC11", "PC12",
1005                                        "PC13", "PC14", "PC15",
1006                                        "PC16";
1007                                 function = "mmc2";
1008                                 drive-strength = <30>;
1009                                 bias-pull-up;
1010                         };
1011
1012                         uart0_ph_pins: uart0-ph-pins {
1013                                 pins = "PH12", "PH13";
1014                                 function = "uart0";
1015                         };
1016
1017                         uart4_pins: uart4-pins {
1018                                 pins = "PG12", "PG13", "PG14", "PG15";
1019                                 function = "uart4";
1020                         };
1021                 };
1022
1023                 uart0: serial@7000000 {
1024                         compatible = "snps,dw-apb-uart";
1025                         reg = <0x07000000 0x400>;
1026                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1027                         reg-shift = <2>;
1028                         reg-io-width = <4>;
1029                         clocks = <&ccu CLK_BUS_UART0>;
1030                         resets = <&ccu RST_BUS_UART0>;
1031                         status = "disabled";
1032                 };
1033
1034                 uart1: serial@7000400 {
1035                         compatible = "snps,dw-apb-uart";
1036                         reg = <0x07000400 0x400>;
1037                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1038                         reg-shift = <2>;
1039                         reg-io-width = <4>;
1040                         clocks = <&ccu CLK_BUS_UART1>;
1041                         resets = <&ccu RST_BUS_UART1>;
1042                         status = "disabled";
1043                 };
1044
1045                 uart2: serial@7000800 {
1046                         compatible = "snps,dw-apb-uart";
1047                         reg = <0x07000800 0x400>;
1048                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1049                         reg-shift = <2>;
1050                         reg-io-width = <4>;
1051                         clocks = <&ccu CLK_BUS_UART2>;
1052                         resets = <&ccu RST_BUS_UART2>;
1053                         status = "disabled";
1054                 };
1055
1056                 uart3: serial@7000c00 {
1057                         compatible = "snps,dw-apb-uart";
1058                         reg = <0x07000c00 0x400>;
1059                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1060                         reg-shift = <2>;
1061                         reg-io-width = <4>;
1062                         clocks = <&ccu CLK_BUS_UART3>;
1063                         resets = <&ccu RST_BUS_UART3>;
1064                         status = "disabled";
1065                 };
1066
1067                 uart4: serial@7001000 {
1068                         compatible = "snps,dw-apb-uart";
1069                         reg = <0x07001000 0x400>;
1070                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1071                         reg-shift = <2>;
1072                         reg-io-width = <4>;
1073                         clocks = <&ccu CLK_BUS_UART4>;
1074                         resets = <&ccu RST_BUS_UART4>;
1075                         status = "disabled";
1076                 };
1077
1078                 uart5: serial@7001400 {
1079                         compatible = "snps,dw-apb-uart";
1080                         reg = <0x07001400 0x400>;
1081                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1082                         reg-shift = <2>;
1083                         reg-io-width = <4>;
1084                         clocks = <&ccu CLK_BUS_UART5>;
1085                         resets = <&ccu RST_BUS_UART5>;
1086                         status = "disabled";
1087                 };
1088
1089                 i2c0: i2c@7002800 {
1090                         compatible = "allwinner,sun6i-a31-i2c";
1091                         reg = <0x07002800 0x400>;
1092                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1093                         clocks = <&ccu CLK_BUS_I2C0>;
1094                         resets = <&ccu RST_BUS_I2C0>;
1095                         status = "disabled";
1096                         #address-cells = <1>;
1097                         #size-cells = <0>;
1098                 };
1099
1100                 i2c1: i2c@7002c00 {
1101                         compatible = "allwinner,sun6i-a31-i2c";
1102                         reg = <0x07002c00 0x400>;
1103                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1104                         clocks = <&ccu CLK_BUS_I2C1>;
1105                         resets = <&ccu RST_BUS_I2C1>;
1106                         status = "disabled";
1107                         #address-cells = <1>;
1108                         #size-cells = <0>;
1109                 };
1110
1111                 i2c2: i2c@7003000 {
1112                         compatible = "allwinner,sun6i-a31-i2c";
1113                         reg = <0x07003000 0x400>;
1114                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1115                         clocks = <&ccu CLK_BUS_I2C2>;
1116                         resets = <&ccu RST_BUS_I2C2>;
1117                         status = "disabled";
1118                         #address-cells = <1>;
1119                         #size-cells = <0>;
1120                 };
1121
1122                 i2c3: i2c@7003400 {
1123                         compatible = "allwinner,sun6i-a31-i2c";
1124                         reg = <0x07003400 0x400>;
1125                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1126                         clocks = <&ccu CLK_BUS_I2C3>;
1127                         resets = <&ccu RST_BUS_I2C3>;
1128                         status = "disabled";
1129                         #address-cells = <1>;
1130                         #size-cells = <0>;
1131                 };
1132
1133                 i2c4: i2c@7003800 {
1134                         compatible = "allwinner,sun6i-a31-i2c";
1135                         reg = <0x07003800 0x400>;
1136                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1137                         clocks = <&ccu CLK_BUS_I2C4>;
1138                         resets = <&ccu RST_BUS_I2C4>;
1139                         status = "disabled";
1140                         #address-cells = <1>;
1141                         #size-cells = <0>;
1142                 };
1143
1144                 r_wdt: watchdog@8001000 {
1145                         compatible = "allwinner,sun6i-a31-wdt";
1146                         reg = <0x08001000 0x20>;
1147                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1148                 };
1149
1150                 prcm@8001400 {
1151                         compatible = "allwinner,sun9i-a80-prcm";
1152                         reg = <0x08001400 0x200>;
1153                 };
1154
1155                 apbs_rst: reset@80014b0 {
1156                         reg = <0x080014b0 0x4>;
1157                         compatible = "allwinner,sun6i-a31-clock-reset";
1158                         #reset-cells = <1>;
1159                 };
1160
1161                 nmi_intc: interrupt-controller@80015a0 {
1162                         compatible = "allwinner,sun9i-a80-nmi";
1163                         interrupt-controller;
1164                         #interrupt-cells = <2>;
1165                         reg = <0x080015a0 0xc>;
1166                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1167                 };
1168
1169                 r_ir: ir@8002000 {
1170                         compatible = "allwinner,sun5i-a13-ir";
1171                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1172                         pinctrl-names = "default";
1173                         pinctrl-0 = <&r_ir_pins>;
1174                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
1175                         clock-names = "apb", "ir";
1176                         resets = <&apbs_rst 1>;
1177                         reg = <0x08002000 0x40>;
1178                         status = "disabled";
1179                 };
1180
1181                 r_uart: serial@8002800 {
1182                         compatible = "snps,dw-apb-uart";
1183                         reg = <0x08002800 0x400>;
1184                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1185                         reg-shift = <2>;
1186                         reg-io-width = <4>;
1187                         clocks = <&apbs_gates 4>;
1188                         resets = <&apbs_rst 4>;
1189                         status = "disabled";
1190                 };
1191
1192                 r_pio: pinctrl@8002c00 {
1193                         compatible = "allwinner,sun9i-a80-r-pinctrl";
1194                         reg = <0x08002c00 0x400>;
1195                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1197                         clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1198                         clock-names = "apb", "hosc", "losc";
1199                         resets = <&apbs_rst 0>;
1200                         gpio-controller;
1201                         interrupt-controller;
1202                         #interrupt-cells = <3>;
1203                         #gpio-cells = <3>;
1204
1205                         r_ir_pins: r-ir-pins {
1206                                 pins = "PL6";
1207                                 function = "s_cir_rx";
1208                         };
1209
1210                         r_rsb_pins: r-rsb-pins {
1211                                 pins = "PN0", "PN1";
1212                                 function = "s_rsb";
1213                                 drive-strength = <20>;
1214                                 bias-pull-up;
1215                         };
1216                 };
1217
1218                 r_rsb: rsb@8003400 {
1219                         compatible = "allwinner,sun8i-a23-rsb";
1220                         reg = <0x08003400 0x400>;
1221                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1222                         clocks = <&apbs_gates 3>;
1223                         clock-frequency = <3000000>;
1224                         resets = <&apbs_rst 3>;
1225                         pinctrl-names = "default";
1226                         pinctrl-0 = <&r_rsb_pins>;
1227                         status = "disabled";
1228                         #address-cells = <1>;
1229                         #size-cells = <0>;
1230                 };
1231         };
1232 };