arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43
  44  */
  45
  46 #include "skeleton.dtsi"
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@0 {
  58                         compatible = "arm,cortex-a7";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                 };
  62
  63                 cpu@1 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         reg = <1>;
  67                 };
  68
  69                 cpu@2 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <2>;
  73                 };
  74
  75                 cpu@3 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <3>;
  79                 };
  80
  81                 cpu@100 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <0x100>;
  85                 };
  86
  87                 cpu@101 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <0x101>;
  91                 };
  92
  93                 cpu@102 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <0x102>;
  97                 };
  98
  99                 cpu@103 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <0x103>;
 103                 };
 104         };
 105
 106         timer {
 107                 compatible = "arm,armv7-timer";
 108                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 111                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 112         };
 113
 114         clocks {
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges;
 118
 119                 /* TODO: PRCM block has a mux for this. */
 120                 osc24M: osc24M_clk {
 121                         #clock-cells = <0>;
 122                         compatible = "fixed-clock";
 123                         clock-frequency = <24000000>;
 124                         clock-output-names = "osc24M";
 125                 };
 126
 127                 /*
 128                  * This is called "internal OSC" in some places.
 129                  * It is an internal RC-based oscillator.
 130                  * TODO: Its controls are in the PRCM block.
 131                  */
 132                 osc16M: osc16M_clk {
 133                         #clock-cells = <0>;
 134                         compatible = "fixed-clock";
 135                         clock-frequency = <16000000>;
 136                         clock-output-names = "osc16M";
 137                 };
 138
 139                 osc16Md512: osc16Md512_clk {
 140                         #clock-cells = <0>;
 141                         compatible = "fixed-factor-clock";
 142                         clock-div = <512>;
 143                         clock-mult = <1>;
 144                         clocks = <&osc16M>;
 145                         clock-output-names = "osc16M-d512";
 146                 };
 147         };
 148
 149         soc {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 ranges;
 154
 155                 pio: pinctrl@01c20800 {
 156                         compatible = "allwinner,sun8i-a83t-pinctrl";
 157                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 159                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 160                         reg = <0x01c20800 0x400>;
 161                         clocks = <&osc24M>;
 162                         gpio-controller;
 163                         interrupt-controller;
 164                         #interrupt-cells = <3>;
 165                         #gpio-cells = <3>;
 166
 167                         mmc0_pins_a: mmc0@0 {
 168                                 pins = "PF0", "PF1", "PF2",
 169                                        "PF3", "PF4", "PF5";
 170                                 function = "mmc0";
 171                                 drive-strength = <30>;
 172                                 bias-pull-up;
 173                         };
 174
 175                         uart0_pins_a: uart0@0 {
 176                                 pins = "PF2", "PF4";
 177                                 function = "uart0";
 178                         };
 179
 180                         uart0_pins_b: uart0@1 {
 181                                 pins = "PB9", "PB10";
 182                                 function = "uart0";
 183                         };
 184                 };
 185
 186                 timer@01c20c00 {
 187                         compatible = "allwinner,sun4i-a10-timer";
 188                         reg = <0x01c20c00 0xa0>;
 189                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&osc24M>;
 192                 };
 193
 194                 watchdog@01c20ca0 {
 195                         compatible = "allwinner,sun6i-a31-wdt";
 196                         reg = <0x01c20ca0 0x20>;
 197                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&osc24M>;
 199                 };
 200
 201                 uart0: serial@01c28000 {
 202                         compatible = "snps,dw-apb-uart";
 203                         reg = <0x01c28000 0x400>;
 204                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 205                         reg-shift = <2>;
 206                         reg-io-width = <4>;
 207                         clocks = <&osc24M>;
 208                         status = "disabled";
 209                 };
 210
 211                 gic: interrupt-controller@01c81000 {
 212                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 213                         reg = <0x01c81000 0x1000>,
 214                               <0x01c82000 0x2000>,
 215                               <0x01c84000 0x2000>,
 216                               <0x01c86000 0x2000>;
 217                         interrupt-controller;
 218                         #interrupt-cells = <3>;
 219                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 220                 };
 221         };
 222 };