arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 simplefb_lcd: framebuffer-lcd0 {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "de_be0-lcd0";
  64                         clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
  65                                  <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
  66                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
  67                         status = "disabled";
  68                 };
  69         };
  70
  71         de: display-engine {
  72                 /* compatible gets set in SoC specific dtsi file */
  73                 allwinner,pipelines = <&fe0>;
  74                 status = "disabled";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  83                 clock-frequency = <24000000>;
  84                 arm,cpu-registers-not-fw-configured;
  85         };
  86
  87         cpus {
  88                 enable-method = "allwinner,sun8i-a23";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 cpu0: cpu@0 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         reg = <0>;
  96                 };
  97
  98                 cpu@1 {
  99                         compatible = "arm,cortex-a7";
 100                         device_type = "cpu";
 101                         reg = <1>;
 102                 };
 103         };
 104
 105         clocks {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 osc24M: osc24M_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <24000000>;
 114                         clock-accuracy = <50000>;
 115                         clock-output-names = "osc24M";
 116                 };
 117
 118                 ext_osc32k: ext_osc32k_clk {
 119                         #clock-cells = <0>;
 120                         compatible = "fixed-clock";
 121                         clock-frequency = <32768>;
 122                         clock-accuracy = <50000>;
 123                         clock-output-names = "ext-osc32k";
 124                 };
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132
 133                 system-control@1c00000 {
 134                         compatible = "allwinner,sun8i-a23-system-control";
 135                         reg = <0x01c00000 0x30>;
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         sram_c: sram@1d00000 {
 141                                 compatible = "mmio-sram";
 142                                 reg = <0x01d00000 0x80000>;
 143                                 #address-cells = <1>;
 144                                 #size-cells = <1>;
 145                                 ranges = <0 0x01d00000 0x80000>;
 146
 147                                 ve_sram: sram-section@0 {
 148                                         compatible = "allwinner,sun8i-a23-sram-c1",
 149                                                      "allwinner,sun4i-a10-sram-c1";
 150                                         reg = <0x000000 0x80000>;
 151                                 };
 152                         };
 153                 };
 154
 155                 dma: dma-controller@1c02000 {
 156                         compatible = "allwinner,sun8i-a23-dma";
 157                         reg = <0x01c02000 0x1000>;
 158                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&ccu CLK_BUS_DMA>;
 160                         resets = <&ccu RST_BUS_DMA>;
 161                         #dma-cells = <1>;
 162                 };
 163
 164                 nfc: nand-controller@1c03000 {
 165                         compatible = "allwinner,sun8i-a23-nand-controller";
 166                         reg = <0x01c03000 0x1000>;
 167                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 169                         clock-names = "ahb", "mod";
 170                         resets = <&ccu RST_BUS_NAND>;
 171                         reset-names = "ahb";
 172                         dmas = <&dma 5>;
 173                         dma-names = "rxtx";
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
 176                         status = "disabled";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                 };
 180
 181                 tcon0: lcd-controller@1c0c000 {
 182                         /* compatible gets set in SoC specific dtsi file */
 183                         reg = <0x01c0c000 0x1000>;
 184                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 185                         clocks = <&ccu CLK_BUS_LCD>,
 186                                  <&ccu CLK_LCD_CH0>;
 187                         clock-names = "ahb",
 188                                       "tcon-ch0";
 189                         clock-output-names = "tcon-pixel-clock";
 190                         #clock-cells = <0>;
 191                         resets = <&ccu RST_BUS_LCD>;
 192                         reset-names = "lcd";
 193                         status = "disabled";
 194
 195                         ports {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198
 199                                 tcon0_in: port@0 {
 200                                         reg = <0>;
 201
 202                                         tcon0_in_drc0: endpoint {
 203                                                 remote-endpoint = <&drc0_out_tcon0>;
 204                                         };
 205                                 };
 206
 207                                 tcon0_out: port@1 {
 208                                         reg = <1>;
 209                                 };
 210                         };
 211                 };
 212
 213                 mmc0: mmc@1c0f000 {
 214                         compatible = "allwinner,sun7i-a20-mmc";
 215                         reg = <0x01c0f000 0x1000>;
 216                         clocks = <&ccu CLK_BUS_MMC0>,
 217                                  <&ccu CLK_MMC0>,
 218                                  <&ccu CLK_MMC0_OUTPUT>,
 219                                  <&ccu CLK_MMC0_SAMPLE>;
 220                         clock-names = "ahb",
 221                                       "mmc",
 222                                       "output",
 223                                       "sample";
 224                         resets = <&ccu RST_BUS_MMC0>;
 225                         reset-names = "ahb";
 226                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 227                         pinctrl-names = "default";
 228                         pinctrl-0 = <&mmc0_pins>;
 229                         status = "disabled";
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                 };
 233
 234                 mmc1: mmc@1c10000 {
 235                         compatible = "allwinner,sun7i-a20-mmc";
 236                         reg = <0x01c10000 0x1000>;
 237                         clocks = <&ccu CLK_BUS_MMC1>,
 238                                  <&ccu CLK_MMC1>,
 239                                  <&ccu CLK_MMC1_OUTPUT>,
 240                                  <&ccu CLK_MMC1_SAMPLE>;
 241                         clock-names = "ahb",
 242                                       "mmc",
 243                                       "output",
 244                                       "sample";
 245                         resets = <&ccu RST_BUS_MMC1>;
 246                         reset-names = "ahb";
 247                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 248                         status = "disabled";
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                 };
 252
 253                 mmc2: mmc@1c11000 {
 254                         compatible = "allwinner,sun7i-a20-mmc";
 255                         reg = <0x01c11000 0x1000>;
 256                         clocks = <&ccu CLK_BUS_MMC2>,
 257                                  <&ccu CLK_MMC2>,
 258                                  <&ccu CLK_MMC2_OUTPUT>,
 259                                  <&ccu CLK_MMC2_SAMPLE>;
 260                         clock-names = "ahb",
 261                                       "mmc",
 262                                       "output",
 263                                       "sample";
 264                         resets = <&ccu RST_BUS_MMC2>;
 265                         reset-names = "ahb";
 266                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 267                         status = "disabled";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                 };
 271
 272                 usb_otg: usb@1c19000 {
 273                         /* compatible gets set in SoC specific dtsi file */
 274                         reg = <0x01c19000 0x0400>;
 275                         clocks = <&ccu CLK_BUS_OTG>;
 276                         resets = <&ccu RST_BUS_OTG>;
 277                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 278                         interrupt-names = "mc";
 279                         phys = <&usbphy 0>;
 280                         phy-names = "usb";
 281                         extcon = <&usbphy 0>;
 282                         dr_mode = "otg";
 283                         status = "disabled";
 284                 };
 285
 286                 usbphy: phy@1c19400 {
 287                         /*
 288                          * compatible and address regions get set in
 289                          * SoC specific dtsi file
 290                          */
 291                         clocks = <&ccu CLK_USB_PHY0>,
 292                                  <&ccu CLK_USB_PHY1>;
 293                         clock-names = "usb0_phy",
 294                                       "usb1_phy";
 295                         resets = <&ccu RST_USB_PHY0>,
 296                                  <&ccu RST_USB_PHY1>;
 297                         reset-names = "usb0_reset",
 298                                       "usb1_reset";
 299                         status = "disabled";
 300                         #phy-cells = <1>;
 301                 };
 302
 303                 ehci0: usb@1c1a000 {
 304                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 305                         reg = <0x01c1a000 0x100>;
 306                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&ccu CLK_BUS_EHCI>;
 308                         resets = <&ccu RST_BUS_EHCI>;
 309                         phys = <&usbphy 1>;
 310                         phy-names = "usb";
 311                         status = "disabled";
 312                 };
 313
 314                 ohci0: usb@1c1a400 {
 315                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 316                         reg = <0x01c1a400 0x100>;
 317                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
 319                         resets = <&ccu RST_BUS_OHCI>;
 320                         phys = <&usbphy 1>;
 321                         phy-names = "usb";
 322                         status = "disabled";
 323                 };
 324
 325                 ccu: clock@1c20000 {
 326                         reg = <0x01c20000 0x400>;
 327                         clocks = <&osc24M>, <&rtc 0>;
 328                         clock-names = "hosc", "losc";
 329                         #clock-cells = <1>;
 330                         #reset-cells = <1>;
 331                 };
 332
 333                 pio: pinctrl@1c20800 {
 334                         /* compatible gets set in SoC specific dtsi file */
 335                         reg = <0x01c20800 0x400>;
 336                         /* interrupts get set in SoC specific dtsi file */
 337                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 338                         clock-names = "apb", "hosc", "losc";
 339                         gpio-controller;
 340                         interrupt-controller;
 341                         #interrupt-cells = <3>;
 342                         #gpio-cells = <3>;
 343
 344                         i2c0_pins: i2c0-pins {
 345                                 pins = "PH2", "PH3";
 346                                 function = "i2c0";
 347                         };
 348
 349                         i2c1_pins: i2c1-pins {
 350                                 pins = "PH4", "PH5";
 351                                 function = "i2c1";
 352                         };
 353
 354                         i2c2_pins: i2c2-pins {
 355                                 pins = "PE12", "PE13";
 356                                 function = "i2c2";
 357                         };
 358
 359                         lcd_rgb666_pins: lcd-rgb666-pins {
 360                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 361                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 362                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 363                                        "PD24", "PD25", "PD26", "PD27";
 364                                 function = "lcd0";
 365                         };
 366
 367                         mmc0_pins: mmc0-pins {
 368                                 pins = "PF0", "PF1", "PF2",
 369                                        "PF3", "PF4", "PF5";
 370                                 function = "mmc0";
 371                                 drive-strength = <30>;
 372                                 bias-pull-up;
 373                         };
 374
 375                         mmc1_pg_pins: mmc1-pg-pins {
 376                                 pins = "PG0", "PG1", "PG2",
 377                                        "PG3", "PG4", "PG5";
 378                                 function = "mmc1";
 379                                 drive-strength = <30>;
 380                                 bias-pull-up;
 381                         };
 382
 383                         mmc2_8bit_pins: mmc2-8bit-pins {
 384                                 pins = "PC5", "PC6", "PC8",
 385                                        "PC9", "PC10", "PC11",
 386                                        "PC12", "PC13", "PC14",
 387                                        "PC15", "PC16";
 388                                 function = "mmc2";
 389                                 drive-strength = <30>;
 390                                 bias-pull-up;
 391                         };
 392
 393                         nand_pins: nand-pins {
 394                                 pins = "PC0", "PC1", "PC2", "PC5",
 395                                        "PC8", "PC9", "PC10", "PC11",
 396                                        "PC12", "PC13", "PC14", "PC15";
 397                                 function = "nand0";
 398                         };
 399
 400                         nand_cs0_pin: nand-cs0-pin {
 401                                 pins = "PC4";
 402                                 function = "nand0";
 403                                 bias-pull-up;
 404                         };
 405
 406                         nand_cs1_pin: nand-cs1-pin {
 407                                 pins = "PC3";
 408                                 function = "nand0";
 409                                 bias-pull-up;
 410                         };
 411
 412                         nand_rb0_pin: nand-rb0-pin {
 413                                 pins = "PC6";
 414                                 function = "nand0";
 415                                 bias-pull-up;
 416                         };
 417
 418                         nand_rb1_pin: nand-rb1-pin {
 419                                 pins = "PC7";
 420                                 function = "nand0";
 421                                 bias-pull-up;
 422                         };
 423
 424                         pwm0_pin: pwm0-pin {
 425                                 pins = "PH0";
 426                                 function = "pwm0";
 427                         };
 428
 429                         uart0_pf_pins: uart0-pf-pins {
 430                                 pins = "PF2", "PF4";
 431                                 function = "uart0";
 432                         };
 433
 434                         uart1_pg_pins: uart1-pg-pins {
 435                                 pins = "PG6", "PG7";
 436                                 function = "uart1";
 437                         };
 438
 439                         uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
 440                                 pins = "PG8", "PG9";
 441                                 function = "uart1";
 442                         };
 443                 };
 444
 445                 timer@1c20c00 {
 446                         compatible = "allwinner,sun8i-a23-timer";
 447                         reg = <0x01c20c00 0xa0>;
 448                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 449                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 450                         clocks = <&osc24M>;
 451                 };
 452
 453                 wdt0: watchdog@1c20ca0 {
 454                         compatible = "allwinner,sun6i-a31-wdt";
 455                         reg = <0x01c20ca0 0x20>;
 456                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&osc24M>;
 458                 };
 459
 460                 pwm: pwm@1c21400 {
 461                         compatible = "allwinner,sun7i-a20-pwm";
 462                         reg = <0x01c21400 0xc>;
 463                         clocks = <&osc24M>;
 464                         #pwm-cells = <3>;
 465                         status = "disabled";
 466                 };
 467
 468                 lradc: lradc@1c22800 {
 469                         compatible = "allwinner,sun4i-a10-lradc-keys";
 470                         reg = <0x01c22800 0x100>;
 471                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 472                         status = "disabled";
 473                 };
 474
 475                 uart0: serial@1c28000 {
 476                         compatible = "snps,dw-apb-uart";
 477                         reg = <0x01c28000 0x400>;
 478                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 479                         reg-shift = <2>;
 480                         reg-io-width = <4>;
 481                         clocks = <&ccu CLK_BUS_UART0>;
 482                         resets = <&ccu RST_BUS_UART0>;
 483                         dmas = <&dma 6>, <&dma 6>;
 484                         dma-names = "rx", "tx";
 485                         status = "disabled";
 486                 };
 487
 488                 uart1: serial@1c28400 {
 489                         compatible = "snps,dw-apb-uart";
 490                         reg = <0x01c28400 0x400>;
 491                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 492                         reg-shift = <2>;
 493                         reg-io-width = <4>;
 494                         clocks = <&ccu CLK_BUS_UART1>;
 495                         resets = <&ccu RST_BUS_UART1>;
 496                         dmas = <&dma 7>, <&dma 7>;
 497                         dma-names = "rx", "tx";
 498                         status = "disabled";
 499                 };
 500
 501                 uart2: serial@1c28800 {
 502                         compatible = "snps,dw-apb-uart";
 503                         reg = <0x01c28800 0x400>;
 504                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 505                         reg-shift = <2>;
 506                         reg-io-width = <4>;
 507                         clocks = <&ccu CLK_BUS_UART2>;
 508                         resets = <&ccu RST_BUS_UART2>;
 509                         dmas = <&dma 8>, <&dma 8>;
 510                         dma-names = "rx", "tx";
 511                         status = "disabled";
 512                 };
 513
 514                 uart3: serial@1c28c00 {
 515                         compatible = "snps,dw-apb-uart";
 516                         reg = <0x01c28c00 0x400>;
 517                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 518                         reg-shift = <2>;
 519                         reg-io-width = <4>;
 520                         clocks = <&ccu CLK_BUS_UART3>;
 521                         resets = <&ccu RST_BUS_UART3>;
 522                         dmas = <&dma 9>, <&dma 9>;
 523                         dma-names = "rx", "tx";
 524                         status = "disabled";
 525                 };
 526
 527                 uart4: serial@1c29000 {
 528                         compatible = "snps,dw-apb-uart";
 529                         reg = <0x01c29000 0x400>;
 530                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 531                         reg-shift = <2>;
 532                         reg-io-width = <4>;
 533                         clocks = <&ccu CLK_BUS_UART4>;
 534                         resets = <&ccu RST_BUS_UART4>;
 535                         dmas = <&dma 10>, <&dma 10>;
 536                         dma-names = "rx", "tx";
 537                         status = "disabled";
 538                 };
 539
 540                 i2c0: i2c@1c2ac00 {
 541                         compatible = "allwinner,sun6i-a31-i2c";
 542                         reg = <0x01c2ac00 0x400>;
 543                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&ccu CLK_BUS_I2C0>;
 545                         resets = <&ccu RST_BUS_I2C0>;
 546                         pinctrl-names = "default";
 547                         pinctrl-0 = <&i2c0_pins>;
 548                         status = "disabled";
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                 };
 552
 553                 i2c1: i2c@1c2b000 {
 554                         compatible = "allwinner,sun6i-a31-i2c";
 555                         reg = <0x01c2b000 0x400>;
 556                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&ccu CLK_BUS_I2C1>;
 558                         resets = <&ccu RST_BUS_I2C1>;
 559                         pinctrl-names = "default";
 560                         pinctrl-0 = <&i2c1_pins>;
 561                         status = "disabled";
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                 };
 565
 566                 i2c2: i2c@1c2b400 {
 567                         compatible = "allwinner,sun6i-a31-i2c";
 568                         reg = <0x01c2b400 0x400>;
 569                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&ccu CLK_BUS_I2C2>;
 571                         resets = <&ccu RST_BUS_I2C2>;
 572                         pinctrl-names = "default";
 573                         pinctrl-0 = <&i2c2_pins>;
 574                         status = "disabled";
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                 };
 578
 579                 mali: gpu@1c40000 {
 580                         compatible = "allwinner,sun8i-a23-mali",
 581                                      "allwinner,sun7i-a20-mali", "arm,mali-400";
 582                         reg = <0x01c40000 0x10000>;
 583                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 590                         interrupt-names = "gp",
 591                                           "gpmmu",
 592                                           "pp0",
 593                                           "ppmmu0",
 594                                           "pp1",
 595                                           "ppmmu1",
 596                                           "pmu";
 597                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 598                         clock-names = "bus", "core";
 599                         resets = <&ccu RST_BUS_GPU>;
 600                         #cooling-cells = <2>;
 601
 602                         assigned-clocks = <&ccu CLK_GPU>;
 603                         assigned-clock-rates = <384000000>;
 604                 };
 605
 606                 gic: interrupt-controller@1c81000 {
 607                         compatible = "arm,gic-400";
 608                         reg = <0x01c81000 0x1000>,
 609                               <0x01c82000 0x2000>,
 610                               <0x01c84000 0x2000>,
 611                               <0x01c86000 0x2000>;
 612                         interrupt-controller;
 613                         #interrupt-cells = <3>;
 614                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 615                 };
 616
 617                 fe0: display-frontend@1e00000 {
 618                         /* compatible gets set in SoC specific dtsi file */
 619                         reg = <0x01e00000 0x20000>;
 620                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 621                         clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
 622                                  <&ccu CLK_DRAM_DE_FE>;
 623                         clock-names = "ahb", "mod",
 624                                       "ram";
 625                         resets = <&ccu RST_BUS_DE_FE>;
 626
 627                         ports {
 628                                 #address-cells = <1>;
 629                                 #size-cells = <0>;
 630
 631                                 fe0_out: port@1 {
 632                                         reg = <1>;
 633
 634                                         fe0_out_be0: endpoint {
 635                                                 remote-endpoint = <&be0_in_fe0>;
 636                                         };
 637                                 };
 638                         };
 639                 };
 640
 641                 be0: display-backend@1e60000 {
 642                         /* compatible gets set in SoC specific dtsi file */
 643                         reg = <0x01e60000 0x10000>;
 644                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 646                                  <&ccu CLK_DRAM_DE_BE>;
 647                         clock-names = "ahb", "mod",
 648                                       "ram";
 649                         resets = <&ccu RST_BUS_DE_BE>;
 650
 651                         ports {
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654
 655                                 be0_in: port@0 {
 656                                         reg = <0>;
 657
 658                                         be0_in_fe0: endpoint {
 659                                                 remote-endpoint = <&fe0_out_be0>;
 660                                         };
 661                                 };
 662
 663                                 be0_out: port@1 {
 664                                         reg = <1>;
 665
 666                                         be0_out_drc0: endpoint {
 667                                                 remote-endpoint = <&drc0_in_be0>;
 668                                         };
 669                                 };
 670                         };
 671                 };
 672
 673                 drc0: drc@1e70000 {
 674                         /* compatible gets set in SoC specific dtsi file */
 675                         reg = <0x01e70000 0x10000>;
 676                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 677                         clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
 678                                  <&ccu CLK_DRAM_DRC>;
 679                         clock-names = "ahb", "mod", "ram";
 680                         resets = <&ccu RST_BUS_DRC>;
 681
 682                         assigned-clocks = <&ccu CLK_DRC>;
 683                         assigned-clock-rates = <300000000>;
 684
 685                         ports {
 686                                 #address-cells = <1>;
 687                                 #size-cells = <0>;
 688
 689                                 drc0_in: port@0 {
 690                                         reg = <0>;
 691
 692                                         drc0_in_be0: endpoint {
 693                                                 remote-endpoint = <&be0_out_drc0>;
 694                                         };
 695                                 };
 696
 697                                 drc0_out: port@1 {
 698                                         reg = <1>;
 699
 700                                         drc0_out_tcon0: endpoint {
 701                                                 remote-endpoint = <&tcon0_in_drc0>;
 702                                         };
 703                                 };
 704                         };
 705                 };
 706
 707                 rtc: rtc@1f00000 {
 708                         compatible = "allwinner,sun8i-a23-rtc";
 709                         reg = <0x01f00000 0x400>;
 710                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 712                         clock-output-names = "osc32k", "osc32k-out";
 713                         clocks = <&ext_osc32k>;
 714                         #clock-cells = <1>;
 715                 };
 716
 717                 nmi_intc: interrupt-controller@1f00c00 {
 718                         compatible = "allwinner,sun6i-a31-r-intc";
 719                         interrupt-controller;
 720                         #interrupt-cells = <2>;
 721                         reg = <0x01f00c00 0x400>;
 722                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 723                 };
 724
 725                 prcm@1f01400 {
 726                         compatible = "allwinner,sun8i-a23-prcm";
 727                         reg = <0x01f01400 0x200>;
 728
 729                         ar100: ar100_clk {
 730                                 compatible = "fixed-factor-clock";
 731                                 #clock-cells = <0>;
 732                                 clock-div = <1>;
 733                                 clock-mult = <1>;
 734                                 clocks = <&osc24M>;
 735                                 clock-output-names = "ar100";
 736                         };
 737
 738                         ahb0: ahb0_clk {
 739                                 compatible = "fixed-factor-clock";
 740                                 #clock-cells = <0>;
 741                                 clock-div = <1>;
 742                                 clock-mult = <1>;
 743                                 clocks = <&ar100>;
 744                                 clock-output-names = "ahb0";
 745                         };
 746
 747                         apb0: apb0_clk {
 748                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 749                                 #clock-cells = <0>;
 750                                 clocks = <&ahb0>;
 751                                 clock-output-names = "apb0";
 752                         };
 753
 754                         apb0_gates: apb0_gates_clk {
 755                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 756                                 #clock-cells = <1>;
 757                                 clocks = <&apb0>;
 758                                 clock-output-names = "apb0_pio", "apb0_timer",
 759                                                 "apb0_rsb", "apb0_uart",
 760                                                 "apb0_i2c";
 761                         };
 762
 763                         apb0_rst: apb0_rst {
 764                                 compatible = "allwinner,sun6i-a31-clock-reset";
 765                                 #reset-cells = <1>;
 766                         };
 767
 768                         codec_analog: codec-analog {
 769                                 compatible = "allwinner,sun8i-a23-codec-analog";
 770                         };
 771                 };
 772
 773                 cpucfg@1f01c00 {
 774                         compatible = "allwinner,sun8i-a23-cpuconfig";
 775                         reg = <0x01f01c00 0x300>;
 776                 };
 777
 778                 r_uart: serial@1f02800 {
 779                         compatible = "snps,dw-apb-uart";
 780                         reg = <0x01f02800 0x400>;
 781                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 782                         reg-shift = <2>;
 783                         reg-io-width = <4>;
 784                         clocks = <&apb0_gates 4>;
 785                         resets = <&apb0_rst 4>;
 786                         status = "disabled";
 787                 };
 788
 789                 r_i2c: i2c@1f02400 {
 790                         compatible = "allwinner,sun8i-a23-i2c",
 791                                      "allwinner,sun6i-a31-i2c";
 792                         reg = <0x01f02400 0x400>;
 793                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 794                         pinctrl-names = "default";
 795                         pinctrl-0 = <&r_i2c_pins>;
 796                         clocks = <&apb0_gates 6>;
 797                         resets = <&apb0_rst 6>;
 798                         status = "disabled";
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                 };
 802
 803                 r_pio: pinctrl@1f02c00 {
 804                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 805                         reg = <0x01f02c00 0x400>;
 806                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 807                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 808                         clock-names = "apb", "hosc", "losc";
 809                         resets = <&apb0_rst 0>;
 810                         gpio-controller;
 811                         interrupt-controller;
 812                         #interrupt-cells = <3>;
 813                         #gpio-cells = <3>;
 814
 815                         r_i2c_pins: r-i2c-pins {
 816                                 pins = "PL0", "PL1";
 817                                 function = "s_i2c";
 818                                 bias-pull-up;
 819                         };
 820
 821                         r_rsb_pins: r-rsb-pins {
 822                                 pins = "PL0", "PL1";
 823                                 function = "s_rsb";
 824                                 drive-strength = <20>;
 825                                 bias-pull-up;
 826                         };
 827
 828                         r_uart_pins_a: r-uart-pins {
 829                                 pins = "PL2", "PL3";
 830                                 function = "s_uart";
 831                         };
 832                 };
 833
 834                 r_rsb: rsb@1f03400 {
 835                         compatible = "allwinner,sun8i-a23-rsb";
 836                         reg = <0x01f03400 0x400>;
 837                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&apb0_gates 3>;
 839                         clock-frequency = <3000000>;
 840                         resets = <&apb0_rst 3>;
 841                         pinctrl-names = "default";
 842                         pinctrl-0 = <&r_rsb_pins>;
 843                         status = "disabled";
 844                         #address-cells = <1>;
 845                         #size-cells = <0>;
 846                 };
 847         };
 848 };