2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 #include <dt-bindings/reset/sun6i-a31-ccu.h>
55 interrupt-parent = <&gic>;
66 simplefb_hdmi: framebuffer@0 {
67 compatible = "allwinner,simple-framebuffer",
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
77 simplefb_lcd: framebuffer@1 {
78 compatible = "allwinner,simple-framebuffer",
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 clock-frequency = <24000000>;
95 arm,cpu-registers-not-fw-configured;
99 enable-method = "allwinner,sun6i-a31";
100 #address-cells = <1>;
104 compatible = "arm,cortex-a7";
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
118 cooling-max-level = <3>;
122 compatible = "arm,cortex-a7";
128 compatible = "arm,cortex-a7";
134 compatible = "arm,cortex-a7";
143 polling-delay-passive = <250>;
144 polling-delay = <1000>;
145 thermal-sensors = <&rtp>;
149 trip = <&cpu_alert0>;
150 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
155 cpu_alert0: cpu_alert0 {
157 temperature = <70000>;
164 temperature = <100000>;
173 reg = <0x40000000 0x80000000>;
177 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
178 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
185 #address-cells = <1>;
191 compatible = "fixed-clock";
192 clock-frequency = <24000000>;
197 compatible = "fixed-clock";
198 clock-frequency = <32768>;
199 clock-output-names = "osc32k";
203 * The following two are dummy clocks, placeholders
204 * used in the gmac_tx clock. The gmac driver will
205 * choose one parent depending on the PHY interface
206 * mode, using clk_set_rate auto-reparenting.
208 * The actual TX clock rate is not controlled by the
211 mii_phy_tx_clk: clk@1 {
213 compatible = "fixed-clock";
214 clock-frequency = <25000000>;
215 clock-output-names = "mii_phy_tx";
218 gmac_int_tx_clk: clk@2 {
220 compatible = "fixed-clock";
221 clock-frequency = <125000000>;
222 clock-output-names = "gmac_int_tx";
225 gmac_tx_clk: clk@01c200d0 {
227 compatible = "allwinner,sun7i-a20-gmac-clk";
228 reg = <0x01c200d0 0x4>;
229 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
230 clock-output-names = "gmac_tx";
235 compatible = "allwinner,sun6i-a31-display-engine";
236 allwinner,pipelines = <&fe0>;
241 compatible = "simple-bus";
242 #address-cells = <1>;
246 dma: dma-controller@01c02000 {
247 compatible = "allwinner,sun6i-a31-dma";
248 reg = <0x01c02000 0x1000>;
249 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&ccu CLK_AHB1_DMA>;
251 resets = <&ccu RST_AHB1_DMA>;
255 tcon0: lcd-controller@01c0c000 {
256 compatible = "allwinner,sun6i-a31-tcon";
257 reg = <0x01c0c000 0x1000>;
258 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
259 resets = <&ccu RST_AHB1_LCD0>;
261 clocks = <&ccu CLK_AHB1_LCD0>,
267 clock-output-names = "tcon0-pixel-clock";
271 #address-cells = <1>;
275 #address-cells = <1>;
279 tcon0_in_drc0: endpoint@0 {
281 remote-endpoint = <&drc0_out_tcon0>;
286 #address-cells = <1>;
294 compatible = "allwinner,sun7i-a20-mmc";
295 reg = <0x01c0f000 0x1000>;
296 clocks = <&ccu CLK_AHB1_MMC0>,
298 <&ccu CLK_MMC0_OUTPUT>,
299 <&ccu CLK_MMC0_SAMPLE>;
304 resets = <&ccu RST_AHB1_MMC0>;
306 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
308 #address-cells = <1>;
313 compatible = "allwinner,sun7i-a20-mmc";
314 reg = <0x01c10000 0x1000>;
315 clocks = <&ccu CLK_AHB1_MMC1>,
317 <&ccu CLK_MMC1_OUTPUT>,
318 <&ccu CLK_MMC1_SAMPLE>;
323 resets = <&ccu RST_AHB1_MMC1>;
325 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
332 compatible = "allwinner,sun7i-a20-mmc";
333 reg = <0x01c11000 0x1000>;
334 clocks = <&ccu CLK_AHB1_MMC2>,
336 <&ccu CLK_MMC2_OUTPUT>,
337 <&ccu CLK_MMC2_SAMPLE>;
342 resets = <&ccu RST_AHB1_MMC2>;
344 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
351 compatible = "allwinner,sun7i-a20-mmc";
352 reg = <0x01c12000 0x1000>;
353 clocks = <&ccu CLK_AHB1_MMC3>,
355 <&ccu CLK_MMC3_OUTPUT>,
356 <&ccu CLK_MMC3_SAMPLE>;
361 resets = <&ccu RST_AHB1_MMC3>;
363 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
369 usb_otg: usb@01c19000 {
370 compatible = "allwinner,sun6i-a31-musb";
371 reg = <0x01c19000 0x0400>;
372 clocks = <&ccu CLK_AHB1_OTG>;
373 resets = <&ccu RST_AHB1_OTG>;
374 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "mc";
378 extcon = <&usbphy 0>;
382 usbphy: phy@01c19400 {
383 compatible = "allwinner,sun6i-a31-usb-phy";
384 reg = <0x01c19400 0x10>,
387 reg-names = "phy_ctrl",
390 clocks = <&ccu CLK_USB_PHY0>,
393 clock-names = "usb0_phy",
396 resets = <&ccu RST_USB_PHY0>,
399 reset-names = "usb0_reset",
406 ehci0: usb@01c1a000 {
407 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
408 reg = <0x01c1a000 0x100>;
409 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&ccu CLK_AHB1_EHCI0>;
411 resets = <&ccu RST_AHB1_EHCI0>;
417 ohci0: usb@01c1a400 {
418 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
419 reg = <0x01c1a400 0x100>;
420 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
422 resets = <&ccu RST_AHB1_OHCI0>;
428 ehci1: usb@01c1b000 {
429 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
430 reg = <0x01c1b000 0x100>;
431 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_AHB1_EHCI1>;
433 resets = <&ccu RST_AHB1_EHCI1>;
439 ohci1: usb@01c1b400 {
440 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
441 reg = <0x01c1b400 0x100>;
442 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
444 resets = <&ccu RST_AHB1_OHCI1>;
450 ohci2: usb@01c1c400 {
451 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
452 reg = <0x01c1c400 0x100>;
453 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
455 resets = <&ccu RST_AHB1_OHCI2>;
459 ccu: clock@01c20000 {
460 compatible = "allwinner,sun6i-a31-ccu";
461 reg = <0x01c20000 0x400>;
462 clocks = <&osc24M>, <&osc32k>;
463 clock-names = "hosc", "losc";
468 pio: pinctrl@01c20800 {
469 compatible = "allwinner,sun6i-a31-pinctrl";
470 reg = <0x01c20800 0x400>;
471 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
476 clock-names = "apb", "hosc", "losc";
478 interrupt-controller;
479 #interrupt-cells = <3>;
482 gmac_pins_gmii_a: gmac_gmii@0 {
483 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
484 "PA4", "PA5", "PA6", "PA7",
485 "PA8", "PA9", "PA10", "PA11",
486 "PA12", "PA13", "PA14", "PA15",
487 "PA16", "PA17", "PA18", "PA19",
488 "PA20", "PA21", "PA22", "PA23",
489 "PA24", "PA25", "PA26", "PA27";
490 allwinner,function = "gmac";
492 * data lines in GMII mode run at 125MHz and
493 * might need a higher signal drive strength
495 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
496 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
499 gmac_pins_mii_a: gmac_mii@0 {
500 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
501 "PA8", "PA9", "PA11",
502 "PA12", "PA13", "PA14", "PA19",
503 "PA20", "PA21", "PA22", "PA23",
504 "PA24", "PA26", "PA27";
505 allwinner,function = "gmac";
506 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
507 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
510 gmac_pins_rgmii_a: gmac_rgmii@0 {
511 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
512 "PA9", "PA10", "PA11",
513 "PA12", "PA13", "PA14", "PA19",
514 "PA20", "PA25", "PA26", "PA27";
515 allwinner,function = "gmac";
517 * data lines in RGMII mode use DDR mode
518 * and need a higher signal drive strength
520 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
521 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
524 i2c0_pins_a: i2c0@0 {
525 allwinner,pins = "PH14", "PH15";
526 allwinner,function = "i2c0";
527 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
528 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
531 i2c1_pins_a: i2c1@0 {
532 allwinner,pins = "PH16", "PH17";
533 allwinner,function = "i2c1";
534 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
535 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
538 i2c2_pins_a: i2c2@0 {
539 allwinner,pins = "PH18", "PH19";
540 allwinner,function = "i2c2";
541 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
542 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
545 lcd0_rgb888_pins: lcd0_rgb888 {
546 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
547 "PD4", "PD5", "PD6", "PD7",
548 "PD8", "PD9", "PD10", "PD11",
549 "PD12", "PD13", "PD14", "PD15",
550 "PD16", "PD17", "PD18", "PD19",
551 "PD20", "PD21", "PD22", "PD23",
552 "PD24", "PD25", "PD26", "PD27";
553 allwinner,function = "lcd0";
554 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
555 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
558 mmc0_pins_a: mmc0@0 {
559 allwinner,pins = "PF0", "PF1", "PF2",
561 allwinner,function = "mmc0";
562 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
563 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
566 mmc1_pins_a: mmc1@0 {
567 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
569 allwinner,function = "mmc1";
570 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
571 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
574 mmc2_pins_a: mmc2@0 {
575 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
577 allwinner,function = "mmc2";
578 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
579 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
582 mmc2_8bit_emmc_pins: mmc2@1 {
583 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
584 "PC10", "PC11", "PC12",
585 "PC13", "PC14", "PC15",
587 allwinner,function = "mmc2";
588 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
589 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
592 mmc3_8bit_emmc_pins: mmc3@1 {
593 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
594 "PC10", "PC11", "PC12",
595 "PC13", "PC14", "PC15",
597 allwinner,function = "mmc3";
598 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
599 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
602 uart0_pins_a: uart0@0 {
603 allwinner,pins = "PH20", "PH21";
604 allwinner,function = "uart0";
605 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
606 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
611 compatible = "allwinner,sun4i-a10-timer";
612 reg = <0x01c20c00 0xa0>;
613 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
621 wdt1: watchdog@01c20ca0 {
622 compatible = "allwinner,sun6i-a31-wdt";
623 reg = <0x01c20ca0 0x20>;
626 lradc: lradc@01c22800 {
627 compatible = "allwinner,sun4i-a10-lradc-keys";
628 reg = <0x01c22800 0x100>;
629 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
634 compatible = "allwinner,sun6i-a31-ts";
635 reg = <0x01c25000 0x100>;
636 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
637 #thermal-sensor-cells = <0>;
640 uart0: serial@01c28000 {
641 compatible = "snps,dw-apb-uart";
642 reg = <0x01c28000 0x400>;
643 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&ccu CLK_APB2_UART0>;
647 resets = <&ccu RST_APB2_UART0>;
648 dmas = <&dma 6>, <&dma 6>;
649 dma-names = "rx", "tx";
653 uart1: serial@01c28400 {
654 compatible = "snps,dw-apb-uart";
655 reg = <0x01c28400 0x400>;
656 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&ccu CLK_APB2_UART1>;
660 resets = <&ccu RST_APB2_UART1>;
661 dmas = <&dma 7>, <&dma 7>;
662 dma-names = "rx", "tx";
666 uart2: serial@01c28800 {
667 compatible = "snps,dw-apb-uart";
668 reg = <0x01c28800 0x400>;
669 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&ccu CLK_APB2_UART2>;
673 resets = <&ccu RST_APB2_UART2>;
674 dmas = <&dma 8>, <&dma 8>;
675 dma-names = "rx", "tx";
679 uart3: serial@01c28c00 {
680 compatible = "snps,dw-apb-uart";
681 reg = <0x01c28c00 0x400>;
682 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&ccu CLK_APB2_UART3>;
686 resets = <&ccu RST_APB2_UART3>;
687 dmas = <&dma 9>, <&dma 9>;
688 dma-names = "rx", "tx";
692 uart4: serial@01c29000 {
693 compatible = "snps,dw-apb-uart";
694 reg = <0x01c29000 0x400>;
695 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&ccu CLK_APB2_UART4>;
699 resets = <&ccu RST_APB2_UART4>;
700 dmas = <&dma 10>, <&dma 10>;
701 dma-names = "rx", "tx";
705 uart5: serial@01c29400 {
706 compatible = "snps,dw-apb-uart";
707 reg = <0x01c29400 0x400>;
708 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&ccu CLK_APB2_UART5>;
712 resets = <&ccu RST_APB2_UART5>;
713 dmas = <&dma 22>, <&dma 22>;
714 dma-names = "rx", "tx";
719 compatible = "allwinner,sun6i-a31-i2c";
720 reg = <0x01c2ac00 0x400>;
721 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&ccu CLK_APB2_I2C0>;
723 resets = <&ccu RST_APB2_I2C0>;
725 #address-cells = <1>;
730 compatible = "allwinner,sun6i-a31-i2c";
731 reg = <0x01c2b000 0x400>;
732 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&ccu CLK_APB2_I2C1>;
734 resets = <&ccu RST_APB2_I2C1>;
736 #address-cells = <1>;
741 compatible = "allwinner,sun6i-a31-i2c";
742 reg = <0x01c2b400 0x400>;
743 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&ccu CLK_APB2_I2C2>;
745 resets = <&ccu RST_APB2_I2C2>;
747 #address-cells = <1>;
752 compatible = "allwinner,sun6i-a31-i2c";
753 reg = <0x01c2b800 0x400>;
754 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&ccu CLK_APB2_I2C3>;
756 resets = <&ccu RST_APB2_I2C3>;
758 #address-cells = <1>;
762 gmac: ethernet@01c30000 {
763 compatible = "allwinner,sun7i-a20-gmac";
764 reg = <0x01c30000 0x1054>;
765 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
766 interrupt-names = "macirq";
767 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
768 clock-names = "stmmaceth", "allwinner_gmac_tx";
769 resets = <&ccu RST_AHB1_EMAC>;
770 reset-names = "stmmaceth";
773 snps,force_sf_dma_mode;
775 #address-cells = <1>;
779 crypto: crypto-engine@01c15000 {
780 compatible = "allwinner,sun4i-a10-crypto";
781 reg = <0x01c15000 0x1000>;
782 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
784 clock-names = "ahb", "mod";
785 resets = <&ccu RST_AHB1_SS>;
789 codec: codec@01c22c00 {
790 #sound-dai-cells = <0>;
791 compatible = "allwinner,sun6i-a31-codec";
792 reg = <0x01c22c00 0x400>;
793 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
795 clock-names = "apb", "codec";
796 resets = <&ccu RST_APB1_CODEC>;
797 dmas = <&dma 15>, <&dma 15>;
798 dma-names = "rx", "tx";
803 compatible = "allwinner,sun6i-a31-hstimer",
804 "allwinner,sun7i-a20-hstimer";
805 reg = <0x01c60000 0x1000>;
806 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&ccu CLK_AHB1_HSTIMER>;
811 resets = <&ccu RST_AHB1_HSTIMER>;
815 compatible = "allwinner,sun6i-a31-spi";
816 reg = <0x01c68000 0x1000>;
817 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
819 clock-names = "ahb", "mod";
820 dmas = <&dma 23>, <&dma 23>;
821 dma-names = "rx", "tx";
822 resets = <&ccu RST_AHB1_SPI0>;
827 compatible = "allwinner,sun6i-a31-spi";
828 reg = <0x01c69000 0x1000>;
829 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
831 clock-names = "ahb", "mod";
832 dmas = <&dma 24>, <&dma 24>;
833 dma-names = "rx", "tx";
834 resets = <&ccu RST_AHB1_SPI1>;
839 compatible = "allwinner,sun6i-a31-spi";
840 reg = <0x01c6a000 0x1000>;
841 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
843 clock-names = "ahb", "mod";
844 dmas = <&dma 25>, <&dma 25>;
845 dma-names = "rx", "tx";
846 resets = <&ccu RST_AHB1_SPI2>;
851 compatible = "allwinner,sun6i-a31-spi";
852 reg = <0x01c6b000 0x1000>;
853 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
855 clock-names = "ahb", "mod";
856 dmas = <&dma 26>, <&dma 26>;
857 dma-names = "rx", "tx";
858 resets = <&ccu RST_AHB1_SPI3>;
862 gic: interrupt-controller@01c81000 {
863 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
864 reg = <0x01c81000 0x1000>,
868 interrupt-controller;
869 #interrupt-cells = <3>;
870 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
873 fe0: display-frontend@01e00000 {
874 compatible = "allwinner,sun6i-a31-display-frontend";
875 reg = <0x01e00000 0x20000>;
876 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
879 clock-names = "ahb", "mod",
881 resets = <&ccu RST_AHB1_FE0>;
884 #address-cells = <1>;
888 #address-cells = <1>;
892 fe0_out_be0: endpoint@0 {
894 remote-endpoint = <&be0_in_fe0>;
900 be0: display-backend@01e60000 {
901 compatible = "allwinner,sun6i-a31-display-backend";
902 reg = <0x01e60000 0x10000>;
903 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
906 clock-names = "ahb", "mod",
908 resets = <&ccu RST_AHB1_BE0>;
910 assigned-clocks = <&ccu CLK_BE0>;
911 assigned-clock-rates = <300000000>;
914 #address-cells = <1>;
918 #address-cells = <1>;
922 be0_in_fe0: endpoint@0 {
924 remote-endpoint = <&fe0_out_be0>;
929 #address-cells = <1>;
933 be0_out_drc0: endpoint@0 {
935 remote-endpoint = <&drc0_in_be0>;
942 compatible = "allwinner,sun6i-a31-drc";
943 reg = <0x01e70000 0x10000>;
944 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
946 <&ccu CLK_DRAM_DRC0>;
947 clock-names = "ahb", "mod",
949 resets = <&ccu RST_AHB1_DRC0>;
951 assigned-clocks = <&ccu CLK_IEP_DRC0>;
952 assigned-clock-rates = <300000000>;
955 #address-cells = <1>;
959 #address-cells = <1>;
963 drc0_in_be0: endpoint@0 {
965 remote-endpoint = <&be0_out_drc0>;
970 #address-cells = <1>;
974 drc0_out_tcon0: endpoint@0 {
976 remote-endpoint = <&tcon0_in_drc0>;
983 compatible = "allwinner,sun6i-a31-rtc";
984 reg = <0x01f00000 0x54>;
985 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
989 nmi_intc: interrupt-controller@01f00c0c {
990 compatible = "allwinner,sun6i-a31-sc-nmi";
991 interrupt-controller;
992 #interrupt-cells = <2>;
993 reg = <0x01f00c0c 0x38>;
994 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
998 compatible = "allwinner,sun6i-a31-prcm";
999 reg = <0x01f01400 0x200>;
1002 compatible = "allwinner,sun6i-a31-ar100-clk";
1004 clocks = <&osc32k>, <&osc24M>,
1005 <&ccu CLK_PLL_PERIPH>,
1006 <&ccu CLK_PLL_PERIPH>;
1007 clock-output-names = "ar100";
1011 compatible = "fixed-factor-clock";
1016 clock-output-names = "ahb0";
1020 compatible = "allwinner,sun6i-a31-apb0-clk";
1023 clock-output-names = "apb0";
1026 apb0_gates: apb0_gates_clk {
1027 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1030 clock-output-names = "apb0_pio", "apb0_ir",
1031 "apb0_timer", "apb0_p2wi",
1032 "apb0_uart", "apb0_1wire",
1038 compatible = "allwinner,sun4i-a10-mod0-clk";
1039 clocks = <&osc32k>, <&osc24M>;
1040 clock-output-names = "ir";
1043 apb0_rst: apb0_rst {
1044 compatible = "allwinner,sun6i-a31-clock-reset";
1050 compatible = "allwinner,sun6i-a31-cpuconfig";
1051 reg = <0x01f01c00 0x300>;
1055 compatible = "allwinner,sun5i-a13-ir";
1056 clocks = <&apb0_gates 1>, <&ir_clk>;
1057 clock-names = "apb", "ir";
1058 resets = <&apb0_rst 1>;
1059 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1060 reg = <0x01f02000 0x40>;
1061 status = "disabled";
1064 r_pio: pinctrl@01f02c00 {
1065 compatible = "allwinner,sun6i-a31-r-pinctrl";
1066 reg = <0x01f02c00 0x400>;
1067 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1070 clock-names = "apb", "hosc", "losc";
1071 resets = <&apb0_rst 0>;
1073 interrupt-controller;
1074 #interrupt-cells = <3>;
1079 allwinner,pins = "PL4";
1080 allwinner,function = "s_ir";
1081 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1082 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1086 allwinner,pins = "PL0", "PL1";
1087 allwinner,function = "s_p2wi";
1088 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1089 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1093 p2wi: i2c@01f03400 {
1094 compatible = "allwinner,sun6i-a31-p2wi";
1095 reg = <0x01f03400 0x400>;
1096 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&apb0_gates 3>;
1098 clock-frequency = <100000>;
1099 resets = <&apb0_rst 3>;
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&p2wi_pins>;
1102 status = "disabled";
1103 #address-cells = <1>;