arch/arm/boot/dts/stih407-family.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-pinctrl.dtsi"
  10 #include <dt-bindings/mfd/st-lpc.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/reset/stih407-resets.h>
  13 #include <dt-bindings/interrupt-controller/irq-st.h>
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         reserved-memory {
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges;
  22
  23                 gp0_reserved: rproc@45000000 {
  24                         compatible = "shared-dma-pool";
  25                         reg = <0x45000000 0x00400000>;
  26                         no-map;
  27                 };
  28
  29                 delta_reserved: rproc@44000000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x44000000 0x01000000>;
  32                         no-map;
  33                 };
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <0>;
  43
  44                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  45                         cpu-release-addr = <0x94100A4>;
  46
  47                                          /* kHz     uV   */
  48                         operating-points = <1500000 0
  49                                             1200000 0
  50                                             800000  0
  51                                             500000  0>;
  52
  53                         clocks = <&clk_m_a9>;
  54                         clock-names = "cpu";
  55                         clock-latency = <100000>;
  56                         cpu0-supply = <&pwm_regulator>;
  57                         st,syscfg = <&syscfg_core 0x8e0>;
  58                 };
  59                 cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a9";
  62                         reg = <1>;
  63
  64                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  65                         cpu-release-addr = <0x94100A4>;
  66
  67                                          /* kHz     uV   */
  68                         operating-points = <1500000 0
  69                                             1200000 0
  70                                             800000  0
  71                                             500000  0>;
  72                 };
  73         };
  74
  75         intc: interrupt-controller@8761000 {
  76                 compatible = "arm,cortex-a9-gic";
  77                 #interrupt-cells = <3>;
  78                 interrupt-controller;
  79                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
  80         };
  81
  82         scu@8760000 {
  83                 compatible = "arm,cortex-a9-scu";
  84                 reg = <0x08760000 0x1000>;
  85         };
  86
  87         timer@8760200 {
  88                 interrupt-parent = <&intc>;
  89                 compatible = "arm,cortex-a9-global-timer";
  90                 reg = <0x08760200 0x100>;
  91                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  92                 clocks = <&arm_periph_clk>;
  93         };
  94
  95         l2: cache-controller@8762000 {
  96                 compatible = "arm,pl310-cache";
  97                 reg = <0x08762000 0x1000>;
  98                 arm,data-latency = <3 3 3>;
  99                 arm,tag-latency = <2 2 2>;
 100                 cache-unified;
 101                 cache-level = <2>;
 102         };
 103
 104         arm-pmu {
 105                 interrupt-parent = <&intc>;
 106                 compatible = "arm,cortex-a9-pmu";
 107                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 108         };
 109
 110         pwm_regulator: pwm-regulator {
 111                 compatible = "pwm-regulator";
 112                 pwms = <&pwm1 3 8448>;
 113                 regulator-name = "CPU_1V0_AVS";
 114                 regulator-min-microvolt = <784000>;
 115                 regulator-max-microvolt = <1299000>;
 116                 regulator-always-on;
 117                 max-duty-cycle = <255>;
 118                 status = "okay";
 119         };
 120
 121         soc {
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 interrupt-parent = <&intc>;
 125                 ranges;
 126                 compatible = "simple-bus";
 127
 128                 restart: restart-controller@0 {
 129                         compatible = "st,stih407-restart";
 130                         reg = <0 0>;
 131                         st,syscfg = <&syscfg_sbc_reg>;
 132                         status = "okay";
 133                 };
 134
 135                 powerdown: powerdown-controller@0 {
 136                         compatible = "st,stih407-powerdown";
 137                         reg = <0 0>;
 138                         #reset-cells = <1>;
 139                 };
 140
 141                 softreset: softreset-controller@0 {
 142                         compatible = "st,stih407-softreset";
 143                         reg = <0 0>;
 144                         #reset-cells = <1>;
 145                 };
 146
 147                 picophyreset: picophyreset-controller@0 {
 148                         compatible = "st,stih407-picophyreset";
 149                         reg = <0 0>;
 150                         #reset-cells = <1>;
 151                 };
 152
 153                 syscfg_sbc: sbc-syscfg@9620000 {
 154                         compatible = "st,stih407-sbc-syscfg", "syscon";
 155                         reg = <0x9620000 0x1000>;
 156                 };
 157
 158                 syscfg_front: front-syscfg@9280000 {
 159                         compatible = "st,stih407-front-syscfg", "syscon";
 160                         reg = <0x9280000 0x1000>;
 161                 };
 162
 163                 syscfg_rear: rear-syscfg@9290000 {
 164                         compatible = "st,stih407-rear-syscfg", "syscon";
 165                         reg = <0x9290000 0x1000>;
 166                 };
 167
 168                 syscfg_flash: flash-syscfg@92a0000 {
 169                         compatible = "st,stih407-flash-syscfg", "syscon";
 170                         reg = <0x92a0000 0x1000>;
 171                 };
 172
 173                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
 174                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
 175                         reg = <0x9600000 0x1000>;
 176                 };
 177
 178                 syscfg_core: core-syscfg@92b0000 {
 179                         compatible = "st,stih407-core-syscfg", "syscon";
 180                         reg = <0x92b0000 0x1000>;
 181
 182                         sti_sasg_codec: sti-sasg-codec {
 183                                 compatible = "st,stih407-sas-codec";
 184                                 #sound-dai-cells = <1>;
 185                                 status = "disabled";
 186                                 st,syscfg = <&syscfg_core>;
 187                         };
 188                 };
 189
 190                 syscfg_lpm: lpm-syscfg@94b5100 {
 191                         compatible = "st,stih407-lpm-syscfg", "syscon";
 192                         reg = <0x94b5100 0x1000>;
 193                 };
 194
 195                 irq-syscfg@0 {
 196                         compatible    = "st,stih407-irq-syscfg";
 197                         reg = <0 0>;
 198                         st,syscfg     = <&syscfg_core>;
 199                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
 200                                         <ST_IRQ_SYSCFG_PMU_1>;
 201                         st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
 202                                         <ST_IRQ_SYSCFG_DISABLED>;
 203                 };
 204
 205                 /* Display */
 206                 vtg_main: sti-vtg-main@8d02800 {
 207                         compatible = "st,vtg";
 208                         reg = <0x8d02800 0x200>;
 209                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
 210                 };
 211
 212                 vtg_aux: sti-vtg-aux@8d00200 {
 213                         compatible = "st,vtg";
 214                         reg = <0x8d00200 0x100>;
 215                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
 216                 };
 217
 218                 serial@9830000 {
 219                         compatible = "st,asc";
 220                         reg = <0x9830000 0x2c>;
 221                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
 222                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 223                         /* Pinctrl moved out to a per-board configuration */
 224
 225                         status = "disabled";
 226                 };
 227
 228                 serial@9831000 {
 229                         compatible = "st,asc";
 230                         reg = <0x9831000 0x2c>;
 231                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&pinctrl_serial1>;
 234                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 235
 236                         status = "disabled";
 237                 };
 238
 239                 serial@9832000 {
 240                         compatible = "st,asc";
 241                         reg = <0x9832000 0x2c>;
 242                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 243                         pinctrl-names = "default";
 244                         pinctrl-0 = <&pinctrl_serial2>;
 245                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 246
 247                         status = "disabled";
 248                 };
 249
 250                 /* SBC_ASC0 - UART10 */
 251                 sbc_serial0: serial@9530000 {
 252                         compatible = "st,asc";
 253                         reg = <0x9530000 0x2c>;
 254                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
 255                         pinctrl-names = "default";
 256                         pinctrl-0 = <&pinctrl_sbc_serial0>;
 257                         clocks = <&clk_sysin>;
 258
 259                         status = "disabled";
 260                 };
 261
 262                 serial@9531000 {
 263                         compatible = "st,asc";
 264                         reg = <0x9531000 0x2c>;
 265                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
 266                         pinctrl-names = "default";
 267                         pinctrl-0 = <&pinctrl_sbc_serial1>;
 268                         clocks = <&clk_sysin>;
 269
 270                         status = "disabled";
 271                 };
 272
 273                 i2c@9840000 {
 274                         compatible = "st,comms-ssc4-i2c";
 275                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 276                         reg = <0x9840000 0x110>;
 277                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 278                         clock-names = "ssc";
 279                         clock-frequency = <400000>;
 280                         pinctrl-names = "default";
 281                         pinctrl-0 = <&pinctrl_i2c0_default>;
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284
 285                         status = "disabled";
 286                 };
 287
 288                 i2c@9841000 {
 289                         compatible = "st,comms-ssc4-i2c";
 290                         reg = <0x9841000 0x110>;
 291                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 293                         clock-names = "ssc";
 294                         clock-frequency = <400000>;
 295                         pinctrl-names = "default";
 296                         pinctrl-0 = <&pinctrl_i2c1_default>;
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299
 300                         status = "disabled";
 301                 };
 302
 303                 i2c@9842000 {
 304                         compatible = "st,comms-ssc4-i2c";
 305                         reg = <0x9842000 0x110>;
 306                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 308                         clock-names = "ssc";
 309                         clock-frequency = <400000>;
 310                         pinctrl-names = "default";
 311                         pinctrl-0 = <&pinctrl_i2c2_default>;
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314
 315                         status = "disabled";
 316                 };
 317
 318                 i2c@9843000 {
 319                         compatible = "st,comms-ssc4-i2c";
 320                         reg = <0x9843000 0x110>;
 321                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 323                         clock-names = "ssc";
 324                         clock-frequency = <400000>;
 325                         pinctrl-names = "default";
 326                         pinctrl-0 = <&pinctrl_i2c3_default>;
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329
 330                         status = "disabled";
 331                 };
 332
 333                 i2c@9844000 {
 334                         compatible = "st,comms-ssc4-i2c";
 335                         reg = <0x9844000 0x110>;
 336                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 338                         clock-names = "ssc";
 339                         clock-frequency = <400000>;
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&pinctrl_i2c4_default>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344
 345                         status = "disabled";
 346                 };
 347
 348                 i2c@9845000 {
 349                         compatible = "st,comms-ssc4-i2c";
 350                         reg = <0x9845000 0x110>;
 351                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 352                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 353                         clock-names = "ssc";
 354                         clock-frequency = <400000>;
 355                         pinctrl-names = "default";
 356                         pinctrl-0 = <&pinctrl_i2c5_default>;
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359
 360                         status = "disabled";
 361                 };
 362
 363
 364                 /* SSCs on SBC */
 365                 i2c@9540000 {
 366                         compatible = "st,comms-ssc4-i2c";
 367                         reg = <0x9540000 0x110>;
 368                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&clk_sysin>;
 370                         clock-names = "ssc";
 371                         clock-frequency = <400000>;
 372                         pinctrl-names = "default";
 373                         pinctrl-0 = <&pinctrl_i2c10_default>;
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376
 377                         status = "disabled";
 378                 };
 379
 380                 i2c@9541000 {
 381                         compatible = "st,comms-ssc4-i2c";
 382                         reg = <0x9541000 0x110>;
 383                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&clk_sysin>;
 385                         clock-names = "ssc";
 386                         clock-frequency = <400000>;
 387                         pinctrl-names = "default";
 388                         pinctrl-0 = <&pinctrl_i2c11_default>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391
 392                         status = "disabled";
 393                 };
 394
 395                 usb2_picophy0: phy1@0 {
 396                         compatible = "st,stih407-usb2-phy";
 397                         reg = <0 0>;
 398                         #phy-cells = <0>;
 399                         st,syscfg = <&syscfg_core 0x100 0xf4>;
 400                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 401                                  <&picophyreset STIH407_PICOPHY2_RESET>;
 402                         reset-names = "global", "port";
 403                 };
 404
 405                 miphy28lp_phy: miphy28lp@0 {
 406                         compatible = "st,miphy28lp-phy";
 407                         st,syscfg = <&syscfg_core>;
 408                         #address-cells  = <1>;
 409                         #size-cells     = <1>;
 410                         ranges;
 411                         reg = <0 0>;
 412
 413                         phy_port0: port@9b22000 {
 414                                 reg = <0x9b22000 0xff>,
 415                                       <0x9b09000 0xff>,
 416                                       <0x9b04000 0xff>;
 417                                 reg-names = "sata-up",
 418                                             "pcie-up",
 419                                             "pipew";
 420
 421                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 422                                 #phy-cells = <1>;
 423
 424                                 reset-names = "miphy-sw-rst";
 425                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 426                         };
 427
 428                         phy_port1: port@9b2a000 {
 429                                 reg = <0x9b2a000 0xff>,
 430                                       <0x9b19000 0xff>,
 431                                       <0x9b14000 0xff>;
 432                                 reg-names = "sata-up",
 433                                             "pcie-up",
 434                                             "pipew";
 435
 436                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 437
 438                                 #phy-cells = <1>;
 439
 440                                 reset-names = "miphy-sw-rst";
 441                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 442                         };
 443
 444                         phy_port2: port@8f95000 {
 445                                 reg = <0x8f95000 0xff>,
 446                                       <0x8f90000 0xff>;
 447                                 reg-names = "pipew",
 448                                             "usb3-up";
 449
 450                                 st,syscfg = <0x11c 0x820>;
 451
 452                                 #phy-cells = <1>;
 453
 454                                 reset-names = "miphy-sw-rst";
 455                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 456                         };
 457                 };
 458
 459                 spi@9840000 {
 460                         compatible = "st,comms-ssc4-spi";
 461                         reg = <0x9840000 0x110>;
 462                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 464                         clock-names = "ssc";
 465                         pinctrl-0 = <&pinctrl_spi0_default>;
 466                         pinctrl-names = "default";
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469
 470                         status = "disabled";
 471                 };
 472
 473                 spi@9841000 {
 474                         compatible = "st,comms-ssc4-spi";
 475                         reg = <0x9841000 0x110>;
 476                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 477                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 478                         clock-names = "ssc";
 479                         pinctrl-names = "default";
 480                         pinctrl-0 = <&pinctrl_spi1_default>;
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483
 484                         status = "disabled";
 485                 };
 486
 487                 spi@9842000 {
 488                         compatible = "st,comms-ssc4-spi";
 489                         reg = <0x9842000 0x110>;
 490                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 492                         clock-names = "ssc";
 493                         pinctrl-names = "default";
 494                         pinctrl-0 = <&pinctrl_spi2_default>;
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497
 498                         status = "disabled";
 499                 };
 500
 501                 spi@9843000 {
 502                         compatible = "st,comms-ssc4-spi";
 503                         reg = <0x9843000 0x110>;
 504                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 506                         clock-names = "ssc";
 507                         pinctrl-names = "default";
 508                         pinctrl-0 = <&pinctrl_spi3_default>;
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511
 512                         status = "disabled";
 513                 };
 514
 515                 spi@9844000 {
 516                         compatible = "st,comms-ssc4-spi";
 517                         reg = <0x9844000 0x110>;
 518                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 519                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 520                         clock-names = "ssc";
 521                         pinctrl-names = "default";
 522                         pinctrl-0 = <&pinctrl_spi4_default>;
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525
 526                         status = "disabled";
 527                 };
 528
 529                 /* SBC SSC */
 530                 spi@9540000 {
 531                         compatible = "st,comms-ssc4-spi";
 532                         reg = <0x9540000 0x110>;
 533                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&clk_sysin>;
 535                         clock-names = "ssc";
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&pinctrl_spi10_default>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540
 541                         status = "disabled";
 542                 };
 543
 544                 spi@9541000 {
 545                         compatible = "st,comms-ssc4-spi";
 546                         reg = <0x9541000 0x110>;
 547                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&clk_sysin>;
 549                         clock-names = "ssc";
 550                         pinctrl-names = "default";
 551                         pinctrl-0 = <&pinctrl_spi11_default>;
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554
 555                         status = "disabled";
 556                 };
 557
 558                 spi@9542000 {
 559                         compatible = "st,comms-ssc4-spi";
 560                         reg = <0x9542000 0x110>;
 561                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&clk_sysin>;
 563                         clock-names = "ssc";
 564                         pinctrl-names = "default";
 565                         pinctrl-0 = <&pinctrl_spi12_default>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568
 569                         status = "disabled";
 570                 };
 571
 572                 mmc0: sdhci@9060000 {
 573                         compatible = "st,sdhci-stih407", "st,sdhci";
 574                         status = "disabled";
 575                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
 576                         reg-names = "mmc", "top-mmc-delay";
 577                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
 578                         interrupt-names = "mmcirq";
 579                         pinctrl-names = "default";
 580                         pinctrl-0 = <&pinctrl_mmc0>;
 581                         clock-names = "mmc", "icn";
 582                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
 583                                  <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
 584                         bus-width = <8>;
 585                 };
 586
 587                 mmc1: sdhci@9080000 {
 588                         compatible = "st,sdhci-stih407", "st,sdhci";
 589                         status = "disabled";
 590                         reg = <0x09080000 0x7ff>;
 591                         reg-names = "mmc";
 592                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
 593                         interrupt-names = "mmcirq";
 594                         pinctrl-names = "default";
 595                         pinctrl-0 = <&pinctrl_sd1>;
 596                         clock-names = "mmc", "icn";
 597                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
 598                                  <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
 599                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
 600                         bus-width = <4>;
 601                 };
 602
 603                 /* Watchdog and Real-Time Clock */
 604                 lpc@8787000 {
 605                         compatible = "st,stih407-lpc";
 606                         reg = <0x8787000 0x1000>;
 607                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
 608                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
 609                         timeout-sec = <120>;
 610                         st,syscfg = <&syscfg_core>;
 611                         st,lpc-mode = <ST_LPC_MODE_WDT>;
 612                 };
 613
 614                 lpc@8788000 {
 615                         compatible = "st,stih407-lpc";
 616                         reg = <0x8788000 0x1000>;
 617                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 618                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
 619                         st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
 620                 };
 621
 622                 sata0: sata@9b20000 {
 623                         compatible = "st,ahci";
 624                         reg = <0x9b20000 0x1000>;
 625
 626                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 627                         interrupt-names = "hostc";
 628
 629                         phys = <&phy_port0 PHY_TYPE_SATA>;
 630                         phy-names = "ahci_phy";
 631
 632                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
 633                                  <&softreset STIH407_SATA0_SOFTRESET>,
 634                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
 635                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
 636
 637                         clock-names = "ahci_clk";
 638                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 639
 640                         ports-implemented = <0x1>;
 641
 642                         status = "disabled";
 643                 };
 644
 645                 sata1: sata@9b28000 {
 646                         compatible = "st,ahci";
 647                         reg = <0x9b28000 0x1000>;
 648
 649                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 650                         interrupt-names = "hostc";
 651
 652                         phys = <&phy_port1 PHY_TYPE_SATA>;
 653                         phy-names = "ahci_phy";
 654
 655                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
 656                                  <&softreset STIH407_SATA1_SOFTRESET>,
 657                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
 658                         reset-names = "pwr-dwn",
 659                                       "sw-rst",
 660                                       "pwr-rst";
 661
 662                         clock-names = "ahci_clk";
 663                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 664
 665                         ports-implemented = <0x1>;
 666
 667                         status = "disabled";
 668                 };
 669
 670
 671                 st_dwc3: dwc3@8f94000 {
 672                         compatible      = "st,stih407-dwc3";
 673                         reg             = <0x08f94000 0x1000>, <0x110 0x4>;
 674                         reg-names       = "reg-glue", "syscfg-reg";
 675                         st,syscfg       = <&syscfg_core>;
 676                         resets          = <&powerdown STIH407_USB3_POWERDOWN>,
 677                                           <&softreset STIH407_MIPHY2_SOFTRESET>;
 678                         reset-names     = "powerdown", "softreset";
 679                         #address-cells  = <1>;
 680                         #size-cells     = <1>;
 681                         pinctrl-names   = "default";
 682                         pinctrl-0       = <&pinctrl_usb3>;
 683                         ranges;
 684
 685                         status = "disabled";
 686
 687                         dwc3: dwc3@9900000 {
 688                                 compatible      = "snps,dwc3";
 689                                 reg             = <0x09900000 0x100000>;
 690                                 interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
 691                                 dr_mode         = "host";
 692                                 phy-names       = "usb2-phy", "usb3-phy";
 693                                 phys            = <&usb2_picophy0>,
 694                                                   <&phy_port2 PHY_TYPE_USB3>;
 695                                 snps,dis_u3_susphy_quirk;
 696                         };
 697                 };
 698
 699                 /* COMMS PWM Module */
 700                 pwm0: pwm@9810000 {
 701                         compatible      = "st,sti-pwm";
 702                         #pwm-cells      = <2>;
 703                         reg             = <0x9810000 0x68>;
 704                         interrupts      = <GIC_SPI 128 IRQ_TYPE_NONE>;
 705                         pinctrl-names   = "default";
 706                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
 707                         clock-names     = "pwm";
 708                         clocks          = <&clk_sysin>;
 709                         st,pwm-num-chan = <1>;
 710
 711                         status          = "disabled";
 712                 };
 713
 714                 /* SBC PWM Module */
 715                 pwm1: pwm@9510000 {
 716                         compatible      = "st,sti-pwm";
 717                         #pwm-cells      = <2>;
 718                         reg             = <0x9510000 0x68>;
 719                         interrupts      = <GIC_SPI 131 IRQ_TYPE_NONE>;
 720                         pinctrl-names   = "default";
 721                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
 722                                         &pinctrl_pwm1_chan1_default
 723                                         &pinctrl_pwm1_chan2_default
 724                                         &pinctrl_pwm1_chan3_default>;
 725                         clock-names     = "pwm";
 726                         clocks          = <&clk_sysin>;
 727                         st,pwm-num-chan = <4>;
 728
 729                         status          = "disabled";
 730                 };
 731
 732                 rng10: rng@8a89000 {
 733                         compatible      = "st,rng";
 734                         reg             = <0x08a89000 0x1000>;
 735                         clocks          = <&clk_sysin>;
 736                         status          = "okay";
 737                 };
 738
 739                 rng11: rng@8a8a000 {
 740                         compatible      = "st,rng";
 741                         reg             = <0x08a8a000 0x1000>;
 742                         clocks          = <&clk_sysin>;
 743                         status          = "okay";
 744                 };
 745
 746                 ethernet0: dwmac@9630000 {
 747                         device_type = "network";
 748                         status = "disabled";
 749                         compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 750                         reg = <0x9630000 0x8000>, <0x80 0x4>;
 751                         reg-names = "stmmaceth", "sti-ethconf";
 752
 753                         st,syscon = <&syscfg_sbc_reg 0x80>;
 754                         st,gmac_en;
 755                         resets = <&softreset STIH407_ETH1_SOFTRESET>;
 756                         reset-names = "stmmaceth";
 757
 758                         interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
 759                                      <GIC_SPI 99 IRQ_TYPE_NONE>;
 760                         interrupt-names = "macirq", "eth_wake_irq";
 761
 762                         /* DMA Bus Mode */
 763                         snps,pbl = <8>;
 764
 765                         pinctrl-names = "default";
 766                         pinctrl-0 = <&pinctrl_rgmii1>;
 767
 768                         clock-names = "stmmaceth", "sti-ethclk";
 769                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 770                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
 771                 };
 772
 773                 rng10: rng@8a89000 {
 774                         compatible      = "st,rng";
 775                         reg             = <0x08a89000 0x1000>;
 776                         clocks          = <&clk_sysin>;
 777                         status          = "okay";
 778                 };
 779
 780                 rng11: rng@8a8a000 {
 781                         compatible      = "st,rng";
 782                         reg             = <0x08a8a000 0x1000>;
 783                         clocks          = <&clk_sysin>;
 784                         status          = "okay";
 785                 };
 786
 787                 mailbox0: mailbox@8f00000  {
 788                         compatible      = "st,stih407-mailbox";
 789                         reg             = <0x8f00000 0x1000>;
 790                         interrupts      = <GIC_SPI 1 IRQ_TYPE_NONE>;
 791                         #mbox-cells     = <2>;
 792                         mbox-name       = "a9";
 793                         status          = "okay";
 794                 };
 795
 796                 mailbox1: mailbox@8f01000 {
 797                         compatible      = "st,stih407-mailbox";
 798                         reg             = <0x8f01000 0x1000>;
 799                         #mbox-cells     = <2>;
 800                         mbox-name       = "st231_gp_1";
 801                         status          = "okay";
 802                 };
 803
 804                 mailbox2: mailbox@8f02000 {
 805                         compatible      = "st,stih407-mailbox";
 806                         reg             = <0x8f02000 0x1000>;
 807                         #mbox-cells     = <2>;
 808                         mbox-name       = "st231_gp_0";
 809                         status          = "okay";
 810                 };
 811
 812                 mailbox3: mailbox@8f03000 {
 813                         compatible      = "st,stih407-mailbox";
 814                         reg             = <0x8f03000 0x1000>;
 815                         #mbox-cells     = <2>;
 816                         mbox-name       = "st231_audio_video";
 817                         status          = "okay";
 818                 };
 819
 820                 st231_gp0: st231-gp0@0 {
 821                         compatible      = "st,st231-rproc";
 822                         reg             = <0 0>;
 823                         memory-region   = <&gp0_reserved>;
 824                         resets          = <&softreset STIH407_ST231_GP0_SOFTRESET>;
 825                         reset-names     = "sw_reset";
 826                         clocks          = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
 827                         clock-frequency = <600000000>;
 828                         st,syscfg       = <&syscfg_core 0x22c>;
 829                         #mbox-cells = <1>;
 830                         mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
 831                         mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
 832                 };
 833
 834                 st231_delta: st231-delta@0 {
 835                         compatible      = "st,st231-rproc";
 836                         reg             = <0 0>;
 837                         memory-region   = <&delta_reserved>;
 838                         resets          = <&softreset STIH407_ST231_DMU_SOFTRESET>;
 839                         reset-names     = "sw_reset";
 840                         clocks          = <&clk_s_c0_flexgen CLK_ST231_DMU>;
 841                         clock-frequency = <600000000>;
 842                         st,syscfg       = <&syscfg_core 0x224>;
 843                         #mbox-cells = <1>;
 844                         mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
 845                         mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
 846                 };
 847
 848                 /* fdma audio */
 849                 fdma0: dma-controller@8e20000 {
 850                         compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
 851                         reg = <0x8e20000 0x8000>,
 852                               <0x8e30000 0x3000>,
 853                               <0x8e37000 0x1000>,
 854                               <0x8e38000 0x8000>;
 855                         reg-names = "slimcore", "dmem", "peripherals", "imem";
 856                         clocks = <&clk_s_c0_flexgen CLK_FDMA>,
 857                                  <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 858                                  <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 859                                  <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 860                         interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
 861                         dma-channels = <16>;
 862                         #dma-cells = <3>;
 863                 };
 864
 865                 /* fdma app */
 866                 fdma1: dma-controller@8e40000 {
 867                         compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
 868                         reg = <0x8e40000 0x8000>,
 869                               <0x8e50000 0x3000>,
 870                               <0x8e57000 0x1000>,
 871                               <0x8e58000 0x8000>;
 872                         reg-names = "slimcore", "dmem", "peripherals", "imem";
 873                         clocks = <&clk_s_c0_flexgen CLK_FDMA>,
 874                                 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
 875                                 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
 876                                 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 877
 878                         interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
 879                         dma-channels = <16>;
 880                         #dma-cells = <3>;
 881
 882                         status = "disabled";
 883                 };
 884
 885                 /* fdma free running */
 886                 fdma2: dma-controller@8e60000 {
 887                         compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
 888                         reg = <0x8e60000 0x8000>,
 889                               <0x8e70000 0x3000>,
 890                               <0x8e77000 0x1000>,
 891                               <0x8e78000 0x8000>;
 892                         reg-names = "slimcore", "dmem", "peripherals", "imem";
 893                         interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
 894                         dma-channels = <16>;
 895                         #dma-cells = <3>;
 896                         clocks = <&clk_s_c0_flexgen CLK_FDMA>,
 897                                 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 898                                 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
 899                                 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 900
 901                         status = "disabled";
 902                 };
 903
 904                 sti_uni_player0: sti-uni-player@8d80000 {
 905                         compatible = "st,stih407-uni-player-hdmi";
 906                         #sound-dai-cells = <0>;
 907                         st,syscfg = <&syscfg_core>;
 908                         clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
 909                         assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
 910                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
 911                         assigned-clock-rates = <50000000>;
 912                         reg = <0x8d80000 0x158>;
 913                         interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
 914                         dmas = <&fdma0 2 0 1>;
 915                         dma-names = "tx";
 916
 917                         status          = "disabled";
 918                 };
 919
 920                 sti_uni_player1: sti-uni-player@8d81000 {
 921                         compatible = "st,stih407-uni-player-pcm-out";
 922                         #sound-dai-cells = <0>;
 923                         st,syscfg = <&syscfg_core>;
 924                         clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
 925                         assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
 926                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
 927                         assigned-clock-rates = <50000000>;
 928                         reg = <0x8d81000 0x158>;
 929                         interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
 930                         dmas = <&fdma0 3 0 1>;
 931                         dma-names = "tx";
 932
 933                         status = "disabled";
 934                 };
 935
 936                 sti_uni_player2: sti-uni-player@8d82000 {
 937                         compatible = "st,stih407-uni-player-dac";
 938                         #sound-dai-cells = <0>;
 939                         st,syscfg = <&syscfg_core>;
 940                         clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
 941                         assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
 942                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
 943                         assigned-clock-rates = <50000000>;
 944                         reg = <0x8d82000 0x158>;
 945                         interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
 946                         dmas = <&fdma0 4 0 1>;
 947                         dma-names = "tx";
 948
 949                         status = "disabled";
 950                 };
 951
 952                 sti_uni_player3: sti-uni-player@8d85000 {
 953                         compatible = "st,stih407-uni-player-spdif";
 954                         #sound-dai-cells = <0>;
 955                         st,syscfg = <&syscfg_core>;
 956                         clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
 957                         assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
 958                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
 959                         assigned-clock-rates = <50000000>;
 960                         reg = <0x8d85000 0x158>;
 961                         interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
 962                         dmas = <&fdma0 7 0 1>;
 963                         dma-names = "tx";
 964
 965                         status = "disabled";
 966                 };
 967
 968                 sti_uni_reader0: sti-uni-reader@8d83000 {
 969                         compatible = "st,stih407-uni-reader-pcm_in";
 970                         #sound-dai-cells = <0>;
 971                         st,syscfg = <&syscfg_core>;
 972                         reg = <0x8d83000 0x158>;
 973                         interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
 974                         dmas = <&fdma0 5 0 1>;
 975                         dma-names = "rx";
 976
 977                         status = "disabled";
 978                 };
 979
 980                 sti_uni_reader1: sti-uni-reader@8d84000 {
 981                         compatible = "st,stih407-uni-reader-hdmi";
 982                         #sound-dai-cells = <0>;
 983                         st,syscfg = <&syscfg_core>;
 984                         reg = <0x8d84000 0x158>;
 985                         interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
 986                         dmas = <&fdma0 6 0 1>;
 987                         dma-names = "rx";
 988
 989                         status = "disabled";
 990                 };
 991
 992                 delta0@0 {
 993                         compatible = "st,st-delta";
 994                         reg = <0 0>;
 995                         clock-names = "delta",
 996                                       "delta-st231",
 997                                       "delta-flash-promip";
 998                         clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
 999                                  <&clk_s_c0_flexgen CLK_ST231_DMU>,
1000                                  <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
1001                 };
1002         };
1003 };