arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/mfd/dbx500-prcmu.h>
  15 #include <dt-bindings/arm/ux500_pm_domains.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include "skeleton.dtsi"
  18
  19 / {
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 enable-method = "ste,dbx500-smp";
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&CPU0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&CPU1>;
  32                                 };
  33                         };
  34                 };
  35                 CPU0: cpu@300 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <0x300>;
  39                 };
  40                 CPU1: cpu@301 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <0x301>;
  44                 };
  45         };
  46
  47         soc {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 compatible = "stericsson,db8500";
  51                 interrupt-parent = <&intc>;
  52                 ranges;
  53
  54                 ptm@801ae000 {
  55                         compatible = "arm,coresight-etm3x", "arm,primecell";
  56                         reg = <0x801ae000 0x1000>;
  57
  58                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  59                         clock-names = "apb_pclk", "atclk";
  60                         cpu = <&CPU0>;
  61                         port {
  62                                 ptm0_out_port: endpoint {
  63                                         remote-endpoint = <&funnel_in_port0>;
  64                                 };
  65                         };
  66                 };
  67
  68                 ptm@801af000 {
  69                         compatible = "arm,coresight-etm3x", "arm,primecell";
  70                         reg = <0x801af000 0x1000>;
  71
  72                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  73                         clock-names = "apb_pclk", "atclk";
  74                         cpu = <&CPU1>;
  75                         port {
  76                                 ptm1_out_port: endpoint {
  77                                         remote-endpoint = <&funnel_in_port1>;
  78                                 };
  79                         };
  80                 };
  81
  82                 funnel@801a6000 {
  83                         compatible = "arm,coresight-funnel", "arm,primecell";
  84                         reg = <0x801a6000 0x1000>;
  85
  86                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  87                         clock-names = "apb_pclk", "atclk";
  88                         ports {
  89                                 #address-cells = <1>;
  90                                 #size-cells = <0>;
  91
  92                                 /* funnel output ports */
  93                                 port@0 {
  94                                         reg = <0>;
  95                                         funnel_out_port: endpoint {
  96                                                 remote-endpoint =
  97                                                         <&replicator_in_port0>;
  98                                         };
  99                                 };
 100
 101                                 /* funnel input ports */
 102                                 port@1 {
 103                                         reg = <0>;
 104                                         funnel_in_port0: endpoint {
 105                                                 slave-mode;
 106                                                 remote-endpoint = <&ptm0_out_port>;
 107                                         };
 108                                 };
 109
 110                                 port@2 {
 111                                         reg = <1>;
 112                                         funnel_in_port1: endpoint {
 113                                                 slave-mode;
 114                                                 remote-endpoint = <&ptm1_out_port>;
 115                                         };
 116                                 };
 117                         };
 118                 };
 119
 120                 replicator {
 121                         compatible = "arm,coresight-replicator";
 122                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 123                         clock-names = "atclk";
 124
 125                         ports {
 126                                 #address-cells = <1>;
 127                                 #size-cells = <0>;
 128
 129                                 /* replicator output ports */
 130                                 port@0 {
 131                                         reg = <0>;
 132                                         replicator_out_port0: endpoint {
 133                                                 remote-endpoint = <&tpiu_in_port>;
 134                                         };
 135                                 };
 136                                 port@1 {
 137                                         reg = <1>;
 138                                         replicator_out_port1: endpoint {
 139                                                 remote-endpoint = <&etb_in_port>;
 140                                         };
 141                                 };
 142
 143                                 /* replicator input port */
 144                                 port@2 {
 145                                         reg = <0>;
 146                                         replicator_in_port0: endpoint {
 147                                                 slave-mode;
 148                                                 remote-endpoint = <&funnel_out_port>;
 149                                         };
 150                                 };
 151                         };
 152                 };
 153
 154                 tpiu@80190000 {
 155                         compatible = "arm,coresight-tpiu", "arm,primecell";
 156                         reg = <0x80190000 0x1000>;
 157
 158                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 159                         clock-names = "apb_pclk", "atclk";
 160                         port {
 161                                 tpiu_in_port: endpoint {
 162                                         slave-mode;
 163                                         remote-endpoint = <&replicator_out_port0>;
 164                                 };
 165                         };
 166                 };
 167
 168                 etb@801a4000 {
 169                         compatible = "arm,coresight-etb10", "arm,primecell";
 170                         reg = <0x801a4000 0x1000>;
 171
 172                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 173                         clock-names = "apb_pclk", "atclk";
 174                         port {
 175                                 etb_in_port: endpoint {
 176                                         slave-mode;
 177                                         remote-endpoint = <&replicator_out_port1>;
 178                                 };
 179                         };
 180                 };
 181
 182                 intc: interrupt-controller@a0411000 {
 183                         compatible = "arm,cortex-a9-gic";
 184                         #interrupt-cells = <3>;
 185                         #address-cells = <1>;
 186                         interrupt-controller;
 187                         reg = <0xa0411000 0x1000>,
 188                               <0xa0410100 0x100>;
 189                 };
 190
 191                 scu@a04100000 {
 192                         compatible = "arm,cortex-a9-scu";
 193                         reg = <0xa0410000 0x100>;
 194                 };
 195
 196                 /*
 197                  * The backup RAM is used for retention during sleep
 198                  * and various things like spin tables
 199                  */
 200                 backupram@80150000 {
 201                         compatible = "ste,dbx500-backupram";
 202                         reg = <0x80150000 0x2000>;
 203                 };
 204
 205                 L2: l2-cache {
 206                         compatible = "arm,pl310-cache";
 207                         reg = <0xa0412000 0x1000>;
 208                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 209                         cache-unified;
 210                         cache-level = <2>;
 211                 };
 212
 213                 pmu {
 214                         compatible = "arm,cortex-a9-pmu";
 215                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 216                 };
 217
 218                 pm_domains: pm_domains0 {
 219                         compatible = "stericsson,ux500-pm-domains";
 220                         #power-domain-cells = <1>;
 221                 };
 222
 223                 clocks {
 224                         compatible = "stericsson,u8500-clks";
 225                         /*
 226                          * Registers for the CLKRST block on peripheral
 227                          * groups 1, 2, 3, 5, 6,
 228                          */
 229                         reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 230                             <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 231                             <0xa03cf000 0x1000>;
 232
 233                         prcmu_clk: prcmu-clock {
 234                                 #clock-cells = <1>;
 235                         };
 236
 237                         prcc_pclk: prcc-periph-clock {
 238                                 #clock-cells = <2>;
 239                         };
 240
 241                         prcc_kclk: prcc-kernel-clock {
 242                                 #clock-cells = <2>;
 243                         };
 244
 245                         rtc_clk: rtc32k-clock {
 246                                 #clock-cells = <0>;
 247                         };
 248
 249                         smp_twd_clk: smp-twd-clock {
 250                                 #clock-cells = <0>;
 251                         };
 252                 };
 253
 254                 mtu@a03c6000 {
 255                         /* Nomadik System Timer */
 256                         compatible = "st,nomadik-mtu";
 257                         reg = <0xa03c6000 0x1000>;
 258                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 259
 260                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 261                         clock-names = "timclk", "apb_pclk";
 262                 };
 263
 264                 timer@a0410600 {
 265                         compatible = "arm,cortex-a9-twd-timer";
 266                         reg = <0xa0410600 0x20>;
 267                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 268
 269                         clocks = <&smp_twd_clk>;
 270                 };
 271
 272                 watchdog@a0410620 {
 273                         compatible = "arm,cortex-a9-twd-wdt";
 274                         reg = <0xa0410620 0x20>;
 275                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 276                         clocks = <&smp_twd_clk>;
 277                 };
 278
 279                 rtc@80154000 {
 280                         compatible = "arm,rtc-pl031", "arm,primecell";
 281                         reg = <0x80154000 0x1000>;
 282                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 283
 284                         clocks = <&rtc_clk>;
 285                         clock-names = "apb_pclk";
 286                 };
 287
 288                 gpio0: gpio@8012e000 {
 289                         compatible = "stericsson,db8500-gpio",
 290                                 "st,nomadik-gpio";
 291                         reg =  <0x8012e000 0x80>;
 292                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 293                         interrupt-controller;
 294                         #interrupt-cells = <2>;
 295                         st,supports-sleepmode;
 296                         gpio-controller;
 297                         #gpio-cells = <2>;
 298                         gpio-bank = <0>;
 299                         gpio-ranges = <&pinctrl 0 0 32>;
 300                         clocks = <&prcc_pclk 1 9>;
 301                 };
 302
 303                 gpio1: gpio@8012e080 {
 304                         compatible = "stericsson,db8500-gpio",
 305                                 "st,nomadik-gpio";
 306                         reg =  <0x8012e080 0x80>;
 307                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                         st,supports-sleepmode;
 311                         gpio-controller;
 312                         #gpio-cells = <2>;
 313                         gpio-bank = <1>;
 314                         gpio-ranges = <&pinctrl 0 32 5>;
 315                         clocks = <&prcc_pclk 1 9>;
 316                 };
 317
 318                 gpio2: gpio@8000e000 {
 319                         compatible = "stericsson,db8500-gpio",
 320                                 "st,nomadik-gpio";
 321                         reg =  <0x8000e000 0x80>;
 322                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                         st,supports-sleepmode;
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         gpio-bank = <2>;
 329                         gpio-ranges = <&pinctrl 0 64 32>;
 330                         clocks = <&prcc_pclk 3 8>;
 331                 };
 332
 333                 gpio3: gpio@8000e080 {
 334                         compatible = "stericsson,db8500-gpio",
 335                                 "st,nomadik-gpio";
 336                         reg =  <0x8000e080 0x80>;
 337                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                         st,supports-sleepmode;
 341                         gpio-controller;
 342                         #gpio-cells = <2>;
 343                         gpio-bank = <3>;
 344                         gpio-ranges = <&pinctrl 0 96 2>;
 345                         clocks = <&prcc_pclk 3 8>;
 346                 };
 347
 348                 gpio4: gpio@8000e100 {
 349                         compatible = "stericsson,db8500-gpio",
 350                                 "st,nomadik-gpio";
 351                         reg =  <0x8000e100 0x80>;
 352                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                         st,supports-sleepmode;
 356                         gpio-controller;
 357                         #gpio-cells = <2>;
 358                         gpio-bank = <4>;
 359                         gpio-ranges = <&pinctrl 0 128 32>;
 360                         clocks = <&prcc_pclk 3 8>;
 361                 };
 362
 363                 gpio5: gpio@8000e180 {
 364                         compatible = "stericsson,db8500-gpio",
 365                                 "st,nomadik-gpio";
 366                         reg =  <0x8000e180 0x80>;
 367                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 368                         interrupt-controller;
 369                         #interrupt-cells = <2>;
 370                         st,supports-sleepmode;
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                         gpio-bank = <5>;
 374                         gpio-ranges = <&pinctrl 0 160 12>;
 375                         clocks = <&prcc_pclk 3 8>;
 376                 };
 377
 378                 gpio6: gpio@8011e000 {
 379                         compatible = "stericsson,db8500-gpio",
 380                                 "st,nomadik-gpio";
 381                         reg =  <0x8011e000 0x80>;
 382                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 383                         interrupt-controller;
 384                         #interrupt-cells = <2>;
 385                         st,supports-sleepmode;
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         gpio-bank = <6>;
 389                         gpio-ranges = <&pinctrl 0 192 32>;
 390                         clocks = <&prcc_pclk 2 11>;
 391                 };
 392
 393                 gpio7: gpio@8011e080 {
 394                         compatible = "stericsson,db8500-gpio",
 395                                 "st,nomadik-gpio";
 396                         reg =  <0x8011e080 0x80>;
 397                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 398                         interrupt-controller;
 399                         #interrupt-cells = <2>;
 400                         st,supports-sleepmode;
 401                         gpio-controller;
 402                         #gpio-cells = <2>;
 403                         gpio-bank = <7>;
 404                         gpio-ranges = <&pinctrl 0 224 7>;
 405                         clocks = <&prcc_pclk 2 11>;
 406                 };
 407
 408                 gpio8: gpio@a03fe000 {
 409                         compatible = "stericsson,db8500-gpio",
 410                                 "st,nomadik-gpio";
 411                         reg =  <0xa03fe000 0x80>;
 412                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 413                         interrupt-controller;
 414                         #interrupt-cells = <2>;
 415                         st,supports-sleepmode;
 416                         gpio-controller;
 417                         #gpio-cells = <2>;
 418                         gpio-bank = <8>;
 419                         gpio-ranges = <&pinctrl 0 256 12>;
 420                         clocks = <&prcc_pclk 5 1>;
 421                 };
 422
 423                 pinctrl: pinctrl {
 424                         compatible = "stericsson,db8500-pinctrl";
 425                         nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
 426                                                 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
 427                                                 <&gpio8>;
 428                         prcm = <&prcmu>;
 429                 };
 430
 431                 usb_per5@a03e0000 {
 432                         compatible = "stericsson,db8500-musb";
 433                         reg = <0xa03e0000 0x10000>;
 434                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 435                         interrupt-names = "mc";
 436
 437                         dr_mode = "otg";
 438
 439                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 440                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 441                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 442                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 443                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 444                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 445                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 446                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 447                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 448                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 449                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 450                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 451                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 452                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 453                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 454                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 455
 456                         dma-names = "iep_1_9",  "oep_1_9",
 457                                     "iep_2_10", "oep_2_10",
 458                                     "iep_3_11", "oep_3_11",
 459                                     "iep_4_12", "oep_4_12",
 460                                     "iep_5_13", "oep_5_13",
 461                                     "iep_6_14", "oep_6_14",
 462                                     "iep_7_15", "oep_7_15",
 463                                     "iep_8",    "oep_8";
 464
 465                         clocks = <&prcc_pclk 5 0>;
 466                 };
 467
 468                 dma: dma-controller@801C0000 {
 469                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 470                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 471                         reg-names = "base", "lcpa";
 472                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 473
 474                         #dma-cells = <3>;
 475                         memcpy-channels = <56 57 58 59 60>;
 476
 477                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 478                 };
 479
 480                 prcmu: prcmu@80157000 {
 481                         compatible = "stericsson,db8500-prcmu";
 482                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 483                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 484                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 485                         #address-cells = <1>;
 486                         #size-cells = <1>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                         ranges;
 490
 491                         prcmu-timer-4@80157450 {
 492                                 compatible = "stericsson,db8500-prcmu-timer-4";
 493                                 reg = <0x80157450 0xC>;
 494                         };
 495
 496                         cpufreq {
 497                                 compatible = "stericsson,cpufreq-ux500";
 498                                 clocks = <&prcmu_clk PRCMU_ARMSS>;
 499                                 clock-names = "armss";
 500                                 status = "disabled";
 501                         };
 502
 503                         thermal@801573c0 {
 504                                 compatible = "stericsson,db8500-thermal";
 505                                 reg = <0x801573c0 0x40>;
 506                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 507                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 508                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 509                                 status = "disabled";
 510                         };
 511
 512                         db8500-prcmu-regulators {
 513                                 compatible = "stericsson,db8500-prcmu-regulator";
 514
 515                                 // DB8500_REGULATOR_VAPE
 516                                 db8500_vape_reg: db8500_vape {
 517                                         regulator-always-on;
 518                                 };
 519
 520                                 // DB8500_REGULATOR_VARM
 521                                 db8500_varm_reg: db8500_varm {
 522                                 };
 523
 524                                 // DB8500_REGULATOR_VMODEM
 525                                 db8500_vmodem_reg: db8500_vmodem {
 526                                 };
 527
 528                                 // DB8500_REGULATOR_VPLL
 529                                 db8500_vpll_reg: db8500_vpll {
 530                                 };
 531
 532                                 // DB8500_REGULATOR_VSMPS1
 533                                 db8500_vsmps1_reg: db8500_vsmps1 {
 534                                 };
 535
 536                                 // DB8500_REGULATOR_VSMPS2
 537                                 db8500_vsmps2_reg: db8500_vsmps2 {
 538                                 };
 539
 540                                 // DB8500_REGULATOR_VSMPS3
 541                                 db8500_vsmps3_reg: db8500_vsmps3 {
 542                                 };
 543
 544                                 // DB8500_REGULATOR_VRF1
 545                                 db8500_vrf1_reg: db8500_vrf1 {
 546                                 };
 547
 548                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 549                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 550                                 };
 551
 552                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 553                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 554                                 };
 555
 556                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 557                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 558                                 };
 559
 560                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 561                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 562                                 };
 563
 564                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 565                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 566                                 };
 567
 568                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 569                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 570                                 };
 571
 572                                 // DB8500_REGULATOR_SWITCH_SGA
 573                                 db8500_sga_reg: db8500_sga {
 574                                         vin-supply = <&db8500_vape_reg>;
 575                                 };
 576
 577                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 578                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 579                                         vin-supply = <&db8500_vape_reg>;
 580                                 };
 581
 582                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 583                                 db8500_esram12_reg: db8500_esram12 {
 584                                 };
 585
 586                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 587                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 588                                 };
 589
 590                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 591                                 db8500_esram34_reg: db8500_esram34 {
 592                                 };
 593
 594                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 595                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 596                                 };
 597                         };
 598
 599                         ab8500 {
 600                                 compatible = "stericsson,ab8500";
 601                                 interrupt-parent = <&intc>;
 602                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 603                                 interrupt-controller;
 604                                 #interrupt-cells = <2>;
 605
 606                                 ab8500_gpio: ab8500-gpio {
 607                                         compatible = "stericsson,ab8500-gpio";
 608                                         gpio-controller;
 609                                         #gpio-cells = <2>;
 610                                 };
 611
 612                                 ab8500-rtc {
 613                                         compatible = "stericsson,ab8500-rtc";
 614                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 615                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 616                                         interrupt-names = "60S", "ALARM";
 617                                 };
 618
 619                                 ab8500-gpadc {
 620                                         compatible = "stericsson,ab8500-gpadc";
 621                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 622                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 623                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 624                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 625                                 };
 626
 627                                 ab8500_battery: ab8500_battery {
 628                                         stericsson,battery-type = "LIPO";
 629                                         thermistor-on-batctrl;
 630                                 };
 631
 632                                 ab8500_fg {
 633                                         compatible = "stericsson,ab8500-fg";
 634                                         battery    = <&ab8500_battery>;
 635                                 };
 636
 637                                 ab8500_btemp {
 638                                         compatible = "stericsson,ab8500-btemp";
 639                                         battery    = <&ab8500_battery>;
 640                                 };
 641
 642                                 ab8500_charger {
 643                                         compatible      = "stericsson,ab8500-charger";
 644                                         battery         = <&ab8500_battery>;
 645                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 646                                 };
 647
 648                                 ab8500_chargalg {
 649                                         compatible      = "stericsson,ab8500-chargalg";
 650                                         battery         = <&ab8500_battery>;
 651                                 };
 652
 653                                 ab8500_usb {
 654                                         compatible = "stericsson,ab8500-usb";
 655                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 656                                                        96 IRQ_TYPE_LEVEL_HIGH
 657                                                        14 IRQ_TYPE_LEVEL_HIGH
 658                                                        15 IRQ_TYPE_LEVEL_HIGH
 659                                                        79 IRQ_TYPE_LEVEL_HIGH
 660                                                        74 IRQ_TYPE_LEVEL_HIGH
 661                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 662                                         interrupt-names = "ID_WAKEUP_R",
 663                                                           "ID_WAKEUP_F",
 664                                                           "VBUS_DET_F",
 665                                                           "VBUS_DET_R",
 666                                                           "USB_LINK_STATUS",
 667                                                           "USB_ADP_PROBE_PLUG",
 668                                                           "USB_ADP_PROBE_UNPLUG";
 669                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 670                                         v-ape-supply = <&db8500_vape_reg>;
 671                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 672                                 };
 673
 674                                 ab8500-ponkey {
 675                                         compatible = "stericsson,ab8500-poweron-key";
 676                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 677                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 678                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 679                                 };
 680
 681                                 ab8500-sysctrl {
 682                                         compatible = "stericsson,ab8500-sysctrl";
 683                                 };
 684
 685                                 ab8500-pwm {
 686                                         compatible = "stericsson,ab8500-pwm";
 687                                 };
 688
 689                                 ab8500-debugfs {
 690                                         compatible = "stericsson,ab8500-debug";
 691                                 };
 692
 693                                 codec: ab8500-codec {
 694                                         compatible = "stericsson,ab8500-codec";
 695
 696                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 697                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 698                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 699                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 700
 701                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 702                                 };
 703
 704                                 ext_regulators: ab8500-ext-regulators {
 705                                         compatible = "stericsson,ab8500-ext-regulator";
 706
 707                                         ab8500_ext1_reg: ab8500_ext1 {
 708                                                 regulator-min-microvolt = <1800000>;
 709                                                 regulator-max-microvolt = <1800000>;
 710                                                 regulator-boot-on;
 711                                                 regulator-always-on;
 712                                         };
 713
 714                                         ab8500_ext2_reg: ab8500_ext2 {
 715                                                 regulator-min-microvolt = <1360000>;
 716                                                 regulator-max-microvolt = <1360000>;
 717                                                 regulator-boot-on;
 718                                                 regulator-always-on;
 719                                         };
 720
 721                                         ab8500_ext3_reg: ab8500_ext3 {
 722                                                 regulator-min-microvolt = <3400000>;
 723                                                 regulator-max-microvolt = <3400000>;
 724                                                 regulator-boot-on;
 725                                         };
 726                                 };
 727
 728                                 ab8500-regulators {
 729                                         compatible = "stericsson,ab8500-regulator";
 730                                         vin-supply = <&ab8500_ext3_reg>;
 731
 732                                         // supplies to the display/camera
 733                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 734                                                 regulator-min-microvolt = <2500000>;
 735                                                 regulator-max-microvolt = <2900000>;
 736                                                 regulator-boot-on;
 737                                                 /* BUG: If turned off MMC will be affected. */
 738                                                 regulator-always-on;
 739                                         };
 740
 741                                         // supplies to the on-board eMMC
 742                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 743                                                 regulator-min-microvolt = <1100000>;
 744                                                 regulator-max-microvolt = <3300000>;
 745                                         };
 746
 747                                         // supply for VAUX3; SDcard slots
 748                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 749                                                 regulator-min-microvolt = <1100000>;
 750                                                 regulator-max-microvolt = <3300000>;
 751                                         };
 752
 753                                         // supply for v-intcore12; VINTCORE12 LDO
 754                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 755                                         };
 756
 757                                         // supply for tvout; gpadc; TVOUT LDO
 758                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 759                                         };
 760
 761                                         // supply for ab8500-usb; USB LDO
 762                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 763                                         };
 764
 765                                         // supply for ab8500-vaudio; VAUDIO LDO
 766                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 767                                         };
 768
 769                                         // supply for v-anamic1 VAMIC1 LDO
 770                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 771                                         };
 772
 773                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 774                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 775                                         };
 776
 777                                         // supply for v-dmic; VDMIC LDO
 778                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 779                                         };
 780
 781                                         // supply for U8500 CSI/DSI; VANA LDO
 782                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 783                                         };
 784                                 };
 785                         };
 786                 };
 787
 788                 i2c@80004000 {
 789                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 790                         reg = <0x80004000 0x1000>;
 791                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 792
 793                         #address-cells = <1>;
 794                         #size-cells = <0>;
 795                         v-i2c-supply = <&db8500_vape_reg>;
 796
 797                         clock-frequency = <400000>;
 798                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 799                         clock-names = "i2cclk", "apb_pclk";
 800                         power-domains = <&pm_domains DOMAIN_VAPE>;
 801                 };
 802
 803                 i2c@80122000 {
 804                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 805                         reg = <0x80122000 0x1000>;
 806                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 807
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810                         v-i2c-supply = <&db8500_vape_reg>;
 811
 812                         clock-frequency = <400000>;
 813
 814                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 815                         clock-names = "i2cclk", "apb_pclk";
 816                         power-domains = <&pm_domains DOMAIN_VAPE>;
 817                 };
 818
 819                 i2c@80128000 {
 820                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 821                         reg = <0x80128000 0x1000>;
 822                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 823
 824                         #address-cells = <1>;
 825                         #size-cells = <0>;
 826                         v-i2c-supply = <&db8500_vape_reg>;
 827
 828                         clock-frequency = <400000>;
 829
 830                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 831                         clock-names = "i2cclk", "apb_pclk";
 832                         power-domains = <&pm_domains DOMAIN_VAPE>;
 833                 };
 834
 835                 i2c@80110000 {
 836                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 837                         reg = <0x80110000 0x1000>;
 838                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 839
 840                         #address-cells = <1>;
 841                         #size-cells = <0>;
 842                         v-i2c-supply = <&db8500_vape_reg>;
 843
 844                         clock-frequency = <400000>;
 845
 846                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 847                         clock-names = "i2cclk", "apb_pclk";
 848                         power-domains = <&pm_domains DOMAIN_VAPE>;
 849                 };
 850
 851                 i2c@8012a000 {
 852                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 853                         reg = <0x8012a000 0x1000>;
 854                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 855
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         v-i2c-supply = <&db8500_vape_reg>;
 859
 860                         clock-frequency = <400000>;
 861
 862                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 863                         clock-names = "i2cclk", "apb_pclk";
 864                         power-domains = <&pm_domains DOMAIN_VAPE>;
 865                 };
 866
 867                 ssp@80002000 {
 868                         compatible = "arm,pl022", "arm,primecell";
 869                         reg = <0x80002000 0x1000>;
 870                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 874                         clock-names = "SSPCLK", "apb_pclk";
 875                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 876                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 877                         dma-names = "rx", "tx";
 878                         power-domains = <&pm_domains DOMAIN_VAPE>;
 879                 };
 880
 881                 ssp@80003000 {
 882                         compatible = "arm,pl022", "arm,primecell";
 883                         reg = <0x80003000 0x1000>;
 884                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 885                         #address-cells = <1>;
 886                         #size-cells = <0>;
 887                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 888                         clock-names = "SSPCLK", "apb_pclk";
 889                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 890                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 891                         dma-names = "rx", "tx";
 892                         power-domains = <&pm_domains DOMAIN_VAPE>;
 893                 };
 894
 895                 spi@8011a000 {
 896                         compatible = "arm,pl022", "arm,primecell";
 897                         reg = <0x8011a000 0x1000>;
 898                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 899                         #address-cells = <1>;
 900                         #size-cells = <0>;
 901                         /* Same clock wired to kernel and pclk */
 902                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 903                         clock-names = "SSPCLK", "apb_pclk";
 904                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 905                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 906                         dma-names = "rx", "tx";
 907                         power-domains = <&pm_domains DOMAIN_VAPE>;
 908                 };
 909
 910                 spi@80112000 {
 911                         compatible = "arm,pl022", "arm,primecell";
 912                         reg = <0x80112000 0x1000>;
 913                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 914                         #address-cells = <1>;
 915                         #size-cells = <0>;
 916                         /* Same clock wired to kernel and pclk */
 917                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 918                         clock-names = "SSPCLK", "apb_pclk";
 919                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 920                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 921                         dma-names = "rx", "tx";
 922                         power-domains = <&pm_domains DOMAIN_VAPE>;
 923                 };
 924
 925                 spi@80111000 {
 926                         compatible = "arm,pl022", "arm,primecell";
 927                         reg = <0x80111000 0x1000>;
 928                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931                         /* Same clock wired to kernel and pclk */
 932                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 933                         clock-names = "SSPCLK", "apb_pclk";
 934                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 935                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 936                         dma-names = "rx", "tx";
 937                         power-domains = <&pm_domains DOMAIN_VAPE>;
 938                 };
 939
 940                 spi@80129000 {
 941                         compatible = "arm,pl022", "arm,primecell";
 942                         reg = <0x80129000 0x1000>;
 943                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         /* Same clock wired to kernel and pclk */
 947                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 948                         clock-names = "SSPCLK", "apb_pclk";
 949                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 950                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 951                         dma-names = "rx", "tx";
 952                         power-domains = <&pm_domains DOMAIN_VAPE>;
 953                 };
 954
 955                 ux500_serial0: uart@80120000 {
 956                         compatible = "arm,pl011", "arm,primecell";
 957                         reg = <0x80120000 0x1000>;
 958                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 959
 960                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 961                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 962                         dma-names = "rx", "tx";
 963
 964                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 965                         clock-names = "uart", "apb_pclk";
 966
 967                         status = "disabled";
 968                 };
 969
 970                 ux500_serial1: uart@80121000 {
 971                         compatible = "arm,pl011", "arm,primecell";
 972                         reg = <0x80121000 0x1000>;
 973                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 974
 975                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 976                                <&dma 12 0 0x0>; /* Logical - MemToDev */
 977                         dma-names = "rx", "tx";
 978
 979                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
 980                         clock-names = "uart", "apb_pclk";
 981
 982                         status = "disabled";
 983                 };
 984
 985                 ux500_serial2: uart@80007000 {
 986                         compatible = "arm,pl011", "arm,primecell";
 987                         reg = <0x80007000 0x1000>;
 988                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 989
 990                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
 991                                <&dma 11 0 0x0>; /* Logical - MemToDev */
 992                         dma-names = "rx", "tx";
 993
 994                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
 995                         clock-names = "uart", "apb_pclk";
 996
 997                         status = "disabled";
 998                 };
 999
1000                 sdi0_per1@80126000 {
1001                         compatible = "arm,pl18x", "arm,primecell";
1002                         reg = <0x80126000 0x1000>;
1003                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1004
1005                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1006                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1007                         dma-names = "rx", "tx";
1008
1009                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1010                         clock-names = "sdi", "apb_pclk";
1011                         power-domains = <&pm_domains DOMAIN_VAPE>;
1012
1013                         status = "disabled";
1014                 };
1015
1016                 sdi1_per2@80118000 {
1017                         compatible = "arm,pl18x", "arm,primecell";
1018                         reg = <0x80118000 0x1000>;
1019                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1020
1021                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1022                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1023                         dma-names = "rx", "tx";
1024
1025                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1026                         clock-names = "sdi", "apb_pclk";
1027                         power-domains = <&pm_domains DOMAIN_VAPE>;
1028
1029                         status = "disabled";
1030                 };
1031
1032                 sdi2_per3@80005000 {
1033                         compatible = "arm,pl18x", "arm,primecell";
1034                         reg = <0x80005000 0x1000>;
1035                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1036
1037                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1038                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1039                         dma-names = "rx", "tx";
1040
1041                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1042                         clock-names = "sdi", "apb_pclk";
1043                         power-domains = <&pm_domains DOMAIN_VAPE>;
1044
1045                         status = "disabled";
1046                 };
1047
1048                 sdi3_per2@80119000 {
1049                         compatible = "arm,pl18x", "arm,primecell";
1050                         reg = <0x80119000 0x1000>;
1051                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1052
1053                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1054                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1055                         dma-names = "rx", "tx";
1056
1057                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1058                         clock-names = "sdi", "apb_pclk";
1059                         power-domains = <&pm_domains DOMAIN_VAPE>;
1060
1061                         status = "disabled";
1062                 };
1063
1064                 sdi4_per2@80114000 {
1065                         compatible = "arm,pl18x", "arm,primecell";
1066                         reg = <0x80114000 0x1000>;
1067                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1068
1069                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1070                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1071                         dma-names = "rx", "tx";
1072
1073                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1074                         clock-names = "sdi", "apb_pclk";
1075                         power-domains = <&pm_domains DOMAIN_VAPE>;
1076
1077                         status = "disabled";
1078                 };
1079
1080                 sdi5_per3@80008000 {
1081                         compatible = "arm,pl18x", "arm,primecell";
1082                         reg = <0x80008000 0x1000>;
1083                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1084
1085                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1086                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1087                         dma-names = "rx", "tx";
1088
1089                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1090                         clock-names = "sdi", "apb_pclk";
1091                         power-domains = <&pm_domains DOMAIN_VAPE>;
1092
1093                         status = "disabled";
1094                 };
1095
1096                 msp0: msp@80123000 {
1097                         compatible = "stericsson,ux500-msp-i2s";
1098                         reg = <0x80123000 0x1000>;
1099                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1100                         v-ape-supply = <&db8500_vape_reg>;
1101
1102                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1103                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1104                         dma-names = "rx", "tx";
1105
1106                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1107                         clock-names = "msp", "apb_pclk";
1108
1109                         status = "disabled";
1110                 };
1111
1112                 msp1: msp@80124000 {
1113                         compatible = "stericsson,ux500-msp-i2s";
1114                         reg = <0x80124000 0x1000>;
1115                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1116                         v-ape-supply = <&db8500_vape_reg>;
1117
1118                         /* This DMA channel only exist on DB8500 v1 */
1119                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1120                         dma-names = "tx";
1121
1122                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1123                         clock-names = "msp", "apb_pclk";
1124
1125                         status = "disabled";
1126                 };
1127
1128                 // HDMI sound
1129                 msp2: msp@80117000 {
1130                         compatible = "stericsson,ux500-msp-i2s";
1131                         reg = <0x80117000 0x1000>;
1132                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1133                         v-ape-supply = <&db8500_vape_reg>;
1134
1135                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1136                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1137                                                     HighPrio - Fixed */
1138                         dma-names = "rx", "tx";
1139
1140                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1141                         clock-names = "msp", "apb_pclk";
1142
1143                         status = "disabled";
1144                 };
1145
1146                 msp3: msp@80125000 {
1147                         compatible = "stericsson,ux500-msp-i2s";
1148                         reg = <0x80125000 0x1000>;
1149                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1150                         v-ape-supply = <&db8500_vape_reg>;
1151
1152                         /* This DMA channel only exist on DB8500 v2 */
1153                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1154                         dma-names = "rx";
1155
1156                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1157                         clock-names = "msp", "apb_pclk";
1158
1159                         status = "disabled";
1160                 };
1161
1162                 external-bus@50000000 {
1163                         compatible = "simple-bus";
1164                         reg = <0x50000000 0x4000000>;
1165                         #address-cells = <1>;
1166                         #size-cells = <1>;
1167                         ranges = <0 0x50000000 0x4000000>;
1168                         status = "disabled";
1169                 };
1170
1171                 cpufreq-cooling {
1172                         compatible = "stericsson,db8500-cpufreq-cooling";
1173                         status = "disabled";
1174                 };
1175
1176                 mcde@a0350000 {
1177                         compatible = "stericsson,mcde";
1178                         reg = <0xa0350000 0x1000>, /* MCDE */
1179                               <0xa0351000 0x1000>, /* DSI link 1 */
1180                               <0xa0352000 0x1000>, /* DSI link 2 */
1181                               <0xa0353000 0x1000>; /* DSI link 3 */
1182                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1183                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1184                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1185                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1186                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1187                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1188                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1189                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1190                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1191                 };
1192
1193                 cryp@a03cb000 {
1194                         compatible = "stericsson,ux500-cryp";
1195                         reg = <0xa03cb000 0x1000>;
1196                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1197
1198                         v-ape-supply = <&db8500_vape_reg>;
1199                         clocks = <&prcc_pclk 6 1>;
1200                 };
1201
1202                 hash@a03c2000 {
1203                         compatible = "stericsson,ux500-hash";
1204                         reg = <0xa03c2000 0x1000>;
1205
1206                         v-ape-supply = <&db8500_vape_reg>;
1207                         clocks = <&prcc_pclk 6 2>;
1208                 };
1209         };
1210 };