arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/mfd/dbx500-prcmu.h>
  15 #include <dt-bindings/arm/ux500_pm_domains.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/clock/ste-ab8500.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "ste,dbx500-smp";
  25
  26                 cpu-map {
  27                         cluster0 {
  28                                 core0 {
  29                                         cpu = <&CPU0>;
  30                                 };
  31                                 core1 {
  32                                         cpu = <&CPU1>;
  33                                 };
  34                         };
  35                 };
  36                 CPU0: cpu@300 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <0x300>;
  40                 };
  41                 CPU1: cpu@301 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <0x301>;
  45                 };
  46         };
  47
  48         soc {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 compatible = "stericsson,db8500";
  52                 interrupt-parent = <&intc>;
  53                 ranges;
  54
  55                 ptm@801ae000 {
  56                         compatible = "arm,coresight-etm3x", "arm,primecell";
  57                         reg = <0x801ae000 0x1000>;
  58
  59                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  60                         clock-names = "apb_pclk", "atclk";
  61                         cpu = <&CPU0>;
  62                         port {
  63                                 ptm0_out_port: endpoint {
  64                                         remote-endpoint = <&funnel_in_port0>;
  65                                 };
  66                         };
  67                 };
  68
  69                 ptm@801af000 {
  70                         compatible = "arm,coresight-etm3x", "arm,primecell";
  71                         reg = <0x801af000 0x1000>;
  72
  73                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  74                         clock-names = "apb_pclk", "atclk";
  75                         cpu = <&CPU1>;
  76                         port {
  77                                 ptm1_out_port: endpoint {
  78                                         remote-endpoint = <&funnel_in_port1>;
  79                                 };
  80                         };
  81                 };
  82
  83                 funnel@801a6000 {
  84                         compatible = "arm,coresight-funnel", "arm,primecell";
  85                         reg = <0x801a6000 0x1000>;
  86
  87                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  88                         clock-names = "apb_pclk", "atclk";
  89                         ports {
  90                                 #address-cells = <1>;
  91                                 #size-cells = <0>;
  92
  93                                 /* funnel output ports */
  94                                 port@0 {
  95                                         reg = <0>;
  96                                         funnel_out_port: endpoint {
  97                                                 remote-endpoint =
  98                                                         <&replicator_in_port0>;
  99                                         };
 100                                 };
 101
 102                                 /* funnel input ports */
 103                                 port@1 {
 104                                         reg = <0>;
 105                                         funnel_in_port0: endpoint {
 106                                                 slave-mode;
 107                                                 remote-endpoint = <&ptm0_out_port>;
 108                                         };
 109                                 };
 110
 111                                 port@2 {
 112                                         reg = <1>;
 113                                         funnel_in_port1: endpoint {
 114                                                 slave-mode;
 115                                                 remote-endpoint = <&ptm1_out_port>;
 116                                         };
 117                                 };
 118                         };
 119                 };
 120
 121                 replicator {
 122                         compatible = "arm,coresight-replicator";
 123                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 124                         clock-names = "atclk";
 125
 126                         ports {
 127                                 #address-cells = <1>;
 128                                 #size-cells = <0>;
 129
 130                                 /* replicator output ports */
 131                                 port@0 {
 132                                         reg = <0>;
 133                                         replicator_out_port0: endpoint {
 134                                                 remote-endpoint = <&tpiu_in_port>;
 135                                         };
 136                                 };
 137                                 port@1 {
 138                                         reg = <1>;
 139                                         replicator_out_port1: endpoint {
 140                                                 remote-endpoint = <&etb_in_port>;
 141                                         };
 142                                 };
 143
 144                                 /* replicator input port */
 145                                 port@2 {
 146                                         reg = <0>;
 147                                         replicator_in_port0: endpoint {
 148                                                 slave-mode;
 149                                                 remote-endpoint = <&funnel_out_port>;
 150                                         };
 151                                 };
 152                         };
 153                 };
 154
 155                 tpiu@80190000 {
 156                         compatible = "arm,coresight-tpiu", "arm,primecell";
 157                         reg = <0x80190000 0x1000>;
 158
 159                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 160                         clock-names = "apb_pclk", "atclk";
 161                         port {
 162                                 tpiu_in_port: endpoint {
 163                                         slave-mode;
 164                                         remote-endpoint = <&replicator_out_port0>;
 165                                 };
 166                         };
 167                 };
 168
 169                 etb@801a4000 {
 170                         compatible = "arm,coresight-etb10", "arm,primecell";
 171                         reg = <0x801a4000 0x1000>;
 172
 173                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 174                         clock-names = "apb_pclk", "atclk";
 175                         port {
 176                                 etb_in_port: endpoint {
 177                                         slave-mode;
 178                                         remote-endpoint = <&replicator_out_port1>;
 179                                 };
 180                         };
 181                 };
 182
 183                 intc: interrupt-controller@a0411000 {
 184                         compatible = "arm,cortex-a9-gic";
 185                         #interrupt-cells = <3>;
 186                         #address-cells = <1>;
 187                         interrupt-controller;
 188                         reg = <0xa0411000 0x1000>,
 189                               <0xa0410100 0x100>;
 190                 };
 191
 192                 scu@a04100000 {
 193                         compatible = "arm,cortex-a9-scu";
 194                         reg = <0xa0410000 0x100>;
 195                 };
 196
 197                 /*
 198                  * The backup RAM is used for retention during sleep
 199                  * and various things like spin tables
 200                  */
 201                 backupram@80150000 {
 202                         compatible = "ste,dbx500-backupram";
 203                         reg = <0x80150000 0x2000>;
 204                 };
 205
 206                 L2: l2-cache {
 207                         compatible = "arm,pl310-cache";
 208                         reg = <0xa0412000 0x1000>;
 209                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 210                         cache-unified;
 211                         cache-level = <2>;
 212                 };
 213
 214                 pmu {
 215                         compatible = "arm,cortex-a9-pmu";
 216                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 217                 };
 218
 219                 pm_domains: pm_domains0 {
 220                         compatible = "stericsson,ux500-pm-domains";
 221                         #power-domain-cells = <1>;
 222                 };
 223
 224                 clocks {
 225                         compatible = "stericsson,u8500-clks";
 226                         /*
 227                          * Registers for the CLKRST block on peripheral
 228                          * groups 1, 2, 3, 5, 6,
 229                          */
 230                         reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 231                             <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 232                             <0xa03cf000 0x1000>;
 233
 234                         prcmu_clk: prcmu-clock {
 235                                 #clock-cells = <1>;
 236                         };
 237
 238                         prcc_pclk: prcc-periph-clock {
 239                                 #clock-cells = <2>;
 240                         };
 241
 242                         prcc_kclk: prcc-kernel-clock {
 243                                 #clock-cells = <2>;
 244                         };
 245
 246                         rtc_clk: rtc32k-clock {
 247                                 #clock-cells = <0>;
 248                         };
 249
 250                         smp_twd_clk: smp-twd-clock {
 251                                 #clock-cells = <0>;
 252                         };
 253                 };
 254
 255                 mtu@a03c6000 {
 256                         /* Nomadik System Timer */
 257                         compatible = "st,nomadik-mtu";
 258                         reg = <0xa03c6000 0x1000>;
 259                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 260
 261                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 262                         clock-names = "timclk", "apb_pclk";
 263                 };
 264
 265                 timer@a0410600 {
 266                         compatible = "arm,cortex-a9-twd-timer";
 267                         reg = <0xa0410600 0x20>;
 268                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 269
 270                         clocks = <&smp_twd_clk>;
 271                 };
 272
 273                 watchdog@a0410620 {
 274                         compatible = "arm,cortex-a9-twd-wdt";
 275                         reg = <0xa0410620 0x20>;
 276                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 277                         clocks = <&smp_twd_clk>;
 278                 };
 279
 280                 rtc@80154000 {
 281                         compatible = "arm,rtc-pl031", "arm,primecell";
 282                         reg = <0x80154000 0x1000>;
 283                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 284
 285                         clocks = <&rtc_clk>;
 286                         clock-names = "apb_pclk";
 287                 };
 288
 289                 gpio0: gpio@8012e000 {
 290                         compatible = "stericsson,db8500-gpio",
 291                                 "st,nomadik-gpio";
 292                         reg =  <0x8012e000 0x80>;
 293                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 294                         interrupt-controller;
 295                         #interrupt-cells = <2>;
 296                         st,supports-sleepmode;
 297                         gpio-controller;
 298                         #gpio-cells = <2>;
 299                         gpio-bank = <0>;
 300                         gpio-ranges = <&pinctrl 0 0 32>;
 301                         clocks = <&prcc_pclk 1 9>;
 302                 };
 303
 304                 gpio1: gpio@8012e080 {
 305                         compatible = "stericsson,db8500-gpio",
 306                                 "st,nomadik-gpio";
 307                         reg =  <0x8012e080 0x80>;
 308                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 309                         interrupt-controller;
 310                         #interrupt-cells = <2>;
 311                         st,supports-sleepmode;
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                         gpio-bank = <1>;
 315                         gpio-ranges = <&pinctrl 0 32 5>;
 316                         clocks = <&prcc_pclk 1 9>;
 317                 };
 318
 319                 gpio2: gpio@8000e000 {
 320                         compatible = "stericsson,db8500-gpio",
 321                                 "st,nomadik-gpio";
 322                         reg =  <0x8000e000 0x80>;
 323                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                         st,supports-sleepmode;
 327                         gpio-controller;
 328                         #gpio-cells = <2>;
 329                         gpio-bank = <2>;
 330                         gpio-ranges = <&pinctrl 0 64 32>;
 331                         clocks = <&prcc_pclk 3 8>;
 332                 };
 333
 334                 gpio3: gpio@8000e080 {
 335                         compatible = "stericsson,db8500-gpio",
 336                                 "st,nomadik-gpio";
 337                         reg =  <0x8000e080 0x80>;
 338                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 339                         interrupt-controller;
 340                         #interrupt-cells = <2>;
 341                         st,supports-sleepmode;
 342                         gpio-controller;
 343                         #gpio-cells = <2>;
 344                         gpio-bank = <3>;
 345                         gpio-ranges = <&pinctrl 0 96 2>;
 346                         clocks = <&prcc_pclk 3 8>;
 347                 };
 348
 349                 gpio4: gpio@8000e100 {
 350                         compatible = "stericsson,db8500-gpio",
 351                                 "st,nomadik-gpio";
 352                         reg =  <0x8000e100 0x80>;
 353                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 354                         interrupt-controller;
 355                         #interrupt-cells = <2>;
 356                         st,supports-sleepmode;
 357                         gpio-controller;
 358                         #gpio-cells = <2>;
 359                         gpio-bank = <4>;
 360                         gpio-ranges = <&pinctrl 0 128 32>;
 361                         clocks = <&prcc_pclk 3 8>;
 362                 };
 363
 364                 gpio5: gpio@8000e180 {
 365                         compatible = "stericsson,db8500-gpio",
 366                                 "st,nomadik-gpio";
 367                         reg =  <0x8000e180 0x80>;
 368                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 369                         interrupt-controller;
 370                         #interrupt-cells = <2>;
 371                         st,supports-sleepmode;
 372                         gpio-controller;
 373                         #gpio-cells = <2>;
 374                         gpio-bank = <5>;
 375                         gpio-ranges = <&pinctrl 0 160 12>;
 376                         clocks = <&prcc_pclk 3 8>;
 377                 };
 378
 379                 gpio6: gpio@8011e000 {
 380                         compatible = "stericsson,db8500-gpio",
 381                                 "st,nomadik-gpio";
 382                         reg =  <0x8011e000 0x80>;
 383                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                         st,supports-sleepmode;
 387                         gpio-controller;
 388                         #gpio-cells = <2>;
 389                         gpio-bank = <6>;
 390                         gpio-ranges = <&pinctrl 0 192 32>;
 391                         clocks = <&prcc_pclk 2 11>;
 392                 };
 393
 394                 gpio7: gpio@8011e080 {
 395                         compatible = "stericsson,db8500-gpio",
 396                                 "st,nomadik-gpio";
 397                         reg =  <0x8011e080 0x80>;
 398                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 399                         interrupt-controller;
 400                         #interrupt-cells = <2>;
 401                         st,supports-sleepmode;
 402                         gpio-controller;
 403                         #gpio-cells = <2>;
 404                         gpio-bank = <7>;
 405                         gpio-ranges = <&pinctrl 0 224 7>;
 406                         clocks = <&prcc_pclk 2 11>;
 407                 };
 408
 409                 gpio8: gpio@a03fe000 {
 410                         compatible = "stericsson,db8500-gpio",
 411                                 "st,nomadik-gpio";
 412                         reg =  <0xa03fe000 0x80>;
 413                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 414                         interrupt-controller;
 415                         #interrupt-cells = <2>;
 416                         st,supports-sleepmode;
 417                         gpio-controller;
 418                         #gpio-cells = <2>;
 419                         gpio-bank = <8>;
 420                         gpio-ranges = <&pinctrl 0 256 12>;
 421                         clocks = <&prcc_pclk 5 1>;
 422                 };
 423
 424                 pinctrl: pinctrl {
 425                         compatible = "stericsson,db8500-pinctrl";
 426                         nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
 427                                                 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
 428                                                 <&gpio8>;
 429                         prcm = <&prcmu>;
 430                 };
 431
 432                 usb_per5@a03e0000 {
 433                         compatible = "stericsson,db8500-musb";
 434                         reg = <0xa03e0000 0x10000>;
 435                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 436                         interrupt-names = "mc";
 437
 438                         dr_mode = "otg";
 439
 440                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 441                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 442                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 443                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 444                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 445                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 446                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 447                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 448                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 449                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 450                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 451                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 452                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 453                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 454                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 455                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 456
 457                         dma-names = "iep_1_9",  "oep_1_9",
 458                                     "iep_2_10", "oep_2_10",
 459                                     "iep_3_11", "oep_3_11",
 460                                     "iep_4_12", "oep_4_12",
 461                                     "iep_5_13", "oep_5_13",
 462                                     "iep_6_14", "oep_6_14",
 463                                     "iep_7_15", "oep_7_15",
 464                                     "iep_8",    "oep_8";
 465
 466                         clocks = <&prcc_pclk 5 0>;
 467                 };
 468
 469                 dma: dma-controller@801C0000 {
 470                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 471                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 472                         reg-names = "base", "lcpa";
 473                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 474
 475                         #dma-cells = <3>;
 476                         memcpy-channels = <56 57 58 59 60>;
 477
 478                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 479                 };
 480
 481                 prcmu: prcmu@80157000 {
 482                         compatible = "stericsson,db8500-prcmu";
 483                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 484                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 485                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 486                         #address-cells = <1>;
 487                         #size-cells = <1>;
 488                         interrupt-controller;
 489                         #interrupt-cells = <2>;
 490                         ranges;
 491
 492                         prcmu-timer-4@80157450 {
 493                                 compatible = "stericsson,db8500-prcmu-timer-4";
 494                                 reg = <0x80157450 0xC>;
 495                         };
 496
 497                         cpufreq {
 498                                 compatible = "stericsson,cpufreq-ux500";
 499                                 clocks = <&prcmu_clk PRCMU_ARMSS>;
 500                                 clock-names = "armss";
 501                                 status = "disabled";
 502                         };
 503
 504                         thermal@801573c0 {
 505                                 compatible = "stericsson,db8500-thermal";
 506                                 reg = <0x801573c0 0x40>;
 507                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 508                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 509                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 510                                 status = "disabled";
 511                         };
 512
 513                         db8500-prcmu-regulators {
 514                                 compatible = "stericsson,db8500-prcmu-regulator";
 515
 516                                 // DB8500_REGULATOR_VAPE
 517                                 db8500_vape_reg: db8500_vape {
 518                                         regulator-always-on;
 519                                 };
 520
 521                                 // DB8500_REGULATOR_VARM
 522                                 db8500_varm_reg: db8500_varm {
 523                                 };
 524
 525                                 // DB8500_REGULATOR_VMODEM
 526                                 db8500_vmodem_reg: db8500_vmodem {
 527                                 };
 528
 529                                 // DB8500_REGULATOR_VPLL
 530                                 db8500_vpll_reg: db8500_vpll {
 531                                 };
 532
 533                                 // DB8500_REGULATOR_VSMPS1
 534                                 db8500_vsmps1_reg: db8500_vsmps1 {
 535                                 };
 536
 537                                 // DB8500_REGULATOR_VSMPS2
 538                                 db8500_vsmps2_reg: db8500_vsmps2 {
 539                                 };
 540
 541                                 // DB8500_REGULATOR_VSMPS3
 542                                 db8500_vsmps3_reg: db8500_vsmps3 {
 543                                 };
 544
 545                                 // DB8500_REGULATOR_VRF1
 546                                 db8500_vrf1_reg: db8500_vrf1 {
 547                                 };
 548
 549                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 550                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 551                                 };
 552
 553                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 554                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 555                                 };
 556
 557                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 558                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 559                                 };
 560
 561                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 562                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 563                                 };
 564
 565                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 566                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 567                                 };
 568
 569                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 570                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 571                                 };
 572
 573                                 // DB8500_REGULATOR_SWITCH_SGA
 574                                 db8500_sga_reg: db8500_sga {
 575                                         vin-supply = <&db8500_vape_reg>;
 576                                 };
 577
 578                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 579                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 580                                         vin-supply = <&db8500_vape_reg>;
 581                                 };
 582
 583                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 584                                 db8500_esram12_reg: db8500_esram12 {
 585                                 };
 586
 587                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 588                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 589                                 };
 590
 591                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 592                                 db8500_esram34_reg: db8500_esram34 {
 593                                 };
 594
 595                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 596                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 597                                 };
 598                         };
 599
 600                         ab8500 {
 601                                 compatible = "stericsson,ab8500";
 602                                 interrupt-parent = <&intc>;
 603                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 604                                 interrupt-controller;
 605                                 #interrupt-cells = <2>;
 606
 607                                 ab8500_clock: clock-controller {
 608                                         compatible = "stericsson,ab8500-clk";
 609                                         #clock-cells = <1>;
 610                                 };
 611
 612                                 ab8500_gpio: ab8500-gpio {
 613                                         compatible = "stericsson,ab8500-gpio";
 614                                         gpio-controller;
 615                                         #gpio-cells = <2>;
 616                                 };
 617
 618                                 ab8500-rtc {
 619                                         compatible = "stericsson,ab8500-rtc";
 620                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 621                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 622                                         interrupt-names = "60S", "ALARM";
 623                                 };
 624
 625                                 ab8500-gpadc {
 626                                         compatible = "stericsson,ab8500-gpadc";
 627                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 628                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 629                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 630                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 631                                 };
 632
 633                                 ab8500_battery: ab8500_battery {
 634                                         stericsson,battery-type = "LIPO";
 635                                         thermistor-on-batctrl;
 636                                 };
 637
 638                                 ab8500_fg {
 639                                         compatible = "stericsson,ab8500-fg";
 640                                         battery    = <&ab8500_battery>;
 641                                 };
 642
 643                                 ab8500_btemp {
 644                                         compatible = "stericsson,ab8500-btemp";
 645                                         battery    = <&ab8500_battery>;
 646                                 };
 647
 648                                 ab8500_charger {
 649                                         compatible      = "stericsson,ab8500-charger";
 650                                         battery         = <&ab8500_battery>;
 651                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 652                                 };
 653
 654                                 ab8500_chargalg {
 655                                         compatible      = "stericsson,ab8500-chargalg";
 656                                         battery         = <&ab8500_battery>;
 657                                 };
 658
 659                                 ab8500_usb {
 660                                         compatible = "stericsson,ab8500-usb";
 661                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 662                                                        96 IRQ_TYPE_LEVEL_HIGH
 663                                                        14 IRQ_TYPE_LEVEL_HIGH
 664                                                        15 IRQ_TYPE_LEVEL_HIGH
 665                                                        79 IRQ_TYPE_LEVEL_HIGH
 666                                                        74 IRQ_TYPE_LEVEL_HIGH
 667                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 668                                         interrupt-names = "ID_WAKEUP_R",
 669                                                           "ID_WAKEUP_F",
 670                                                           "VBUS_DET_F",
 671                                                           "VBUS_DET_R",
 672                                                           "USB_LINK_STATUS",
 673                                                           "USB_ADP_PROBE_PLUG",
 674                                                           "USB_ADP_PROBE_UNPLUG";
 675                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 676                                         v-ape-supply = <&db8500_vape_reg>;
 677                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 678                                         clocks = <&prcmu_clk PRCMU_SYSCLK>;
 679                                         clock-names = "sysclk";
 680                                 };
 681
 682                                 ab8500-ponkey {
 683                                         compatible = "stericsson,ab8500-poweron-key";
 684                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 685                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 686                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 687                                 };
 688
 689                                 ab8500-sysctrl {
 690                                         compatible = "stericsson,ab8500-sysctrl";
 691                                 };
 692
 693                                 ab8500-pwm {
 694                                         compatible = "stericsson,ab8500-pwm";
 695                                         clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
 696                                         clock-names = "intclk";
 697                                 };
 698
 699                                 ab8500-debugfs {
 700                                         compatible = "stericsson,ab8500-debug";
 701                                 };
 702
 703                                 codec: ab8500-codec {
 704                                         compatible = "stericsson,ab8500-codec";
 705
 706                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 707                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 708                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 709                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 710
 711                                         clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
 712                                         clock-names = "audioclk";
 713
 714                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 715                                 };
 716
 717                                 ext_regulators: ab8500-ext-regulators {
 718                                         compatible = "stericsson,ab8500-ext-regulator";
 719
 720                                         ab8500_ext1_reg: ab8500_ext1 {
 721                                                 regulator-min-microvolt = <1800000>;
 722                                                 regulator-max-microvolt = <1800000>;
 723                                                 regulator-boot-on;
 724                                                 regulator-always-on;
 725                                         };
 726
 727                                         ab8500_ext2_reg: ab8500_ext2 {
 728                                                 regulator-min-microvolt = <1360000>;
 729                                                 regulator-max-microvolt = <1360000>;
 730                                                 regulator-boot-on;
 731                                                 regulator-always-on;
 732                                         };
 733
 734                                         ab8500_ext3_reg: ab8500_ext3 {
 735                                                 regulator-min-microvolt = <3400000>;
 736                                                 regulator-max-microvolt = <3400000>;
 737                                                 regulator-boot-on;
 738                                         };
 739                                 };
 740
 741                                 ab8500-regulators {
 742                                         compatible = "stericsson,ab8500-regulator";
 743                                         vin-supply = <&ab8500_ext3_reg>;
 744
 745                                         // supplies to the display/camera
 746                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 747                                                 regulator-min-microvolt = <2500000>;
 748                                                 regulator-max-microvolt = <2900000>;
 749                                                 regulator-boot-on;
 750                                                 /* BUG: If turned off MMC will be affected. */
 751                                                 regulator-always-on;
 752                                         };
 753
 754                                         // supplies to the on-board eMMC
 755                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 756                                                 regulator-min-microvolt = <1100000>;
 757                                                 regulator-max-microvolt = <3300000>;
 758                                         };
 759
 760                                         // supply for VAUX3; SDcard slots
 761                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 762                                                 regulator-min-microvolt = <1100000>;
 763                                                 regulator-max-microvolt = <3300000>;
 764                                         };
 765
 766                                         // supply for v-intcore12; VINTCORE12 LDO
 767                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 768                                         };
 769
 770                                         // supply for tvout; gpadc; TVOUT LDO
 771                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 772                                         };
 773
 774                                         // supply for ab8500-usb; USB LDO
 775                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 776                                         };
 777
 778                                         // supply for ab8500-vaudio; VAUDIO LDO
 779                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 780                                         };
 781
 782                                         // supply for v-anamic1 VAMIC1 LDO
 783                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 784                                         };
 785
 786                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 787                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 788                                         };
 789
 790                                         // supply for v-dmic; VDMIC LDO
 791                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 792                                         };
 793
 794                                         // supply for U8500 CSI/DSI; VANA LDO
 795                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 796                                         };
 797                                 };
 798                         };
 799                 };
 800
 801                 i2c@80004000 {
 802                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 803                         reg = <0x80004000 0x1000>;
 804                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 805
 806                         #address-cells = <1>;
 807                         #size-cells = <0>;
 808                         v-i2c-supply = <&db8500_vape_reg>;
 809
 810                         clock-frequency = <400000>;
 811                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 812                         clock-names = "i2cclk", "apb_pclk";
 813                         power-domains = <&pm_domains DOMAIN_VAPE>;
 814                 };
 815
 816                 i2c@80122000 {
 817                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 818                         reg = <0x80122000 0x1000>;
 819                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 820
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                         v-i2c-supply = <&db8500_vape_reg>;
 824
 825                         clock-frequency = <400000>;
 826
 827                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 828                         clock-names = "i2cclk", "apb_pclk";
 829                         power-domains = <&pm_domains DOMAIN_VAPE>;
 830                 };
 831
 832                 i2c@80128000 {
 833                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 834                         reg = <0x80128000 0x1000>;
 835                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 836
 837                         #address-cells = <1>;
 838                         #size-cells = <0>;
 839                         v-i2c-supply = <&db8500_vape_reg>;
 840
 841                         clock-frequency = <400000>;
 842
 843                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 844                         clock-names = "i2cclk", "apb_pclk";
 845                         power-domains = <&pm_domains DOMAIN_VAPE>;
 846                 };
 847
 848                 i2c@80110000 {
 849                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 850                         reg = <0x80110000 0x1000>;
 851                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 852
 853                         #address-cells = <1>;
 854                         #size-cells = <0>;
 855                         v-i2c-supply = <&db8500_vape_reg>;
 856
 857                         clock-frequency = <400000>;
 858
 859                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 860                         clock-names = "i2cclk", "apb_pclk";
 861                         power-domains = <&pm_domains DOMAIN_VAPE>;
 862                 };
 863
 864                 i2c@8012a000 {
 865                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 866                         reg = <0x8012a000 0x1000>;
 867                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 868
 869                         #address-cells = <1>;
 870                         #size-cells = <0>;
 871                         v-i2c-supply = <&db8500_vape_reg>;
 872
 873                         clock-frequency = <400000>;
 874
 875                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 876                         clock-names = "i2cclk", "apb_pclk";
 877                         power-domains = <&pm_domains DOMAIN_VAPE>;
 878                 };
 879
 880                 ssp@80002000 {
 881                         compatible = "arm,pl022", "arm,primecell";
 882                         reg = <0x80002000 0x1000>;
 883                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 884                         #address-cells = <1>;
 885                         #size-cells = <0>;
 886                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 887                         clock-names = "SSPCLK", "apb_pclk";
 888                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 889                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 890                         dma-names = "rx", "tx";
 891                         power-domains = <&pm_domains DOMAIN_VAPE>;
 892                 };
 893
 894                 ssp@80003000 {
 895                         compatible = "arm,pl022", "arm,primecell";
 896                         reg = <0x80003000 0x1000>;
 897                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 898                         #address-cells = <1>;
 899                         #size-cells = <0>;
 900                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 901                         clock-names = "SSPCLK", "apb_pclk";
 902                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 903                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 904                         dma-names = "rx", "tx";
 905                         power-domains = <&pm_domains DOMAIN_VAPE>;
 906                 };
 907
 908                 spi@8011a000 {
 909                         compatible = "arm,pl022", "arm,primecell";
 910                         reg = <0x8011a000 0x1000>;
 911                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 912                         #address-cells = <1>;
 913                         #size-cells = <0>;
 914                         /* Same clock wired to kernel and pclk */
 915                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 916                         clock-names = "SSPCLK", "apb_pclk";
 917                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 918                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 919                         dma-names = "rx", "tx";
 920                         power-domains = <&pm_domains DOMAIN_VAPE>;
 921                 };
 922
 923                 spi@80112000 {
 924                         compatible = "arm,pl022", "arm,primecell";
 925                         reg = <0x80112000 0x1000>;
 926                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 927                         #address-cells = <1>;
 928                         #size-cells = <0>;
 929                         /* Same clock wired to kernel and pclk */
 930                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 931                         clock-names = "SSPCLK", "apb_pclk";
 932                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 933                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 934                         dma-names = "rx", "tx";
 935                         power-domains = <&pm_domains DOMAIN_VAPE>;
 936                 };
 937
 938                 spi@80111000 {
 939                         compatible = "arm,pl022", "arm,primecell";
 940                         reg = <0x80111000 0x1000>;
 941                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 942                         #address-cells = <1>;
 943                         #size-cells = <0>;
 944                         /* Same clock wired to kernel and pclk */
 945                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 946                         clock-names = "SSPCLK", "apb_pclk";
 947                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 948                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 949                         dma-names = "rx", "tx";
 950                         power-domains = <&pm_domains DOMAIN_VAPE>;
 951                 };
 952
 953                 spi@80129000 {
 954                         compatible = "arm,pl022", "arm,primecell";
 955                         reg = <0x80129000 0x1000>;
 956                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 957                         #address-cells = <1>;
 958                         #size-cells = <0>;
 959                         /* Same clock wired to kernel and pclk */
 960                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 961                         clock-names = "SSPCLK", "apb_pclk";
 962                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 963                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 964                         dma-names = "rx", "tx";
 965                         power-domains = <&pm_domains DOMAIN_VAPE>;
 966                 };
 967
 968                 ux500_serial0: uart@80120000 {
 969                         compatible = "arm,pl011", "arm,primecell";
 970                         reg = <0x80120000 0x1000>;
 971                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 972
 973                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 974                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 975                         dma-names = "rx", "tx";
 976
 977                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 978                         clock-names = "uart", "apb_pclk";
 979
 980                         status = "disabled";
 981                 };
 982
 983                 ux500_serial1: uart@80121000 {
 984                         compatible = "arm,pl011", "arm,primecell";
 985                         reg = <0x80121000 0x1000>;
 986                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 987
 988                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 989                                <&dma 12 0 0x0>; /* Logical - MemToDev */
 990                         dma-names = "rx", "tx";
 991
 992                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
 993                         clock-names = "uart", "apb_pclk";
 994
 995                         status = "disabled";
 996                 };
 997
 998                 ux500_serial2: uart@80007000 {
 999                         compatible = "arm,pl011", "arm,primecell";
1000                         reg = <0x80007000 0x1000>;
1001                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1002
1003                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1004                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1005                         dma-names = "rx", "tx";
1006
1007                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1008                         clock-names = "uart", "apb_pclk";
1009
1010                         status = "disabled";
1011                 };
1012
1013                 sdi0_per1@80126000 {
1014                         compatible = "arm,pl18x", "arm,primecell";
1015                         reg = <0x80126000 0x1000>;
1016                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1017
1018                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1019                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1020                         dma-names = "rx", "tx";
1021
1022                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1023                         clock-names = "sdi", "apb_pclk";
1024                         power-domains = <&pm_domains DOMAIN_VAPE>;
1025
1026                         status = "disabled";
1027                 };
1028
1029                 sdi1_per2@80118000 {
1030                         compatible = "arm,pl18x", "arm,primecell";
1031                         reg = <0x80118000 0x1000>;
1032                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1033
1034                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1035                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1036                         dma-names = "rx", "tx";
1037
1038                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1039                         clock-names = "sdi", "apb_pclk";
1040                         power-domains = <&pm_domains DOMAIN_VAPE>;
1041
1042                         status = "disabled";
1043                 };
1044
1045                 sdi2_per3@80005000 {
1046                         compatible = "arm,pl18x", "arm,primecell";
1047                         reg = <0x80005000 0x1000>;
1048                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1049
1050                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1051                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1052                         dma-names = "rx", "tx";
1053
1054                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1055                         clock-names = "sdi", "apb_pclk";
1056                         power-domains = <&pm_domains DOMAIN_VAPE>;
1057
1058                         status = "disabled";
1059                 };
1060
1061                 sdi3_per2@80119000 {
1062                         compatible = "arm,pl18x", "arm,primecell";
1063                         reg = <0x80119000 0x1000>;
1064                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1065
1066                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1067                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1068                         dma-names = "rx", "tx";
1069
1070                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1071                         clock-names = "sdi", "apb_pclk";
1072                         power-domains = <&pm_domains DOMAIN_VAPE>;
1073
1074                         status = "disabled";
1075                 };
1076
1077                 sdi4_per2@80114000 {
1078                         compatible = "arm,pl18x", "arm,primecell";
1079                         reg = <0x80114000 0x1000>;
1080                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1081
1082                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1083                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1084                         dma-names = "rx", "tx";
1085
1086                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1087                         clock-names = "sdi", "apb_pclk";
1088                         power-domains = <&pm_domains DOMAIN_VAPE>;
1089
1090                         status = "disabled";
1091                 };
1092
1093                 sdi5_per3@80008000 {
1094                         compatible = "arm,pl18x", "arm,primecell";
1095                         reg = <0x80008000 0x1000>;
1096                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1097
1098                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1099                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1100                         dma-names = "rx", "tx";
1101
1102                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1103                         clock-names = "sdi", "apb_pclk";
1104                         power-domains = <&pm_domains DOMAIN_VAPE>;
1105
1106                         status = "disabled";
1107                 };
1108
1109                 sound {
1110                         compatible = "stericsson,snd-soc-mop500";
1111                         stericsson,cpu-dai = <&msp1 &msp3>;
1112                         stericsson,audio-codec = <&codec>;
1113                         clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
1114                         clock-names = "sysclk", "ulpclk", "intclk";
1115                 };
1116
1117                 msp0: msp@80123000 {
1118                         compatible = "stericsson,ux500-msp-i2s";
1119                         reg = <0x80123000 0x1000>;
1120                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1121                         v-ape-supply = <&db8500_vape_reg>;
1122
1123                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1124                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1125                         dma-names = "rx", "tx";
1126
1127                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1128                         clock-names = "msp", "apb_pclk";
1129
1130                         status = "disabled";
1131                 };
1132
1133                 msp1: msp@80124000 {
1134                         compatible = "stericsson,ux500-msp-i2s";
1135                         reg = <0x80124000 0x1000>;
1136                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1137                         v-ape-supply = <&db8500_vape_reg>;
1138
1139                         /* This DMA channel only exist on DB8500 v1 */
1140                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1141                         dma-names = "tx";
1142
1143                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1144                         clock-names = "msp", "apb_pclk";
1145
1146                         status = "disabled";
1147                 };
1148
1149                 // HDMI sound
1150                 msp2: msp@80117000 {
1151                         compatible = "stericsson,ux500-msp-i2s";
1152                         reg = <0x80117000 0x1000>;
1153                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1154                         v-ape-supply = <&db8500_vape_reg>;
1155
1156                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1157                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1158                                                     HighPrio - Fixed */
1159                         dma-names = "rx", "tx";
1160
1161                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1162                         clock-names = "msp", "apb_pclk";
1163
1164                         status = "disabled";
1165                 };
1166
1167                 msp3: msp@80125000 {
1168                         compatible = "stericsson,ux500-msp-i2s";
1169                         reg = <0x80125000 0x1000>;
1170                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1171                         v-ape-supply = <&db8500_vape_reg>;
1172
1173                         /* This DMA channel only exist on DB8500 v2 */
1174                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1175                         dma-names = "rx";
1176
1177                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1178                         clock-names = "msp", "apb_pclk";
1179
1180                         status = "disabled";
1181                 };
1182
1183                 external-bus@50000000 {
1184                         compatible = "simple-bus";
1185                         reg = <0x50000000 0x4000000>;
1186                         #address-cells = <1>;
1187                         #size-cells = <1>;
1188                         ranges = <0 0x50000000 0x4000000>;
1189                         status = "disabled";
1190                 };
1191
1192                 mcde@a0350000 {
1193                         compatible = "stericsson,mcde";
1194                         reg = <0xa0350000 0x1000>, /* MCDE */
1195                               <0xa0351000 0x1000>, /* DSI link 1 */
1196                               <0xa0352000 0x1000>, /* DSI link 2 */
1197                               <0xa0353000 0x1000>; /* DSI link 3 */
1198                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1199                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1200                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1201                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1202                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1203                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1204                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1205                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1206                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1207                 };
1208
1209                 cryp@a03cb000 {
1210                         compatible = "stericsson,ux500-cryp";
1211                         reg = <0xa03cb000 0x1000>;
1212                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1213
1214                         v-ape-supply = <&db8500_vape_reg>;
1215                         clocks = <&prcc_pclk 6 1>;
1216                 };
1217
1218                 hash@a03c2000 {
1219                         compatible = "stericsson,ux500-hash";
1220                         reg = <0xa03c2000 0x1000>;
1221
1222                         v-ape-supply = <&db8500_vape_reg>;
1223                         clocks = <&prcc_pclk 6 2>;
1224                 };
1225         };
1226 };