arch/arm/boot/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <dt-bindings/reset/altr,rst-mgr.h>
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 serial0 = &uart0;
  26                 serial1 = &uart1;
  27                 timer0 = &timer0;
  28                 timer1 = &timer1;
  29                 timer2 = &timer2;
  30                 timer3 = &timer3;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36                 enable-method = "altr,socfpga-smp";
  37
  38                 cpu0: cpu@0 {
  39                         compatible = "arm,cortex-a9";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                         next-level-cache = <&L2>;
  43                 };
  44                 cpu1: cpu@1 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         reg = <1>;
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         pmu: pmu@ff111000 {
  53                 compatible = "arm,cortex-a9-pmu";
  54                 interrupt-parent = <&intc>;
  55                 interrupts = <0 176 4>, <0 177 4>;
  56                 interrupt-affinity = <&cpu0>, <&cpu1>;
  57                 reg = <0xff111000 0x1000>,
  58                       <0xff113000 0x1000>;
  59         };
  60
  61         intc: intc@fffed000 {
  62                 compatible = "arm,cortex-a9-gic";
  63                 #interrupt-cells = <3>;
  64                 interrupt-controller;
  65                 reg = <0xfffed000 0x1000>,
  66                       <0xfffec100 0x100>;
  67         };
  68
  69         soc {
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 compatible = "simple-bus";
  73                 device_type = "soc";
  74                 interrupt-parent = <&intc>;
  75                 ranges;
  76
  77                 amba {
  78                         compatible = "simple-bus";
  79                         #address-cells = <1>;
  80                         #size-cells = <1>;
  81                         ranges;
  82
  83                         pdma: pdma@ffe01000 {
  84                                 compatible = "arm,pl330", "arm,primecell";
  85                                 reg = <0xffe01000 0x1000>;
  86                                 interrupts = <0 104 4>,
  87                                              <0 105 4>,
  88                                              <0 106 4>,
  89                                              <0 107 4>,
  90                                              <0 108 4>,
  91                                              <0 109 4>,
  92                                              <0 110 4>,
  93                                              <0 111 4>;
  94                                 #dma-cells = <1>;
  95                                 #dma-channels = <8>;
  96                                 #dma-requests = <32>;
  97                                 clocks = <&l4_main_clk>;
  98                                 clock-names = "apb_pclk";
  99                         };
 100                 };
 101
 102                 base_fpga_region {
 103                         compatible = "fpga-region";
 104                         fpga-mgr = <&fpgamgr0>;
 105
 106                         #address-cells = <0x1>;
 107                         #size-cells = <0x1>;
 108                 };
 109
 110                 can0: can@ffc00000 {
 111                         compatible = "bosch,d_can";
 112                         reg = <0xffc00000 0x1000>;
 113                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
 114                         clocks = <&can0_clk>;
 115                         status = "disabled";
 116                 };
 117
 118                 can1: can@ffc01000 {
 119                         compatible = "bosch,d_can";
 120                         reg = <0xffc01000 0x1000>;
 121                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 122                         clocks = <&can1_clk>;
 123                         status = "disabled";
 124                 };
 125
 126                 clkmgr@ffd04000 {
 127                                 compatible = "altr,clk-mgr";
 128                                 reg = <0xffd04000 0x1000>;
 129
 130                                 clocks {
 131                                         #address-cells = <1>;
 132                                         #size-cells = <0>;
 133
 134                                         osc1: osc1 {
 135                                                 #clock-cells = <0>;
 136                                                 compatible = "fixed-clock";
 137                                         };
 138
 139                                         osc2: osc2 {
 140                                                 #clock-cells = <0>;
 141                                                 compatible = "fixed-clock";
 142                                         };
 143
 144                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 145                                                 #clock-cells = <0>;
 146                                                 compatible = "fixed-clock";
 147                                         };
 148
 149                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 150                                                 #clock-cells = <0>;
 151                                                 compatible = "fixed-clock";
 152                                         };
 153
 154                                         main_pll: main_pll@40 {
 155                                                 #address-cells = <1>;
 156                                                 #size-cells = <0>;
 157                                                 #clock-cells = <0>;
 158                                                 compatible = "altr,socfpga-pll-clock";
 159                                                 clocks = <&osc1>;
 160                                                 reg = <0x40>;
 161
 162                                                 mpuclk: mpuclk@48 {
 163                                                         #clock-cells = <0>;
 164                                                         compatible = "altr,socfpga-perip-clk";
 165                                                         clocks = <&main_pll>;
 166                                                         div-reg = <0xe0 0 9>;
 167                                                         reg = <0x48>;
 168                                                 };
 169
 170                                                 mainclk: mainclk@4c {
 171                                                         #clock-cells = <0>;
 172                                                         compatible = "altr,socfpga-perip-clk";
 173                                                         clocks = <&main_pll>;
 174                                                         div-reg = <0xe4 0 9>;
 175                                                         reg = <0x4C>;
 176                                                 };
 177
 178                                                 dbg_base_clk: dbg_base_clk@50 {
 179                                                         #clock-cells = <0>;
 180                                                         compatible = "altr,socfpga-perip-clk";
 181                                                         clocks = <&main_pll>, <&osc1>;
 182                                                         div-reg = <0xe8 0 9>;
 183                                                         reg = <0x50>;
 184                                                 };
 185
 186                                                 main_qspi_clk: main_qspi_clk@54 {
 187                                                         #clock-cells = <0>;
 188                                                         compatible = "altr,socfpga-perip-clk";
 189                                                         clocks = <&main_pll>;
 190                                                         reg = <0x54>;
 191                                                 };
 192
 193                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
 194                                                         #clock-cells = <0>;
 195                                                         compatible = "altr,socfpga-perip-clk";
 196                                                         clocks = <&main_pll>;
 197                                                         reg = <0x58>;
 198                                                 };
 199
 200                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
 201                                                         #clock-cells = <0>;
 202                                                         compatible = "altr,socfpga-perip-clk";
 203                                                         clocks = <&main_pll>;
 204                                                         reg = <0x5C>;
 205                                                 };
 206                                         };
 207
 208                                         periph_pll: periph_pll@80 {
 209                                                 #address-cells = <1>;
 210                                                 #size-cells = <0>;
 211                                                 #clock-cells = <0>;
 212                                                 compatible = "altr,socfpga-pll-clock";
 213                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 214                                                 reg = <0x80>;
 215
 216                                                 emac0_clk: emac0_clk@88 {
 217                                                         #clock-cells = <0>;
 218                                                         compatible = "altr,socfpga-perip-clk";
 219                                                         clocks = <&periph_pll>;
 220                                                         reg = <0x88>;
 221                                                 };
 222
 223                                                 emac1_clk: emac1_clk@8c {
 224                                                         #clock-cells = <0>;
 225                                                         compatible = "altr,socfpga-perip-clk";
 226                                                         clocks = <&periph_pll>;
 227                                                         reg = <0x8C>;
 228                                                 };
 229
 230                                                 per_qspi_clk: per_qsi_clk@90 {
 231                                                         #clock-cells = <0>;
 232                                                         compatible = "altr,socfpga-perip-clk";
 233                                                         clocks = <&periph_pll>;
 234                                                         reg = <0x90>;
 235                                                 };
 236
 237                                                 per_nand_mmc_clk: per_nand_mmc_clk@94 {
 238                                                         #clock-cells = <0>;
 239                                                         compatible = "altr,socfpga-perip-clk";
 240                                                         clocks = <&periph_pll>;
 241                                                         reg = <0x94>;
 242                                                 };
 243
 244                                                 per_base_clk: per_base_clk@98 {
 245                                                         #clock-cells = <0>;
 246                                                         compatible = "altr,socfpga-perip-clk";
 247                                                         clocks = <&periph_pll>;
 248                                                         reg = <0x98>;
 249                                                 };
 250
 251                                                 h2f_usr1_clk: h2f_usr1_clk@9c {
 252                                                         #clock-cells = <0>;
 253                                                         compatible = "altr,socfpga-perip-clk";
 254                                                         clocks = <&periph_pll>;
 255                                                         reg = <0x9C>;
 256                                                 };
 257                                         };
 258
 259                                         sdram_pll: sdram_pll@c0 {
 260                                                 #address-cells = <1>;
 261                                                 #size-cells = <0>;
 262                                                 #clock-cells = <0>;
 263                                                 compatible = "altr,socfpga-pll-clock";
 264                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 265                                                 reg = <0xC0>;
 266
 267                                                 ddr_dqs_clk: ddr_dqs_clk@c8 {
 268                                                         #clock-cells = <0>;
 269                                                         compatible = "altr,socfpga-perip-clk";
 270                                                         clocks = <&sdram_pll>;
 271                                                         reg = <0xC8>;
 272                                                 };
 273
 274                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
 275                                                         #clock-cells = <0>;
 276                                                         compatible = "altr,socfpga-perip-clk";
 277                                                         clocks = <&sdram_pll>;
 278                                                         reg = <0xCC>;
 279                                                 };
 280
 281                                                 ddr_dq_clk: ddr_dq_clk@d0 {
 282                                                         #clock-cells = <0>;
 283                                                         compatible = "altr,socfpga-perip-clk";
 284                                                         clocks = <&sdram_pll>;
 285                                                         reg = <0xD0>;
 286                                                 };
 287
 288                                                 h2f_usr2_clk: h2f_usr2_clk@d4 {
 289                                                         #clock-cells = <0>;
 290                                                         compatible = "altr,socfpga-perip-clk";
 291                                                         clocks = <&sdram_pll>;
 292                                                         reg = <0xD4>;
 293                                                 };
 294                                         };
 295
 296                                         mpu_periph_clk: mpu_periph_clk {
 297                                                 #clock-cells = <0>;
 298                                                 compatible = "altr,socfpga-perip-clk";
 299                                                 clocks = <&mpuclk>;
 300                                                 fixed-divider = <4>;
 301                                         };
 302
 303                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 304                                                 #clock-cells = <0>;
 305                                                 compatible = "altr,socfpga-perip-clk";
 306                                                 clocks = <&mpuclk>;
 307                                                 fixed-divider = <2>;
 308                                         };
 309
 310                                         l4_main_clk: l4_main_clk {
 311                                                 #clock-cells = <0>;
 312                                                 compatible = "altr,socfpga-gate-clk";
 313                                                 clocks = <&mainclk>;
 314                                                 clk-gate = <0x60 0>;
 315                                         };
 316
 317                                         l3_main_clk: l3_main_clk {
 318                                                 #clock-cells = <0>;
 319                                                 compatible = "altr,socfpga-perip-clk";
 320                                                 clocks = <&mainclk>;
 321                                                 fixed-divider = <1>;
 322                                         };
 323
 324                                         l3_mp_clk: l3_mp_clk {
 325                                                 #clock-cells = <0>;
 326                                                 compatible = "altr,socfpga-gate-clk";
 327                                                 clocks = <&mainclk>;
 328                                                 div-reg = <0x64 0 2>;
 329                                                 clk-gate = <0x60 1>;
 330                                         };
 331
 332                                         l3_sp_clk: l3_sp_clk {
 333                                                 #clock-cells = <0>;
 334                                                 compatible = "altr,socfpga-gate-clk";
 335                                                 clocks = <&l3_mp_clk>;
 336                                                 div-reg = <0x64 2 2>;
 337                                         };
 338
 339                                         l4_mp_clk: l4_mp_clk {
 340                                                 #clock-cells = <0>;
 341                                                 compatible = "altr,socfpga-gate-clk";
 342                                                 clocks = <&mainclk>, <&per_base_clk>;
 343                                                 div-reg = <0x64 4 3>;
 344                                                 clk-gate = <0x60 2>;
 345                                         };
 346
 347                                         l4_sp_clk: l4_sp_clk {
 348                                                 #clock-cells = <0>;
 349                                                 compatible = "altr,socfpga-gate-clk";
 350                                                 clocks = <&mainclk>, <&per_base_clk>;
 351                                                 div-reg = <0x64 7 3>;
 352                                                 clk-gate = <0x60 3>;
 353                                         };
 354
 355                                         dbg_at_clk: dbg_at_clk {
 356                                                 #clock-cells = <0>;
 357                                                 compatible = "altr,socfpga-gate-clk";
 358                                                 clocks = <&dbg_base_clk>;
 359                                                 div-reg = <0x68 0 2>;
 360                                                 clk-gate = <0x60 4>;
 361                                         };
 362
 363                                         dbg_clk: dbg_clk {
 364                                                 #clock-cells = <0>;
 365                                                 compatible = "altr,socfpga-gate-clk";
 366                                                 clocks = <&dbg_at_clk>;
 367                                                 div-reg = <0x68 2 2>;
 368                                                 clk-gate = <0x60 5>;
 369                                         };
 370
 371                                         dbg_trace_clk: dbg_trace_clk {
 372                                                 #clock-cells = <0>;
 373                                                 compatible = "altr,socfpga-gate-clk";
 374                                                 clocks = <&dbg_base_clk>;
 375                                                 div-reg = <0x6C 0 3>;
 376                                                 clk-gate = <0x60 6>;
 377                                         };
 378
 379                                         dbg_timer_clk: dbg_timer_clk {
 380                                                 #clock-cells = <0>;
 381                                                 compatible = "altr,socfpga-gate-clk";
 382                                                 clocks = <&dbg_base_clk>;
 383                                                 clk-gate = <0x60 7>;
 384                                         };
 385
 386                                         cfg_clk: cfg_clk {
 387                                                 #clock-cells = <0>;
 388                                                 compatible = "altr,socfpga-gate-clk";
 389                                                 clocks = <&cfg_h2f_usr0_clk>;
 390                                                 clk-gate = <0x60 8>;
 391                                         };
 392
 393                                         h2f_user0_clk: h2f_user0_clk {
 394                                                 #clock-cells = <0>;
 395                                                 compatible = "altr,socfpga-gate-clk";
 396                                                 clocks = <&cfg_h2f_usr0_clk>;
 397                                                 clk-gate = <0x60 9>;
 398                                         };
 399
 400                                         emac_0_clk: emac_0_clk {
 401                                                 #clock-cells = <0>;
 402                                                 compatible = "altr,socfpga-gate-clk";
 403                                                 clocks = <&emac0_clk>;
 404                                                 clk-gate = <0xa0 0>;
 405                                         };
 406
 407                                         emac_1_clk: emac_1_clk {
 408                                                 #clock-cells = <0>;
 409                                                 compatible = "altr,socfpga-gate-clk";
 410                                                 clocks = <&emac1_clk>;
 411                                                 clk-gate = <0xa0 1>;
 412                                         };
 413
 414                                         usb_mp_clk: usb_mp_clk {
 415                                                 #clock-cells = <0>;
 416                                                 compatible = "altr,socfpga-gate-clk";
 417                                                 clocks = <&per_base_clk>;
 418                                                 clk-gate = <0xa0 2>;
 419                                                 div-reg = <0xa4 0 3>;
 420                                         };
 421
 422                                         spi_m_clk: spi_m_clk {
 423                                                 #clock-cells = <0>;
 424                                                 compatible = "altr,socfpga-gate-clk";
 425                                                 clocks = <&per_base_clk>;
 426                                                 clk-gate = <0xa0 3>;
 427                                                 div-reg = <0xa4 3 3>;
 428                                         };
 429
 430                                         can0_clk: can0_clk {
 431                                                 #clock-cells = <0>;
 432                                                 compatible = "altr,socfpga-gate-clk";
 433                                                 clocks = <&per_base_clk>;
 434                                                 clk-gate = <0xa0 4>;
 435                                                 div-reg = <0xa4 6 3>;
 436                                         };
 437
 438                                         can1_clk: can1_clk {
 439                                                 #clock-cells = <0>;
 440                                                 compatible = "altr,socfpga-gate-clk";
 441                                                 clocks = <&per_base_clk>;
 442                                                 clk-gate = <0xa0 5>;
 443                                                 div-reg = <0xa4 9 3>;
 444                                         };
 445
 446                                         gpio_db_clk: gpio_db_clk {
 447                                                 #clock-cells = <0>;
 448                                                 compatible = "altr,socfpga-gate-clk";
 449                                                 clocks = <&per_base_clk>;
 450                                                 clk-gate = <0xa0 6>;
 451                                                 div-reg = <0xa8 0 24>;
 452                                         };
 453
 454                                         h2f_user1_clk: h2f_user1_clk {
 455                                                 #clock-cells = <0>;
 456                                                 compatible = "altr,socfpga-gate-clk";
 457                                                 clocks = <&h2f_usr1_clk>;
 458                                                 clk-gate = <0xa0 7>;
 459                                         };
 460
 461                                         sdmmc_clk: sdmmc_clk {
 462                                                 #clock-cells = <0>;
 463                                                 compatible = "altr,socfpga-gate-clk";
 464                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 465                                                 clk-gate = <0xa0 8>;
 466                                                 clk-phase = <0 135>;
 467                                         };
 468
 469                                         sdmmc_clk_divided: sdmmc_clk_divided {
 470                                                 #clock-cells = <0>;
 471                                                 compatible = "altr,socfpga-gate-clk";
 472                                                 clocks = <&sdmmc_clk>;
 473                                                 clk-gate = <0xa0 8>;
 474                                                 fixed-divider = <4>;
 475                                         };
 476
 477                                         nand_x_clk: nand_x_clk {
 478                                                 #clock-cells = <0>;
 479                                                 compatible = "altr,socfpga-gate-clk";
 480                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 481                                                 clk-gate = <0xa0 9>;
 482                                         };
 483
 484                                         nand_ecc_clk: nand_ecc_clk {
 485                                                 #clock-cells = <0>;
 486                                                 compatible = "altr,socfpga-gate-clk";
 487                                                 clocks = <&nand_x_clk>;
 488                                                 clk-gate = <0xa0 9>;
 489                                         };
 490
 491                                         nand_clk: nand_clk {
 492                                                 #clock-cells = <0>;
 493                                                 compatible = "altr,socfpga-gate-clk";
 494                                                 clocks = <&nand_x_clk>;
 495                                                 clk-gate = <0xa0 10>;
 496                                                 fixed-divider = <4>;
 497                                         };
 498
 499                                         qspi_clk: qspi_clk {
 500                                                 #clock-cells = <0>;
 501                                                 compatible = "altr,socfpga-gate-clk";
 502                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 503                                                 clk-gate = <0xa0 11>;
 504                                         };
 505
 506                                         ddr_dqs_clk_gate: ddr_dqs_clk_gate {
 507                                                 #clock-cells = <0>;
 508                                                 compatible = "altr,socfpga-gate-clk";
 509                                                 clocks = <&ddr_dqs_clk>;
 510                                                 clk-gate = <0xd8 0>;
 511                                         };
 512
 513                                         ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
 514                                                 #clock-cells = <0>;
 515                                                 compatible = "altr,socfpga-gate-clk";
 516                                                 clocks = <&ddr_2x_dqs_clk>;
 517                                                 clk-gate = <0xd8 1>;
 518                                         };
 519
 520                                         ddr_dq_clk_gate: ddr_dq_clk_gate {
 521                                                 #clock-cells = <0>;
 522                                                 compatible = "altr,socfpga-gate-clk";
 523                                                 clocks = <&ddr_dq_clk>;
 524                                                 clk-gate = <0xd8 2>;
 525                                         };
 526
 527                                         h2f_user2_clk: h2f_user2_clk {
 528                                                 #clock-cells = <0>;
 529                                                 compatible = "altr,socfpga-gate-clk";
 530                                                 clocks = <&h2f_usr2_clk>;
 531                                                 clk-gate = <0xd8 3>;
 532                                         };
 533
 534                                 };
 535                 };
 536
 537                 fpga_bridge0: fpga_bridge@ff400000 {
 538                         compatible = "altr,socfpga-lwhps2fpga-bridge";
 539                         reg = <0xff400000 0x100000>;
 540                         resets = <&rst LWHPS2FPGA_RESET>;
 541                         clocks = <&l4_main_clk>;
 542                 };
 543
 544                 fpga_bridge1: fpga_bridge@ff500000 {
 545                         compatible = "altr,socfpga-hps2fpga-bridge";
 546                         reg = <0xff500000 0x10000>;
 547                         resets = <&rst HPS2FPGA_RESET>;
 548                         clocks = <&l4_main_clk>;
 549                 };
 550
 551                 fpgamgr0: fpgamgr@ff706000 {
 552                         compatible = "altr,socfpga-fpga-mgr";
 553                         reg = <0xff706000 0x1000
 554                                0xffb90000 0x4>;
 555                         interrupts = <0 175 4>;
 556                 };
 557
 558                 gmac0: ethernet@ff700000 {
 559                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 560                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 561                         reg = <0xff700000 0x2000>;
 562                         interrupts = <0 115 4>;
 563                         interrupt-names = "macirq";
 564                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 565                         clocks = <&emac_0_clk>;
 566                         clock-names = "stmmaceth";
 567                         resets = <&rst EMAC0_RESET>;
 568                         reset-names = "stmmaceth";
 569                         snps,multicast-filter-bins = <256>;
 570                         snps,perfect-filter-entries = <128>;
 571                         tx-fifo-depth = <4096>;
 572                         rx-fifo-depth = <4096>;
 573                         status = "disabled";
 574                 };
 575
 576                 gmac1: ethernet@ff702000 {
 577                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 578                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 579                         reg = <0xff702000 0x2000>;
 580                         interrupts = <0 120 4>;
 581                         interrupt-names = "macirq";
 582                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 583                         clocks = <&emac_1_clk>;
 584                         clock-names = "stmmaceth";
 585                         resets = <&rst EMAC1_RESET>;
 586                         reset-names = "stmmaceth";
 587                         snps,multicast-filter-bins = <256>;
 588                         snps,perfect-filter-entries = <128>;
 589                         tx-fifo-depth = <4096>;
 590                         rx-fifo-depth = <4096>;
 591                         status = "disabled";
 592                 };
 593
 594                 gpio0: gpio@ff708000 {
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597                         compatible = "snps,dw-apb-gpio";
 598                         reg = <0xff708000 0x1000>;
 599                         clocks = <&l4_mp_clk>;
 600                         status = "disabled";
 601
 602                         porta: gpio-controller@0 {
 603                                 compatible = "snps,dw-apb-gpio-port";
 604                                 gpio-controller;
 605                                 #gpio-cells = <2>;
 606                                 snps,nr-gpios = <29>;
 607                                 reg = <0>;
 608                                 interrupt-controller;
 609                                 #interrupt-cells = <2>;
 610                                 interrupts = <0 164 4>;
 611                         };
 612                 };
 613
 614                 gpio1: gpio@ff709000 {
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                         compatible = "snps,dw-apb-gpio";
 618                         reg = <0xff709000 0x1000>;
 619                         clocks = <&l4_mp_clk>;
 620                         status = "disabled";
 621
 622                         portb: gpio-controller@0 {
 623                                 compatible = "snps,dw-apb-gpio-port";
 624                                 gpio-controller;
 625                                 #gpio-cells = <2>;
 626                                 snps,nr-gpios = <29>;
 627                                 reg = <0>;
 628                                 interrupt-controller;
 629                                 #interrupt-cells = <2>;
 630                                 interrupts = <0 165 4>;
 631                         };
 632                 };
 633
 634                 gpio2: gpio@ff70a000 {
 635                         #address-cells = <1>;
 636                         #size-cells = <0>;
 637                         compatible = "snps,dw-apb-gpio";
 638                         reg = <0xff70a000 0x1000>;
 639                         clocks = <&l4_mp_clk>;
 640                         status = "disabled";
 641
 642                         portc: gpio-controller@0 {
 643                                 compatible = "snps,dw-apb-gpio-port";
 644                                 gpio-controller;
 645                                 #gpio-cells = <2>;
 646                                 snps,nr-gpios = <27>;
 647                                 reg = <0>;
 648                                 interrupt-controller;
 649                                 #interrupt-cells = <2>;
 650                                 interrupts = <0 166 4>;
 651                         };
 652                 };
 653
 654                 i2c0: i2c@ffc04000 {
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         compatible = "snps,designware-i2c";
 658                         reg = <0xffc04000 0x1000>;
 659                         resets = <&rst I2C0_RESET>;
 660                         clocks = <&l4_sp_clk>;
 661                         interrupts = <0 158 0x4>;
 662                         status = "disabled";
 663                 };
 664
 665                 i2c1: i2c@ffc05000 {
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         compatible = "snps,designware-i2c";
 669                         reg = <0xffc05000 0x1000>;
 670                         resets = <&rst I2C1_RESET>;
 671                         clocks = <&l4_sp_clk>;
 672                         interrupts = <0 159 0x4>;
 673                         status = "disabled";
 674                 };
 675
 676                 i2c2: i2c@ffc06000 {
 677                         #address-cells = <1>;
 678                         #size-cells = <0>;
 679                         compatible = "snps,designware-i2c";
 680                         reg = <0xffc06000 0x1000>;
 681                         resets = <&rst I2C2_RESET>;
 682                         clocks = <&l4_sp_clk>;
 683                         interrupts = <0 160 0x4>;
 684                         status = "disabled";
 685                 };
 686
 687                 i2c3: i2c@ffc07000 {
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                         compatible = "snps,designware-i2c";
 691                         reg = <0xffc07000 0x1000>;
 692                         resets = <&rst I2C3_RESET>;
 693                         clocks = <&l4_sp_clk>;
 694                         interrupts = <0 161 0x4>;
 695                         status = "disabled";
 696                 };
 697
 698                 eccmgr: eccmgr {
 699                         compatible = "altr,socfpga-ecc-manager";
 700                         #address-cells = <1>;
 701                         #size-cells = <1>;
 702                         ranges;
 703
 704                         l2-ecc@ffd08140 {
 705                                 compatible = "altr,socfpga-l2-ecc";
 706                                 reg = <0xffd08140 0x4>;
 707                                 interrupts = <0 36 1>, <0 37 1>;
 708                         };
 709
 710                         ocram-ecc@ffd08144 {
 711                                 compatible = "altr,socfpga-ocram-ecc";
 712                                 reg = <0xffd08144 0x4>;
 713                                 iram = <&ocram>;
 714                                 interrupts = <0 178 1>, <0 179 1>;
 715                         };
 716                 };
 717
 718                 L2: l2-cache@fffef000 {
 719                         compatible = "arm,pl310-cache";
 720                         reg = <0xfffef000 0x1000>;
 721                         interrupts = <0 38 0x04>;
 722                         cache-unified;
 723                         cache-level = <2>;
 724                         arm,tag-latency = <1 1 1>;
 725                         arm,data-latency = <2 1 1>;
 726                         prefetch-data = <1>;
 727                         prefetch-instr = <1>;
 728                         arm,shared-override;
 729                         arm,double-linefill = <1>;
 730                         arm,double-linefill-incr = <0>;
 731                         arm,double-linefill-wrap = <1>;
 732                         arm,prefetch-drop = <0>;
 733                         arm,prefetch-offset = <7>;
 734                 };
 735
 736                 l3regs@0xff800000 {
 737                         compatible = "altr,l3regs", "syscon";
 738                         reg = <0xff800000 0x1000>;
 739                 };
 740
 741                 mmc: dwmmc0@ff704000 {
 742                         compatible = "altr,socfpga-dw-mshc";
 743                         reg = <0xff704000 0x1000>;
 744                         interrupts = <0 139 4>;
 745                         fifo-depth = <0x400>;
 746                         #address-cells = <1>;
 747                         #size-cells = <0>;
 748                         clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
 749                         clock-names = "biu", "ciu";
 750                         status = "disabled";
 751                 };
 752
 753                 nand0: nand@ff900000 {
 754                         #address-cells = <0x1>;
 755                         #size-cells = <0x1>;
 756                         compatible = "altr,socfpga-denali-nand";
 757                         reg = <0xff900000 0x100000>,
 758                               <0xffb80000 0x10000>;
 759                         reg-names = "nand_data", "denali_reg";
 760                         interrupts = <0x0 0x90 0x4>;
 761                         dma-mask = <0xffffffff>;
 762                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 763                         clock-names = "nand", "nand_x", "ecc";
 764                         status = "disabled";
 765                 };
 766
 767                 ocram: sram@ffff0000 {
 768                         compatible = "mmio-sram";
 769                         reg = <0xffff0000 0x10000>;
 770                 };
 771
 772                 qspi: spi@ff705000 {
 773                         compatible = "cdns,qspi-nor";
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776                         reg = <0xff705000 0x1000>,
 777                               <0xffa00000 0x1000>;
 778                         interrupts = <0 151 4>;
 779                         cdns,fifo-depth = <128>;
 780                         cdns,fifo-width = <4>;
 781                         cdns,trigger-address = <0x00000000>;
 782                         clocks = <&qspi_clk>;
 783                         status = "disabled";
 784                 };
 785
 786                 rst: rstmgr@ffd05000 {
 787                         #reset-cells = <1>;
 788                         compatible = "altr,rst-mgr";
 789                         reg = <0xffd05000 0x1000>;
 790                         altr,modrst-offset = <0x10>;
 791                 };
 792
 793                 scu: snoop-control-unit@fffec000 {
 794                         compatible = "arm,cortex-a9-scu";
 795                         reg = <0xfffec000 0x100>;
 796                 };
 797
 798                 sdr: sdr@ffc25000 {
 799                         compatible = "altr,sdr-ctl", "syscon";
 800                         reg = <0xffc25000 0x1000>;
 801                 };
 802
 803                 sdramedac {
 804                         compatible = "altr,sdram-edac";
 805                         altr,sdr-syscon = <&sdr>;
 806                         interrupts = <0 39 4>;
 807                 };
 808
 809                 spi0: spi@fff00000 {
 810                         compatible = "snps,dw-apb-ssi";
 811                         #address-cells = <1>;
 812                         #size-cells = <0>;
 813                         reg = <0xfff00000 0x1000>;
 814                         interrupts = <0 154 4>;
 815                         num-cs = <4>;
 816                         clocks = <&spi_m_clk>;
 817                         status = "disabled";
 818                 };
 819
 820                 spi1: spi@fff01000 {
 821                         compatible = "snps,dw-apb-ssi";
 822                         #address-cells = <1>;
 823                         #size-cells = <0>;
 824                         reg = <0xfff01000 0x1000>;
 825                         interrupts = <0 155 4>;
 826                         num-cs = <4>;
 827                         clocks = <&spi_m_clk>;
 828                         status = "disabled";
 829                 };
 830
 831                 sysmgr: sysmgr@ffd08000 {
 832                         compatible = "altr,sys-mgr", "syscon";
 833                         reg = <0xffd08000 0x4000>;
 834                 };
 835
 836                 /* Local timer */
 837                 timer@fffec600 {
 838                         compatible = "arm,cortex-a9-twd-timer";
 839                         reg = <0xfffec600 0x100>;
 840                         interrupts = <1 13 0xf01>;
 841                         clocks = <&mpu_periph_clk>;
 842                 };
 843
 844                 timer0: timer0@ffc08000 {
 845                         compatible = "snps,dw-apb-timer";
 846                         interrupts = <0 167 4>;
 847                         reg = <0xffc08000 0x1000>;
 848                         clocks = <&l4_sp_clk>;
 849                         clock-names = "timer";
 850                         resets = <&rst SPTIMER0_RESET>;
 851                         reset-names = "timer";
 852                 };
 853
 854                 timer1: timer1@ffc09000 {
 855                         compatible = "snps,dw-apb-timer";
 856                         interrupts = <0 168 4>;
 857                         reg = <0xffc09000 0x1000>;
 858                         clocks = <&l4_sp_clk>;
 859                         clock-names = "timer";
 860                         resets = <&rst SPTIMER1_RESET>;
 861                         reset-names = "timer";
 862                 };
 863
 864                 timer2: timer2@ffd00000 {
 865                         compatible = "snps,dw-apb-timer";
 866                         interrupts = <0 169 4>;
 867                         reg = <0xffd00000 0x1000>;
 868                         clocks = <&osc1>;
 869                         clock-names = "timer";
 870                         resets = <&rst OSC1TIMER0_RESET>;
 871                         reset-names = "timer";
 872                 };
 873
 874                 timer3: timer3@ffd01000 {
 875                         compatible = "snps,dw-apb-timer";
 876                         interrupts = <0 170 4>;
 877                         reg = <0xffd01000 0x1000>;
 878                         clocks = <&osc1>;
 879                         clock-names = "timer";
 880                         resets = <&rst OSC1TIMER1_RESET>;
 881                         reset-names = "timer";
 882                 };
 883
 884                 uart0: serial0@ffc02000 {
 885                         compatible = "snps,dw-apb-uart";
 886                         reg = <0xffc02000 0x1000>;
 887                         interrupts = <0 162 4>;
 888                         reg-shift = <2>;
 889                         reg-io-width = <4>;
 890                         clocks = <&l4_sp_clk>;
 891                         dmas = <&pdma 28>,
 892                                <&pdma 29>;
 893                         dma-names = "tx", "rx";
 894                 };
 895
 896                 uart1: serial1@ffc03000 {
 897                         compatible = "snps,dw-apb-uart";
 898                         reg = <0xffc03000 0x1000>;
 899                         interrupts = <0 163 4>;
 900                         reg-shift = <2>;
 901                         reg-io-width = <4>;
 902                         clocks = <&l4_sp_clk>;
 903                         dmas = <&pdma 30>,
 904                                <&pdma 31>;
 905                         dma-names = "tx", "rx";
 906                 };
 907
 908                 usbphy0: usbphy {
 909                         #phy-cells = <0>;
 910                         compatible = "usb-nop-xceiv";
 911                         status = "okay";
 912                 };
 913
 914                 usb0: usb@ffb00000 {
 915                         compatible = "snps,dwc2";
 916                         reg = <0xffb00000 0xffff>;
 917                         interrupts = <0 125 4>;
 918                         clocks = <&usb_mp_clk>;
 919                         clock-names = "otg";
 920                         resets = <&rst USB0_RESET>;
 921                         reset-names = "dwc2";
 922                         phys = <&usbphy0>;
 923                         phy-names = "usb2-phy";
 924                         status = "disabled";
 925                 };
 926
 927                 usb1: usb@ffb40000 {
 928                         compatible = "snps,dwc2";
 929                         reg = <0xffb40000 0xffff>;
 930                         interrupts = <0 128 4>;
 931                         clocks = <&usb_mp_clk>;
 932                         clock-names = "otg";
 933                         resets = <&rst USB1_RESET>;
 934                         reset-names = "dwc2";
 935                         phys = <&usbphy0>;
 936                         phy-names = "usb2-phy";
 937                         status = "disabled";
 938                 };
 939
 940                 watchdog0: watchdog@ffd02000 {
 941                         compatible = "snps,dw-wdt";
 942                         reg = <0xffd02000 0x1000>;
 943                         interrupts = <0 171 4>;
 944                         clocks = <&osc1>;
 945                         status = "disabled";
 946                 };
 947
 948                 watchdog1: watchdog@ffd03000 {
 949                         compatible = "snps,dw-wdt";
 950                         reg = <0xffd03000 0x1000>;
 951                         interrupts = <0 172 4>;
 952                         clocks = <&osc1>;
 953                         status = "disabled";
 954                 };
 955         };
 956 };