2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
37 compatible = "arm,amba-bus";
42 dmac1_s: dma-controller@20018000 {
43 compatible = "arm,pl330", "arm,primecell";
44 reg = <0x20018000 0x4000>;
45 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&cru ACLK_DMA1>;
49 clock-names = "apb_pclk";
52 dmac1_ns: dma-controller@2001c000 {
53 compatible = "arm,pl330", "arm,primecell";
54 reg = <0x2001c000 0x4000>;
55 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&cru ACLK_DMA1>;
59 clock-names = "apb_pclk";
63 dmac2: dma-controller@20078000 {
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&cru ACLK_DMA2>;
70 clock-names = "apb_pclk";
75 compatible = "fixed-clock";
76 clock-frequency = <24000000>;
78 clock-output-names = "xin24m";
81 L2: l2-cache-controller@10138000 {
82 compatible = "arm,pl310-cache";
83 reg = <0x10138000 0x1000>;
89 compatible = "arm,cortex-a9-scu";
90 reg = <0x1013c000 0x100>;
93 global_timer: global-timer@1013c200 {
94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0x1013c200 0x20>;
96 interrupts = <GIC_PPI 11 0x304>;
97 clocks = <&cru CORE_PERI>;
100 local_timer: local-timer@1013c600 {
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0x1013c600 0x20>;
103 interrupts = <GIC_PPI 13 0x304>;
104 clocks = <&cru CORE_PERI>;
107 gic: interrupt-controller@1013d000 {
108 compatible = "arm,cortex-a9-gic";
109 interrupt-controller;
110 #interrupt-cells = <3>;
111 reg = <0x1013d000 0x1000>,
115 uart0: serial@10124000 {
116 compatible = "snps,dw-apb-uart";
117 reg = <0x10124000 0x400>;
118 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
121 clock-names = "baudclk", "apb_pclk";
122 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
126 uart1: serial@10126000 {
127 compatible = "snps,dw-apb-uart";
128 reg = <0x10126000 0x400>;
129 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
132 clock-names = "baudclk", "apb_pclk";
133 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 usb_otg: usb@10180000 {
138 compatible = "rockchip,rk3066-usb", "snps,dwc2";
139 reg = <0x10180000 0x40000>;
140 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cru HCLK_OTG0>;
146 usb_host: usb@101c0000 {
147 compatible = "snps,dwc2";
148 reg = <0x101c0000 0x40000>;
149 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&cru HCLK_OTG1>;
155 mmc0: dwmmc@10214000 {
156 compatible = "rockchip,rk2928-dw-mshc";
157 reg = <0x10214000 0x1000>;
158 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
161 clock-names = "biu", "ciu";
166 mmc1: dwmmc@10218000 {
167 compatible = "rockchip,rk2928-dw-mshc";
168 reg = <0x10218000 0x1000>;
169 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
172 clock-names = "biu", "ciu";
177 emmc: dwmmc@1021c000 {
178 compatible = "rockchip,rk2928-dw-mshc";
179 reg = <0x1021c000 0x1000>;
180 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
183 clock-names = "biu", "ciu";
189 compatible = "rockchip,rk3066-pmu", "syscon";
190 reg = <0x20004000 0x100>;
194 compatible = "syscon";
195 reg = <0x20008000 0x200>;
199 compatible = "rockchip,rk3066-i2c";
200 reg = <0x2002d000 0x1000>;
201 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
202 #address-cells = <1>;
205 rockchip,grf = <&grf>;
208 clocks = <&cru PCLK_I2C0>;
214 compatible = "rockchip,rk3066-i2c";
215 reg = <0x2002f000 0x1000>;
216 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>;
220 rockchip,grf = <&grf>;
222 clocks = <&cru PCLK_I2C1>;
229 compatible = "rockchip,rk2928-pwm";
230 reg = <0x20030000 0x10>;
232 clocks = <&cru PCLK_PWM01>;
237 compatible = "rockchip,rk2928-pwm";
238 reg = <0x20030010 0x10>;
240 clocks = <&cru PCLK_PWM01>;
244 wdt: watchdog@2004c000 {
245 compatible = "snps,dw-wdt";
246 reg = <0x2004c000 0x100>;
247 clocks = <&cru PCLK_WDT>;
248 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
253 compatible = "rockchip,rk2928-pwm";
254 reg = <0x20050020 0x10>;
256 clocks = <&cru PCLK_PWM23>;
261 compatible = "rockchip,rk2928-pwm";
262 reg = <0x20050030 0x10>;
264 clocks = <&cru PCLK_PWM23>;
269 compatible = "rockchip,rk3066-i2c";
270 reg = <0x20056000 0x1000>;
271 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
272 #address-cells = <1>;
275 rockchip,grf = <&grf>;
277 clocks = <&cru PCLK_I2C2>;
284 compatible = "rockchip,rk3066-i2c";
285 reg = <0x2005a000 0x1000>;
286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
290 rockchip,grf = <&grf>;
292 clocks = <&cru PCLK_I2C3>;
299 compatible = "rockchip,rk3066-i2c";
300 reg = <0x2005e000 0x1000>;
301 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
302 #address-cells = <1>;
305 rockchip,grf = <&grf>;
307 clocks = <&cru PCLK_I2C4>;
313 uart2: serial@20064000 {
314 compatible = "snps,dw-apb-uart";
315 reg = <0x20064000 0x400>;
316 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
319 clock-names = "baudclk", "apb_pclk";
320 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
324 uart3: serial@20068000 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0x20068000 0x400>;
327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
330 clock-names = "baudclk", "apb_pclk";
331 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
335 saradc: saradc@2006c000 {
336 compatible = "rockchip,saradc";
337 reg = <0x2006c000 0x100>;
338 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
339 #io-channel-cells = <1>;
340 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
341 clock-names = "saradc", "apb_pclk";
346 compatible = "rockchip,rk3066-spi";
347 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
348 clock-names = "spiclk", "apb_pclk";
349 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
350 reg = <0x20070000 0x1000>;
351 #address-cells = <1>;
357 compatible = "rockchip,rk3066-spi";
358 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
359 clock-names = "spiclk", "apb_pclk";
360 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
361 reg = <0x20074000 0x1000>;
362 #address-cells = <1>;