arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "simple-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         clocks = <&cru ACLK_DMAC2>;
 150                         clock-names = "apb_pclk";
 151                 };
 152
 153                 dmac_bus_ns: dma-controller@ff600000 {
 154                         compatible = "arm,pl330", "arm,primecell";
 155                         reg = <0xff600000 0x4000>;
 156                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 158                         #dma-cells = <1>;
 159                         arm,pl330-broken-no-flushp;
 160                         clocks = <&cru ACLK_DMAC1>;
 161                         clock-names = "apb_pclk";
 162                         status = "disabled";
 163                 };
 164
 165                 dmac_bus_s: dma-controller@ffb20000 {
 166                         compatible = "arm,pl330", "arm,primecell";
 167                         reg = <0xffb20000 0x4000>;
 168                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 170                         #dma-cells = <1>;
 171                         arm,pl330-broken-no-flushp;
 172                         clocks = <&cru ACLK_DMAC1>;
 173                         clock-names = "apb_pclk";
 174                 };
 175         };
 176
 177         reserved-memory {
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 ranges;
 181
 182                 /*
 183                  * The rk3288 cannot use the memory area above 0xfe000000
 184                  * for dma operations for some reason. While there is
 185                  * probably a better solution available somewhere, we
 186                  * haven't found it yet and while devices with 2GB of ram
 187                  * are not affected, this issue prevents 4GB from booting.
 188                  * So to make these devices at least bootable, block
 189                  * this area for the time being until the real solution
 190                  * is found.
 191                  */
 192                 dma-unusable@fe000000 {
 193                         reg = <0xfe000000 0x1000000>;
 194                 };
 195         };
 196
 197         xin24m: oscillator {
 198                 compatible = "fixed-clock";
 199                 clock-frequency = <24000000>;
 200                 clock-output-names = "xin24m";
 201                 #clock-cells = <0>;
 202         };
 203
 204         timer {
 205                 compatible = "arm,armv7-timer";
 206                 arm,cpu-registers-not-fw-configured;
 207                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 208                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 210                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 211                 clock-frequency = <24000000>;
 212         };
 213
 214         timer: timer@ff810000 {
 215                 compatible = "rockchip,rk3288-timer";
 216                 reg = <0xff810000 0x20>;
 217                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 219                 clock-names = "timer", "pclk";
 220         };
 221
 222         display-subsystem {
 223                 compatible = "rockchip,display-subsystem";
 224                 ports = <&vopl_out>, <&vopb_out>;
 225         };
 226
 227         sdmmc: dwmmc@ff0c0000 {
 228                 compatible = "rockchip,rk3288-dw-mshc";
 229                 clock-freq-min-max = <400000 150000000>;
 230                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 231                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 232                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 233                 fifo-depth = <0x100>;
 234                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 235                 reg = <0xff0c0000 0x4000>;
 236                 status = "disabled";
 237         };
 238
 239         sdio0: dwmmc@ff0d0000 {
 240                 compatible = "rockchip,rk3288-dw-mshc";
 241                 clock-freq-min-max = <400000 150000000>;
 242                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 243                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 244                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 245                 fifo-depth = <0x100>;
 246                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg = <0xff0d0000 0x4000>;
 248                 status = "disabled";
 249         };
 250
 251         sdio1: dwmmc@ff0e0000 {
 252                 compatible = "rockchip,rk3288-dw-mshc";
 253                 clock-freq-min-max = <400000 150000000>;
 254                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 255                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 256                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 259                 reg = <0xff0e0000 0x4000>;
 260                 status = "disabled";
 261         };
 262
 263         emmc: dwmmc@ff0f0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 267                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0xff0f0000 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         saradc: saradc@ff100000 {
 276                 compatible = "rockchip,saradc";
 277                 reg = <0xff100000 0x100>;
 278                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 279                 #io-channel-cells = <1>;
 280                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 281                 clock-names = "saradc", "apb_pclk";
 282                 resets = <&cru SRST_SARADC>;
 283                 reset-names = "saradc-apb";
 284                 status = "disabled";
 285         };
 286
 287         spi0: spi@ff110000 {
 288                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 289                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 290                 clock-names = "spiclk", "apb_pclk";
 291                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 292                 dma-names = "tx", "rx";
 293                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 296                 reg = <0xff110000 0x1000>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 status = "disabled";
 300         };
 301
 302         spi1: spi@ff120000 {
 303                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 304                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 305                 clock-names = "spiclk", "apb_pclk";
 306                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 307                 dma-names = "tx", "rx";
 308                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 311                 reg = <0xff120000 0x1000>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 status = "disabled";
 315         };
 316
 317         spi2: spi@ff130000 {
 318                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 319                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 320                 clock-names = "spiclk", "apb_pclk";
 321                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 322                 dma-names = "tx", "rx";
 323                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 326                 reg = <0xff130000 0x1000>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 status = "disabled";
 330         };
 331
 332         i2c1: i2c@ff140000 {
 333                 compatible = "rockchip,rk3288-i2c";
 334                 reg = <0xff140000 0x1000>;
 335                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 clock-names = "i2c";
 339                 clocks = <&cru PCLK_I2C1>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&i2c1_xfer>;
 342                 status = "disabled";
 343         };
 344
 345         i2c3: i2c@ff150000 {
 346                 compatible = "rockchip,rk3288-i2c";
 347                 reg = <0xff150000 0x1000>;
 348                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clock-names = "i2c";
 352                 clocks = <&cru PCLK_I2C3>;
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&i2c3_xfer>;
 355                 status = "disabled";
 356         };
 357
 358         i2c4: i2c@ff160000 {
 359                 compatible = "rockchip,rk3288-i2c";
 360                 reg = <0xff160000 0x1000>;
 361                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clock-names = "i2c";
 365                 clocks = <&cru PCLK_I2C4>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c4_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c5: i2c@ff170000 {
 372                 compatible = "rockchip,rk3288-i2c";
 373                 reg = <0xff170000 0x1000>;
 374                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C5>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c5_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         uart0: serial@ff180000 {
 385                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 386                 reg = <0xff180000 0x100>;
 387                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 388                 reg-shift = <2>;
 389                 reg-io-width = <4>;
 390                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 391                 clock-names = "baudclk", "apb_pclk";
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&uart0_xfer>;
 394                 status = "disabled";
 395         };
 396
 397         uart1: serial@ff190000 {
 398                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 399                 reg = <0xff190000 0x100>;
 400                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 401                 reg-shift = <2>;
 402                 reg-io-width = <4>;
 403                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 404                 clock-names = "baudclk", "apb_pclk";
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&uart1_xfer>;
 407                 status = "disabled";
 408         };
 409
 410         uart2: serial@ff690000 {
 411                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 412                 reg = <0xff690000 0x100>;
 413                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&uart2_xfer>;
 420                 status = "disabled";
 421         };
 422
 423         uart3: serial@ff1b0000 {
 424                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 425                 reg = <0xff1b0000 0x100>;
 426                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 427                 reg-shift = <2>;
 428                 reg-io-width = <4>;
 429                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 430                 clock-names = "baudclk", "apb_pclk";
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&uart3_xfer>;
 433                 status = "disabled";
 434         };
 435
 436         uart4: serial@ff1c0000 {
 437                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 438                 reg = <0xff1c0000 0x100>;
 439                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 440                 reg-shift = <2>;
 441                 reg-io-width = <4>;
 442                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 443                 clock-names = "baudclk", "apb_pclk";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&uart4_xfer>;
 446                 status = "disabled";
 447         };
 448
 449         thermal-zones {
 450                 reserve_thermal: reserve_thermal {
 451                         polling-delay-passive = <1000>; /* milliseconds */
 452                         polling-delay = <5000>; /* milliseconds */
 453
 454                         thermal-sensors = <&tsadc 0>;
 455                 };
 456
 457                 cpu_thermal: cpu_thermal {
 458                         polling-delay-passive = <100>; /* milliseconds */
 459                         polling-delay = <5000>; /* milliseconds */
 460
 461                         thermal-sensors = <&tsadc 1>;
 462
 463                         trips {
 464                                 cpu_alert0: cpu_alert0 {
 465                                         temperature = <70000>; /* millicelsius */
 466                                         hysteresis = <2000>; /* millicelsius */
 467                                         type = "passive";
 468                                 };
 469                                 cpu_alert1: cpu_alert1 {
 470                                         temperature = <75000>; /* millicelsius */
 471                                         hysteresis = <2000>; /* millicelsius */
 472                                         type = "passive";
 473                                 };
 474                                 cpu_crit: cpu_crit {
 475                                         temperature = <90000>; /* millicelsius */
 476                                         hysteresis = <2000>; /* millicelsius */
 477                                         type = "critical";
 478                                 };
 479                         };
 480
 481                         cooling-maps {
 482                                 map0 {
 483                                         trip = <&cpu_alert0>;
 484                                         cooling-device =
 485                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 486                                 };
 487                                 map1 {
 488                                         trip = <&cpu_alert1>;
 489                                         cooling-device =
 490                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 491                                 };
 492                         };
 493                 };
 494
 495                 gpu_thermal: gpu_thermal {
 496                         polling-delay-passive = <100>; /* milliseconds */
 497                         polling-delay = <5000>; /* milliseconds */
 498
 499                         thermal-sensors = <&tsadc 2>;
 500
 501                         trips {
 502                                 gpu_alert0: gpu_alert0 {
 503                                         temperature = <70000>; /* millicelsius */
 504                                         hysteresis = <2000>; /* millicelsius */
 505                                         type = "passive";
 506                                 };
 507                                 gpu_crit: gpu_crit {
 508                                         temperature = <90000>; /* millicelsius */
 509                                         hysteresis = <2000>; /* millicelsius */
 510                                         type = "critical";
 511                                 };
 512                         };
 513
 514                         cooling-maps {
 515                                 map0 {
 516                                         trip = <&gpu_alert0>;
 517                                         cooling-device =
 518                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 519                                 };
 520                         };
 521                 };
 522         };
 523
 524         tsadc: tsadc@ff280000 {
 525                 compatible = "rockchip,rk3288-tsadc";
 526                 reg = <0xff280000 0x100>;
 527                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 528                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 529                 clock-names = "tsadc", "apb_pclk";
 530                 resets = <&cru SRST_TSADC>;
 531                 reset-names = "tsadc-apb";
 532                 pinctrl-names = "init", "default", "sleep";
 533                 pinctrl-0 = <&otp_gpio>;
 534                 pinctrl-1 = <&otp_out>;
 535                 pinctrl-2 = <&otp_gpio>;
 536                 #thermal-sensor-cells = <1>;
 537                 rockchip,hw-tshut-temp = <95000>;
 538                 status = "disabled";
 539         };
 540
 541         gmac: ethernet@ff290000 {
 542                 compatible = "rockchip,rk3288-gmac";
 543                 reg = <0xff290000 0x10000>;
 544                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 545                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 546                 interrupt-names = "macirq", "eth_wake_irq";
 547                 rockchip,grf = <&grf>;
 548                 clocks = <&cru SCLK_MAC>,
 549                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 550                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 551                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 552                 clock-names = "stmmaceth",
 553                         "mac_clk_rx", "mac_clk_tx",
 554                         "clk_mac_ref", "clk_mac_refout",
 555                         "aclk_mac", "pclk_mac";
 556                 resets = <&cru SRST_MAC>;
 557                 reset-names = "stmmaceth";
 558                 status = "disabled";
 559         };
 560
 561         usb_host0_ehci: usb@ff500000 {
 562                 compatible = "generic-ehci";
 563                 reg = <0xff500000 0x100>;
 564                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 565                 clocks = <&cru HCLK_USBHOST0>;
 566                 clock-names = "usbhost";
 567                 phys = <&usbphy1>;
 568                 phy-names = "usb";
 569                 status = "disabled";
 570         };
 571
 572         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 573
 574         usb_host1: usb@ff540000 {
 575                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 576                                 "snps,dwc2";
 577                 reg = <0xff540000 0x40000>;
 578                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&cru HCLK_USBHOST1>;
 580                 clock-names = "otg";
 581                 dr_mode = "host";
 582                 phys = <&usbphy2>;
 583                 phy-names = "usb2-phy";
 584                 status = "disabled";
 585         };
 586
 587         usb_otg: usb@ff580000 {
 588                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 589                                 "snps,dwc2";
 590                 reg = <0xff580000 0x40000>;
 591                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&cru HCLK_OTG0>;
 593                 clock-names = "otg";
 594                 dr_mode = "otg";
 595                 g-np-tx-fifo-size = <16>;
 596                 g-rx-fifo-size = <275>;
 597                 g-tx-fifo-size = <256 128 128 64 64 32>;
 598                 g-use-dma;
 599                 phys = <&usbphy0>;
 600                 phy-names = "usb2-phy";
 601                 status = "disabled";
 602         };
 603
 604         usb_hsic: usb@ff5c0000 {
 605                 compatible = "generic-ehci";
 606                 reg = <0xff5c0000 0x100>;
 607                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 608                 clocks = <&cru HCLK_HSIC>;
 609                 clock-names = "usbhost";
 610                 status = "disabled";
 611         };
 612
 613         i2c0: i2c@ff650000 {
 614                 compatible = "rockchip,rk3288-i2c";
 615                 reg = <0xff650000 0x1000>;
 616                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 clock-names = "i2c";
 620                 clocks = <&cru PCLK_I2C0>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&i2c0_xfer>;
 623                 status = "disabled";
 624         };
 625
 626         i2c2: i2c@ff660000 {
 627                 compatible = "rockchip,rk3288-i2c";
 628                 reg = <0xff660000 0x1000>;
 629                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 clock-names = "i2c";
 633                 clocks = <&cru PCLK_I2C2>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&i2c2_xfer>;
 636                 status = "disabled";
 637         };
 638
 639         pwm0: pwm@ff680000 {
 640                 compatible = "rockchip,rk3288-pwm";
 641                 reg = <0xff680000 0x10>;
 642                 #pwm-cells = <3>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&pwm0_pin>;
 645                 clocks = <&cru PCLK_PWM>;
 646                 clock-names = "pwm";
 647                 status = "disabled";
 648         };
 649
 650         pwm1: pwm@ff680010 {
 651                 compatible = "rockchip,rk3288-pwm";
 652                 reg = <0xff680010 0x10>;
 653                 #pwm-cells = <3>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&pwm1_pin>;
 656                 clocks = <&cru PCLK_PWM>;
 657                 clock-names = "pwm";
 658                 status = "disabled";
 659         };
 660
 661         pwm2: pwm@ff680020 {
 662                 compatible = "rockchip,rk3288-pwm";
 663                 reg = <0xff680020 0x10>;
 664                 #pwm-cells = <3>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&pwm2_pin>;
 667                 clocks = <&cru PCLK_PWM>;
 668                 clock-names = "pwm";
 669                 status = "disabled";
 670         };
 671
 672         pwm3: pwm@ff680030 {
 673                 compatible = "rockchip,rk3288-pwm";
 674                 reg = <0xff680030 0x10>;
 675                 #pwm-cells = <2>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&pwm3_pin>;
 678                 clocks = <&cru PCLK_PWM>;
 679                 clock-names = "pwm";
 680                 status = "disabled";
 681         };
 682
 683         bus_intmem@ff700000 {
 684                 compatible = "mmio-sram";
 685                 reg = <0xff700000 0x18000>;
 686                 #address-cells = <1>;
 687                 #size-cells = <1>;
 688                 ranges = <0 0xff700000 0x18000>;
 689                 smp-sram@0 {
 690                         compatible = "rockchip,rk3066-smp-sram";
 691                         reg = <0x00 0x10>;
 692                 };
 693         };
 694
 695         sram@ff720000 {
 696                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 697                 reg = <0xff720000 0x1000>;
 698         };
 699
 700         pmu: power-management@ff730000 {
 701                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 702                 reg = <0xff730000 0x100>;
 703
 704                 power: power-controller {
 705                         compatible = "rockchip,rk3288-power-controller";
 706                         #power-domain-cells = <1>;
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709
 710                         assigned-clocks = <&cru SCLK_EDP_24M>;
 711                         assigned-clock-parents = <&xin24m>;
 712
 713                         /*
 714                          * Note: Although SCLK_* are the working clocks
 715                          * of device without including on the NOC, needed for
 716                          * synchronous reset.
 717                          *
 718                          * The clocks on the which NOC:
 719                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 720                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 721                          * ACLK_RGA is on ACLK_RGA_NIU.
 722                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 723                          *
 724                          * Which clock are device clocks:
 725                          *      clocks          devices
 726                          *      *_IEP           IEP:Image Enhancement Processor
 727                          *      *_ISP           ISP:Image Signal Processing
 728                          *      *_VIP           VIP:Video Input Processor
 729                          *      *_VOP*          VOP:Visual Output Processor
 730                          *      *_RGA           RGA
 731                          *      *_EDP*          EDP
 732                          *      *_LVDS_*        LVDS
 733                          *      *_HDMI          HDMI
 734                          *      *_MIPI_*        MIPI
 735                          */
 736                         pd_vio@RK3288_PD_VIO {
 737                                 reg = <RK3288_PD_VIO>;
 738                                 clocks = <&cru ACLK_IEP>,
 739                                          <&cru ACLK_ISP>,
 740                                          <&cru ACLK_RGA>,
 741                                          <&cru ACLK_VIP>,
 742                                          <&cru ACLK_VOP0>,
 743                                          <&cru ACLK_VOP1>,
 744                                          <&cru DCLK_VOP0>,
 745                                          <&cru DCLK_VOP1>,
 746                                          <&cru HCLK_IEP>,
 747                                          <&cru HCLK_ISP>,
 748                                          <&cru HCLK_RGA>,
 749                                          <&cru HCLK_VIP>,
 750                                          <&cru HCLK_VOP0>,
 751                                          <&cru HCLK_VOP1>,
 752                                          <&cru PCLK_EDP_CTRL>,
 753                                          <&cru PCLK_HDMI_CTRL>,
 754                                          <&cru PCLK_LVDS_PHY>,
 755                                          <&cru PCLK_MIPI_CSI>,
 756                                          <&cru PCLK_MIPI_DSI0>,
 757                                          <&cru PCLK_MIPI_DSI1>,
 758                                          <&cru SCLK_EDP_24M>,
 759                                          <&cru SCLK_EDP>,
 760                                          <&cru SCLK_ISP_JPE>,
 761                                          <&cru SCLK_ISP>,
 762                                          <&cru SCLK_RGA>;
 763                         };
 764
 765                         /*
 766                          * Note: The following 3 are HEVC(H.265) clocks,
 767                          * and on the ACLK_HEVC_NIU (NOC).
 768                          */
 769                         pd_hevc@RK3288_PD_HEVC {
 770                                 reg = <RK3288_PD_HEVC>;
 771                                 clocks = <&cru ACLK_HEVC>,
 772                                          <&cru SCLK_HEVC_CABAC>,
 773                                          <&cru SCLK_HEVC_CORE>;
 774                         };
 775
 776                         /*
 777                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 778                          * (video endecoder & decoder) clocks that on the
 779                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 780                          */
 781                         pd_video@RK3288_PD_VIDEO {
 782                                 reg = <RK3288_PD_VIDEO>;
 783                                 clocks = <&cru ACLK_VCODEC>,
 784                                          <&cru HCLK_VCODEC>;
 785                         };
 786
 787                         /*
 788                          * Note: ACLK_GPU is the GPU clock,
 789                          * and on the ACLK_GPU_NIU (NOC).
 790                          */
 791                         pd_gpu@RK3288_PD_GPU {
 792                                 reg = <RK3288_PD_GPU>;
 793                                 clocks = <&cru ACLK_GPU>;
 794                         };
 795                 };
 796         };
 797
 798         sgrf: syscon@ff740000 {
 799                 compatible = "rockchip,rk3288-sgrf", "syscon";
 800                 reg = <0xff740000 0x1000>;
 801         };
 802
 803         cru: clock-controller@ff760000 {
 804                 compatible = "rockchip,rk3288-cru";
 805                 reg = <0xff760000 0x1000>;
 806                 rockchip,grf = <&grf>;
 807                 #clock-cells = <1>;
 808                 #reset-cells = <1>;
 809                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 810                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 811                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 812                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 813                                   <&cru PCLK_PERI>;
 814                 assigned-clock-rates = <594000000>, <400000000>,
 815                                        <500000000>, <300000000>,
 816                                        <150000000>, <75000000>,
 817                                        <300000000>, <150000000>,
 818                                        <75000000>;
 819         };
 820
 821         grf: syscon@ff770000 {
 822                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 823                 reg = <0xff770000 0x1000>;
 824
 825                 edp_phy: edp-phy {
 826                         compatible = "rockchip,rk3288-dp-phy";
 827                         clocks = <&cru SCLK_EDP_24M>;
 828                         clock-names = "24m";
 829                         #phy-cells = <0>;
 830                         status = "disabled";
 831                 };
 832
 833                 io_domains: io-domains {
 834                         compatible = "rockchip,rk3288-io-voltage-domain";
 835                         status = "disabled";
 836                 };
 837         };
 838
 839         wdt: watchdog@ff800000 {
 840                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 841                 reg = <0xff800000 0x100>;
 842                 clocks = <&cru PCLK_WDT>;
 843                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 844                 status = "disabled";
 845         };
 846
 847         spdif: sound@ff88b0000 {
 848                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 849                 reg = <0xff8b0000 0x10000>;
 850                 #sound-dai-cells = <0>;
 851                 clock-names = "hclk", "mclk";
 852                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 853                 dmas = <&dmac_bus_s 3>;
 854                 dma-names = "tx";
 855                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 856                 pinctrl-names = "default";
 857                 pinctrl-0 = <&spdif_tx>;
 858                 rockchip,grf = <&grf>;
 859                 status = "disabled";
 860         };
 861
 862         i2s: i2s@ff890000 {
 863                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 864                 reg = <0xff890000 0x10000>;
 865                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 866                 #address-cells = <1>;
 867                 #size-cells = <0>;
 868                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 869                 dma-names = "tx", "rx";
 870                 clock-names = "i2s_hclk", "i2s_clk";
 871                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 872                 pinctrl-names = "default";
 873                 pinctrl-0 = <&i2s0_bus>;
 874                 rockchip,playback-channels = <8>;
 875                 rockchip,capture-channels = <2>;
 876                 status = "disabled";
 877         };
 878
 879         crypto: cypto-controller@ff8a0000 {
 880                 compatible = "rockchip,rk3288-crypto";
 881                 reg = <0xff8a0000 0x4000>;
 882                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 883                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 884                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 885                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 886                 resets = <&cru SRST_CRYPTO>;
 887                 reset-names = "crypto-rst";
 888                 status = "okay";
 889         };
 890
 891         vopb: vop@ff930000 {
 892                 compatible = "rockchip,rk3288-vop";
 893                 reg = <0xff930000 0x19c>;
 894                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 895                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 896                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 897                 power-domains = <&power RK3288_PD_VIO>;
 898                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 899                 reset-names = "axi", "ahb", "dclk";
 900                 iommus = <&vopb_mmu>;
 901                 status = "disabled";
 902
 903                 vopb_out: port {
 904                         #address-cells = <1>;
 905                         #size-cells = <0>;
 906
 907                         vopb_out_hdmi: endpoint@0 {
 908                                 reg = <0>;
 909                                 remote-endpoint = <&hdmi_in_vopb>;
 910                         };
 911
 912                         vopb_out_edp: endpoint@1 {
 913                                 reg = <1>;
 914                                 remote-endpoint = <&edp_in_vopb>;
 915                         };
 916
 917                         vopb_out_mipi: endpoint@2 {
 918                                 reg = <2>;
 919                                 remote-endpoint = <&mipi_in_vopb>;
 920                         };
 921                 };
 922         };
 923
 924         vopb_mmu: iommu@ff930300 {
 925                 compatible = "rockchip,iommu";
 926                 reg = <0xff930300 0x100>;
 927                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 928                 interrupt-names = "vopb_mmu";
 929                 power-domains = <&power RK3288_PD_VIO>;
 930                 #iommu-cells = <0>;
 931                 status = "disabled";
 932         };
 933
 934         vopl: vop@ff940000 {
 935                 compatible = "rockchip,rk3288-vop";
 936                 reg = <0xff940000 0x19c>;
 937                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 938                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 939                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 940                 power-domains = <&power RK3288_PD_VIO>;
 941                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 942                 reset-names = "axi", "ahb", "dclk";
 943                 iommus = <&vopl_mmu>;
 944                 status = "disabled";
 945
 946                 vopl_out: port {
 947                         #address-cells = <1>;
 948                         #size-cells = <0>;
 949
 950                         vopl_out_hdmi: endpoint@0 {
 951                                 reg = <0>;
 952                                 remote-endpoint = <&hdmi_in_vopl>;
 953                         };
 954
 955                         vopl_out_edp: endpoint@1 {
 956                                 reg = <1>;
 957                                 remote-endpoint = <&edp_in_vopl>;
 958                         };
 959
 960                         vopl_out_mipi: endpoint@2 {
 961                                 reg = <2>;
 962                                 remote-endpoint = <&mipi_in_vopl>;
 963                         };
 964                 };
 965         };
 966
 967         vopl_mmu: iommu@ff940300 {
 968                 compatible = "rockchip,iommu";
 969                 reg = <0xff940300 0x100>;
 970                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 971                 interrupt-names = "vopl_mmu";
 972                 power-domains = <&power RK3288_PD_VIO>;
 973                 #iommu-cells = <0>;
 974                 status = "disabled";
 975         };
 976
 977         mipi_dsi: mipi@ff960000 {
 978                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 979                 reg = <0xff960000 0x4000>;
 980                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 981                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 982                 clock-names = "ref", "pclk";
 983                 power-domains = <&power RK3288_PD_VIO>;
 984                 rockchip,grf = <&grf>;
 985                 #address-cells = <1>;
 986                 #size-cells = <0>;
 987                 status = "disabled";
 988
 989                 ports {
 990                         mipi_in: port {
 991                                 #address-cells = <1>;
 992                                 #size-cells = <0>;
 993                                 mipi_in_vopb: endpoint@0 {
 994                                         reg = <0>;
 995                                         remote-endpoint = <&vopb_out_mipi>;
 996                                 };
 997                                 mipi_in_vopl: endpoint@1 {
 998                                         reg = <1>;
 999                                         remote-endpoint = <&vopl_out_mipi>;
1000                                 };
1001                         };
1002                 };
1003         };
1004
1005         edp: dp@ff970000 {
1006                 compatible = "rockchip,rk3288-dp";
1007                 reg = <0xff970000 0x4000>;
1008                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1009                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1010                 clock-names = "dp", "pclk";
1011                 phys = <&edp_phy>;
1012                 phy-names = "dp";
1013                 resets = <&cru SRST_EDP>;
1014                 reset-names = "dp";
1015                 rockchip,grf = <&grf>;
1016                 status = "disabled";
1017
1018                 ports {
1019                         #address-cells = <1>;
1020                         #size-cells = <0>;
1021                         edp_in: port@0 {
1022                                 reg = <0>;
1023                                 #address-cells = <1>;
1024                                 #size-cells = <0>;
1025                                 edp_in_vopb: endpoint@0 {
1026                                         reg = <0>;
1027                                         remote-endpoint = <&vopb_out_edp>;
1028                                 };
1029                                 edp_in_vopl: endpoint@1 {
1030                                         reg = <1>;
1031                                         remote-endpoint = <&vopl_out_edp>;
1032                                 };
1033                         };
1034                 };
1035         };
1036
1037         hdmi: hdmi@ff980000 {
1038                 compatible = "rockchip,rk3288-dw-hdmi";
1039                 reg = <0xff980000 0x20000>;
1040                 reg-io-width = <4>;
1041                 rockchip,grf = <&grf>;
1042                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1043                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1044                 clock-names = "iahb", "isfr";
1045                 power-domains = <&power RK3288_PD_VIO>;
1046                 status = "disabled";
1047
1048                 ports {
1049                         hdmi_in: port {
1050                                 #address-cells = <1>;
1051                                 #size-cells = <0>;
1052                                 hdmi_in_vopb: endpoint@0 {
1053                                         reg = <0>;
1054                                         remote-endpoint = <&vopb_out_hdmi>;
1055                                 };
1056                                 hdmi_in_vopl: endpoint@1 {
1057                                         reg = <1>;
1058                                         remote-endpoint = <&vopl_out_hdmi>;
1059                                 };
1060                         };
1061                 };
1062         };
1063
1064         gic: interrupt-controller@ffc01000 {
1065                 compatible = "arm,gic-400";
1066                 interrupt-controller;
1067                 #interrupt-cells = <3>;
1068                 #address-cells = <0>;
1069
1070                 reg = <0xffc01000 0x1000>,
1071                       <0xffc02000 0x1000>,
1072                       <0xffc04000 0x2000>,
1073                       <0xffc06000 0x2000>;
1074                 interrupts = <GIC_PPI 9 0xf04>;
1075         };
1076
1077         efuse: efuse@ffb40000 {
1078                 compatible = "rockchip,rockchip-efuse";
1079                 reg = <0xffb40000 0x20>;
1080                 #address-cells = <1>;
1081                 #size-cells = <1>;
1082                 clocks = <&cru PCLK_EFUSE256>;
1083                 clock-names = "pclk_efuse";
1084
1085                 cpu_leakage: cpu_leakage@17 {
1086                         reg = <0x17 0x1>;
1087                 };
1088         };
1089
1090         usbphy: phy {
1091                 compatible = "rockchip,rk3288-usb-phy";
1092                 rockchip,grf = <&grf>;
1093                 #address-cells = <1>;
1094                 #size-cells = <0>;
1095                 status = "disabled";
1096
1097                 usbphy0: usb-phy@320 {
1098                         #phy-cells = <0>;
1099                         reg = <0x320>;
1100                         clocks = <&cru SCLK_OTGPHY0>;
1101                         clock-names = "phyclk";
1102                         #clock-cells = <0>;
1103                 };
1104
1105                 usbphy1: usb-phy@334 {
1106                         #phy-cells = <0>;
1107                         reg = <0x334>;
1108                         clocks = <&cru SCLK_OTGPHY1>;
1109                         clock-names = "phyclk";
1110                         #clock-cells = <0>;
1111                 };
1112
1113                 usbphy2: usb-phy@348 {
1114                         #phy-cells = <0>;
1115                         reg = <0x348>;
1116                         clocks = <&cru SCLK_OTGPHY2>;
1117                         clock-names = "phyclk";
1118                         #clock-cells = <0>;
1119                 };
1120         };
1121
1122         pinctrl: pinctrl {
1123                 compatible = "rockchip,rk3288-pinctrl";
1124                 rockchip,grf = <&grf>;
1125                 rockchip,pmu = <&pmu>;
1126                 #address-cells = <1>;
1127                 #size-cells = <1>;
1128                 ranges;
1129
1130                 gpio0: gpio0@ff750000 {
1131                         compatible = "rockchip,gpio-bank";
1132                         reg =   <0xff750000 0x100>;
1133                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1134                         clocks = <&cru PCLK_GPIO0>;
1135
1136                         gpio-controller;
1137                         #gpio-cells = <2>;
1138
1139                         interrupt-controller;
1140                         #interrupt-cells = <2>;
1141                 };
1142
1143                 gpio1: gpio1@ff780000 {
1144                         compatible = "rockchip,gpio-bank";
1145                         reg = <0xff780000 0x100>;
1146                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1147                         clocks = <&cru PCLK_GPIO1>;
1148
1149                         gpio-controller;
1150                         #gpio-cells = <2>;
1151
1152                         interrupt-controller;
1153                         #interrupt-cells = <2>;
1154                 };
1155
1156                 gpio2: gpio2@ff790000 {
1157                         compatible = "rockchip,gpio-bank";
1158                         reg = <0xff790000 0x100>;
1159                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1160                         clocks = <&cru PCLK_GPIO2>;
1161
1162                         gpio-controller;
1163                         #gpio-cells = <2>;
1164
1165                         interrupt-controller;
1166                         #interrupt-cells = <2>;
1167                 };
1168
1169                 gpio3: gpio3@ff7a0000 {
1170                         compatible = "rockchip,gpio-bank";
1171                         reg = <0xff7a0000 0x100>;
1172                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1173                         clocks = <&cru PCLK_GPIO3>;
1174
1175                         gpio-controller;
1176                         #gpio-cells = <2>;
1177
1178                         interrupt-controller;
1179                         #interrupt-cells = <2>;
1180                 };
1181
1182                 gpio4: gpio4@ff7b0000 {
1183                         compatible = "rockchip,gpio-bank";
1184                         reg = <0xff7b0000 0x100>;
1185                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1186                         clocks = <&cru PCLK_GPIO4>;
1187
1188                         gpio-controller;
1189                         #gpio-cells = <2>;
1190
1191                         interrupt-controller;
1192                         #interrupt-cells = <2>;
1193                 };
1194
1195                 gpio5: gpio5@ff7c0000 {
1196                         compatible = "rockchip,gpio-bank";
1197                         reg = <0xff7c0000 0x100>;
1198                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1199                         clocks = <&cru PCLK_GPIO5>;
1200
1201                         gpio-controller;
1202                         #gpio-cells = <2>;
1203
1204                         interrupt-controller;
1205                         #interrupt-cells = <2>;
1206                 };
1207
1208                 gpio6: gpio6@ff7d0000 {
1209                         compatible = "rockchip,gpio-bank";
1210                         reg = <0xff7d0000 0x100>;
1211                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1212                         clocks = <&cru PCLK_GPIO6>;
1213
1214                         gpio-controller;
1215                         #gpio-cells = <2>;
1216
1217                         interrupt-controller;
1218                         #interrupt-cells = <2>;
1219                 };
1220
1221                 gpio7: gpio7@ff7e0000 {
1222                         compatible = "rockchip,gpio-bank";
1223                         reg = <0xff7e0000 0x100>;
1224                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1225                         clocks = <&cru PCLK_GPIO7>;
1226
1227                         gpio-controller;
1228                         #gpio-cells = <2>;
1229
1230                         interrupt-controller;
1231                         #interrupt-cells = <2>;
1232                 };
1233
1234                 gpio8: gpio8@ff7f0000 {
1235                         compatible = "rockchip,gpio-bank";
1236                         reg = <0xff7f0000 0x100>;
1237                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1238                         clocks = <&cru PCLK_GPIO8>;
1239
1240                         gpio-controller;
1241                         #gpio-cells = <2>;
1242
1243                         interrupt-controller;
1244                         #interrupt-cells = <2>;
1245                 };
1246
1247                 hdmi {
1248                         hdmi_ddc: hdmi-ddc {
1249                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1250                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1251                         };
1252                 };
1253
1254                 pcfg_pull_up: pcfg-pull-up {
1255                         bias-pull-up;
1256                 };
1257
1258                 pcfg_pull_down: pcfg-pull-down {
1259                         bias-pull-down;
1260                 };
1261
1262                 pcfg_pull_none: pcfg-pull-none {
1263                         bias-disable;
1264                 };
1265
1266                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1267                         bias-disable;
1268                         drive-strength = <12>;
1269                 };
1270
1271                 sleep {
1272                         global_pwroff: global-pwroff {
1273                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1274                         };
1275
1276                         ddrio_pwroff: ddrio-pwroff {
1277                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1278                         };
1279
1280                         ddr0_retention: ddr0-retention {
1281                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1282                         };
1283
1284                         ddr1_retention: ddr1-retention {
1285                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1286                         };
1287                 };
1288
1289                 edp {
1290                         edp_hpd: edp-hpd {
1291                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1292                         };
1293                 };
1294
1295                 i2c0 {
1296                         i2c0_xfer: i2c0-xfer {
1297                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1298                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1299                         };
1300                 };
1301
1302                 i2c1 {
1303                         i2c1_xfer: i2c1-xfer {
1304                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1305                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1306                         };
1307                 };
1308
1309                 i2c2 {
1310                         i2c2_xfer: i2c2-xfer {
1311                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1312                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314                 };
1315
1316                 i2c3 {
1317                         i2c3_xfer: i2c3-xfer {
1318                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1319                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1320                         };
1321                 };
1322
1323                 i2c4 {
1324                         i2c4_xfer: i2c4-xfer {
1325                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1326                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1327                         };
1328                 };
1329
1330                 i2c5 {
1331                         i2c5_xfer: i2c5-xfer {
1332                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1333                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1334                         };
1335                 };
1336
1337                 i2s0 {
1338                         i2s0_bus: i2s0-bus {
1339                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1340                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1341                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1342                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1343                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1344                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1345                         };
1346                 };
1347
1348                 sdmmc {
1349                         sdmmc_clk: sdmmc-clk {
1350                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352
1353                         sdmmc_cmd: sdmmc-cmd {
1354                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1355                         };
1356
1357                         sdmmc_cd: sdmmc-cd {
1358                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1359                         };
1360
1361                         sdmmc_bus1: sdmmc-bus1 {
1362                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1363                         };
1364
1365                         sdmmc_bus4: sdmmc-bus4 {
1366                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1367                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1368                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1369                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1370                         };
1371                 };
1372
1373                 sdio0 {
1374                         sdio0_bus1: sdio0-bus1 {
1375                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1376                         };
1377
1378                         sdio0_bus4: sdio0-bus4 {
1379                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1380                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1381                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1382                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1383                         };
1384
1385                         sdio0_cmd: sdio0-cmd {
1386                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1387                         };
1388
1389                         sdio0_clk: sdio0-clk {
1390                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1391                         };
1392
1393                         sdio0_cd: sdio0-cd {
1394                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1395                         };
1396
1397                         sdio0_wp: sdio0-wp {
1398                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1399                         };
1400
1401                         sdio0_pwr: sdio0-pwr {
1402                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1403                         };
1404
1405                         sdio0_bkpwr: sdio0-bkpwr {
1406                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1407                         };
1408
1409                         sdio0_int: sdio0-int {
1410                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1411                         };
1412                 };
1413
1414                 sdio1 {
1415                         sdio1_bus1: sdio1-bus1 {
1416                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1417                         };
1418
1419                         sdio1_bus4: sdio1-bus4 {
1420                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1421                                                 <3 25 4 &pcfg_pull_up>,
1422                                                 <3 26 4 &pcfg_pull_up>,
1423                                                 <3 27 4 &pcfg_pull_up>;
1424                         };
1425
1426                         sdio1_cd: sdio1-cd {
1427                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1428                         };
1429
1430                         sdio1_wp: sdio1-wp {
1431                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1432                         };
1433
1434                         sdio1_bkpwr: sdio1-bkpwr {
1435                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1436                         };
1437
1438                         sdio1_int: sdio1-int {
1439                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1440                         };
1441
1442                         sdio1_cmd: sdio1-cmd {
1443                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1444                         };
1445
1446                         sdio1_clk: sdio1-clk {
1447                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1448                         };
1449
1450                         sdio1_pwr: sdio1-pwr {
1451                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1452                         };
1453                 };
1454
1455                 emmc {
1456                         emmc_clk: emmc-clk {
1457                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1458                         };
1459
1460                         emmc_cmd: emmc-cmd {
1461                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1462                         };
1463
1464                         emmc_pwr: emmc-pwr {
1465                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1466                         };
1467
1468                         emmc_bus1: emmc-bus1 {
1469                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1470                         };
1471
1472                         emmc_bus4: emmc-bus4 {
1473                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1474                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1475                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1476                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1477                         };
1478
1479                         emmc_bus8: emmc-bus8 {
1480                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1481                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1482                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1483                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1484                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1485                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1486                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1487                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1488                         };
1489                 };
1490
1491                 spi0 {
1492                         spi0_clk: spi0-clk {
1493                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1494                         };
1495                         spi0_cs0: spi0-cs0 {
1496                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1497                         };
1498                         spi0_tx: spi0-tx {
1499                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1500                         };
1501                         spi0_rx: spi0-rx {
1502                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1503                         };
1504                         spi0_cs1: spi0-cs1 {
1505                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1506                         };
1507                 };
1508                 spi1 {
1509                         spi1_clk: spi1-clk {
1510                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1511                         };
1512                         spi1_cs0: spi1-cs0 {
1513                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1514                         };
1515                         spi1_rx: spi1-rx {
1516                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1517                         };
1518                         spi1_tx: spi1-tx {
1519                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1520                         };
1521                 };
1522
1523                 spi2 {
1524                         spi2_cs1: spi2-cs1 {
1525                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1526                         };
1527                         spi2_clk: spi2-clk {
1528                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1529                         };
1530                         spi2_cs0: spi2-cs0 {
1531                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1532                         };
1533                         spi2_rx: spi2-rx {
1534                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1535                         };
1536                         spi2_tx: spi2-tx {
1537                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1538                         };
1539                 };
1540
1541                 uart0 {
1542                         uart0_xfer: uart0-xfer {
1543                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1544                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1545                         };
1546
1547                         uart0_cts: uart0-cts {
1548                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1549                         };
1550
1551                         uart0_rts: uart0-rts {
1552                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1553                         };
1554                 };
1555
1556                 uart1 {
1557                         uart1_xfer: uart1-xfer {
1558                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1559                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1560                         };
1561
1562                         uart1_cts: uart1-cts {
1563                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1564                         };
1565
1566                         uart1_rts: uart1-rts {
1567                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 uart2 {
1572                         uart2_xfer: uart2-xfer {
1573                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1574                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1575                         };
1576                         /* no rts / cts for uart2 */
1577                 };
1578
1579                 uart3 {
1580                         uart3_xfer: uart3-xfer {
1581                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1582                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584
1585                         uart3_cts: uart3-cts {
1586                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1587                         };
1588
1589                         uart3_rts: uart3-rts {
1590                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1591                         };
1592                 };
1593
1594                 uart4 {
1595                         uart4_xfer: uart4-xfer {
1596                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1597                                                 <5 13 3 &pcfg_pull_none>;
1598                         };
1599
1600                         uart4_cts: uart4-cts {
1601                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1602                         };
1603
1604                         uart4_rts: uart4-rts {
1605                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1606                         };
1607                 };
1608
1609                 tsadc {
1610                         otp_gpio: otp-gpio {
1611                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1612                         };
1613
1614                         otp_out: otp-out {
1615                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617                 };
1618
1619                 pwm0 {
1620                         pwm0_pin: pwm0-pin {
1621                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1622                         };
1623                 };
1624
1625                 pwm1 {
1626                         pwm1_pin: pwm1-pin {
1627                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1628                         };
1629                 };
1630
1631                 pwm2 {
1632                         pwm2_pin: pwm2-pin {
1633                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1634                         };
1635                 };
1636
1637                 pwm3 {
1638                         pwm3_pin: pwm3-pin {
1639                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1640                         };
1641                 };
1642
1643                 gmac {
1644                         rgmii_pins: rgmii-pins {
1645                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1646                                                 <3 31 3 &pcfg_pull_none>,
1647                                                 <3 26 3 &pcfg_pull_none>,
1648                                                 <3 27 3 &pcfg_pull_none>,
1649                                                 <3 28 3 &pcfg_pull_none_12ma>,
1650                                                 <3 29 3 &pcfg_pull_none_12ma>,
1651                                                 <3 24 3 &pcfg_pull_none_12ma>,
1652                                                 <3 25 3 &pcfg_pull_none_12ma>,
1653                                                 <4 0 3 &pcfg_pull_none>,
1654                                                 <4 5 3 &pcfg_pull_none>,
1655                                                 <4 6 3 &pcfg_pull_none>,
1656                                                 <4 9 3 &pcfg_pull_none_12ma>,
1657                                                 <4 4 3 &pcfg_pull_none_12ma>,
1658                                                 <4 1 3 &pcfg_pull_none>,
1659                                                 <4 3 3 &pcfg_pull_none>;
1660                         };
1661
1662                         rmii_pins: rmii-pins {
1663                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1664                                                 <3 31 3 &pcfg_pull_none>,
1665                                                 <3 28 3 &pcfg_pull_none>,
1666                                                 <3 29 3 &pcfg_pull_none>,
1667                                                 <4 0 3 &pcfg_pull_none>,
1668                                                 <4 5 3 &pcfg_pull_none>,
1669                                                 <4 4 3 &pcfg_pull_none>,
1670                                                 <4 1 3 &pcfg_pull_none>,
1671                                                 <4 2 3 &pcfg_pull_none>,
1672                                                 <4 3 3 &pcfg_pull_none>;
1673                         };
1674                 };
1675
1676                 spdif {
1677                         spdif_tx: spdif-tx {
1678                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1679                         };
1680                 };
1681         };
1682 };