arch/arm/boot/dts/rk3066a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3066a-cru.h>
  10 #include <dt-bindings/power/rk3066-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3066a";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1416000 1300000
  29                                 1200000 1175000
  30                                 1008000 1125000
  31                                 816000  1125000
  32                                 600000  1100000
  33                                 504000  1100000
  34                                 312000  1075000
  35                         >;
  36                         clock-latency = <40000>;
  37                         clocks = <&cru ARMCLK>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x1>;
  44                 };
  45         };
  46
  47         sram: sram@10080000 {
  48                 compatible = "mmio-sram";
  49                 reg = <0x10080000 0x10000>;
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges = <0 0x10080000 0x10000>;
  53
  54                 smp-sram@0 {
  55                         compatible = "rockchip,rk3066-smp-sram";
  56                         reg = <0x0 0x50>;
  57                 };
  58         };
  59
  60         i2s0: i2s@10118000 {
  61                 compatible = "rockchip,rk3066-i2s";
  62                 reg = <0x10118000 0x2000>;
  63                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&i2s0_bus>;
  68                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
  69                 dma-names = "tx", "rx";
  70                 clock-names = "i2s_hclk", "i2s_clk";
  71                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
  72                 rockchip,playback-channels = <8>;
  73                 rockchip,capture-channels = <2>;
  74                 #sound-dai-cells = <0>;
  75                 status = "disabled";
  76         };
  77
  78         i2s1: i2s@1011a000 {
  79                 compatible = "rockchip,rk3066-i2s";
  80                 reg = <0x1011a000 0x2000>;
  81                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&i2s1_bus>;
  86                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
  87                 dma-names = "tx", "rx";
  88                 clock-names = "i2s_hclk", "i2s_clk";
  89                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
  90                 rockchip,playback-channels = <2>;
  91                 rockchip,capture-channels = <2>;
  92                 #sound-dai-cells = <0>;
  93                 status = "disabled";
  94         };
  95
  96         i2s2: i2s@1011c000 {
  97                 compatible = "rockchip,rk3066-i2s";
  98                 reg = <0x1011c000 0x2000>;
  99                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&i2s2_bus>;
 104                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 105                 dma-names = "tx", "rx";
 106                 clock-names = "i2s_hclk", "i2s_clk";
 107                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 108                 rockchip,playback-channels = <2>;
 109                 rockchip,capture-channels = <2>;
 110                 #sound-dai-cells = <0>;
 111                 status = "disabled";
 112         };
 113
 114         cru: clock-controller@20000000 {
 115                 compatible = "rockchip,rk3066a-cru";
 116                 reg = <0x20000000 0x1000>;
 117                 rockchip,grf = <&grf>;
 118
 119                 #clock-cells = <1>;
 120                 #reset-cells = <1>;
 121                 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 122                                   <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 123                                   <&cru PCLK_CPU>, <&cru ACLK_PERI>,
 124                                   <&cru HCLK_PERI>, <&cru PCLK_PERI>;
 125                 assigned-clock-rates = <400000000>, <594000000>,
 126                                        <300000000>, <150000000>,
 127                                        <75000000>, <300000000>,
 128                                        <150000000>, <75000000>;
 129         };
 130
 131         timer@2000e000 {
 132                 compatible = "snps,dw-apb-timer-osc";
 133                 reg = <0x2000e000 0x100>;
 134                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 135                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 136                 clock-names = "timer", "pclk";
 137         };
 138
 139         efuse: efuse@20010000 {
 140                 compatible = "rockchip,rk3066a-efuse";
 141                 reg = <0x20010000 0x4000>;
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 clocks = <&cru PCLK_EFUSE>;
 145                 clock-names = "pclk_efuse";
 146
 147                 cpu_leakage: cpu_leakage@17 {
 148                         reg = <0x17 0x1>;
 149                 };
 150         };
 151
 152         timer@20038000 {
 153                 compatible = "snps,dw-apb-timer-osc";
 154                 reg = <0x20038000 0x100>;
 155                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 157                 clock-names = "timer", "pclk";
 158         };
 159
 160         timer@2003a000 {
 161                 compatible = "snps,dw-apb-timer-osc";
 162                 reg = <0x2003a000 0x100>;
 163                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 164                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 165                 clock-names = "timer", "pclk";
 166         };
 167
 168         tsadc: tsadc@20060000 {
 169                 compatible = "rockchip,rk3066-tsadc";
 170                 reg = <0x20060000 0x100>;
 171                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 172                 clock-names = "saradc", "apb_pclk";
 173                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 174                 #io-channel-cells = <1>;
 175                 resets = <&cru SRST_TSADC>;
 176                 reset-names = "saradc-apb";
 177                 status = "disabled";
 178         };
 179
 180         usbphy: phy {
 181                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 182                 rockchip,grf = <&grf>;
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 status = "disabled";
 186
 187                 usbphy0: usb-phy@17c {
 188                         #phy-cells = <0>;
 189                         reg = <0x17c>;
 190                         clocks = <&cru SCLK_OTGPHY0>;
 191                         clock-names = "phyclk";
 192                         #clock-cells = <0>;
 193                 };
 194
 195                 usbphy1: usb-phy@188 {
 196                         #phy-cells = <0>;
 197                         reg = <0x188>;
 198                         clocks = <&cru SCLK_OTGPHY1>;
 199                         clock-names = "phyclk";
 200                         #clock-cells = <0>;
 201                 };
 202         };
 203
 204         pinctrl: pinctrl {
 205                 compatible = "rockchip,rk3066a-pinctrl";
 206                 rockchip,grf = <&grf>;
 207                 #address-cells = <1>;
 208                 #size-cells = <1>;
 209                 ranges;
 210
 211                 gpio0: gpio0@20034000 {
 212                         compatible = "rockchip,gpio-bank";
 213                         reg = <0x20034000 0x100>;
 214                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&cru PCLK_GPIO0>;
 216
 217                         gpio-controller;
 218                         #gpio-cells = <2>;
 219
 220                         interrupt-controller;
 221                         #interrupt-cells = <2>;
 222                 };
 223
 224                 gpio1: gpio1@2003c000 {
 225                         compatible = "rockchip,gpio-bank";
 226                         reg = <0x2003c000 0x100>;
 227                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 228                         clocks = <&cru PCLK_GPIO1>;
 229
 230                         gpio-controller;
 231                         #gpio-cells = <2>;
 232
 233                         interrupt-controller;
 234                         #interrupt-cells = <2>;
 235                 };
 236
 237                 gpio2: gpio2@2003e000 {
 238                         compatible = "rockchip,gpio-bank";
 239                         reg = <0x2003e000 0x100>;
 240                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&cru PCLK_GPIO2>;
 242
 243                         gpio-controller;
 244                         #gpio-cells = <2>;
 245
 246                         interrupt-controller;
 247                         #interrupt-cells = <2>;
 248                 };
 249
 250                 gpio3: gpio3@20080000 {
 251                         compatible = "rockchip,gpio-bank";
 252                         reg = <0x20080000 0x100>;
 253                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&cru PCLK_GPIO3>;
 255
 256                         gpio-controller;
 257                         #gpio-cells = <2>;
 258
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio4: gpio4@20084000 {
 264                         compatible = "rockchip,gpio-bank";
 265                         reg = <0x20084000 0x100>;
 266                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 267                         clocks = <&cru PCLK_GPIO4>;
 268
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271
 272                         interrupt-controller;
 273                         #interrupt-cells = <2>;
 274                 };
 275
 276                 gpio6: gpio6@2000a000 {
 277                         compatible = "rockchip,gpio-bank";
 278                         reg = <0x2000a000 0x100>;
 279                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&cru PCLK_GPIO6>;
 281
 282                         gpio-controller;
 283                         #gpio-cells = <2>;
 284
 285                         interrupt-controller;
 286                         #interrupt-cells = <2>;
 287                 };
 288
 289                 pcfg_pull_default: pcfg_pull_default {
 290                         bias-pull-pin-default;
 291                 };
 292
 293                 pcfg_pull_none: pcfg_pull_none {
 294                         bias-disable;
 295                 };
 296
 297                 emac {
 298                         emac_xfer: emac-xfer {
 299                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 300                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 301                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 302                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 303                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 304                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 305                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 306                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 307                         };
 308
 309                         emac_mdio: emac-mdio {
 310                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 311                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 312                         };
 313                 };
 314
 315                 emmc {
 316                         emmc_clk: emmc-clk {
 317                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 318                         };
 319
 320                         emmc_cmd: emmc-cmd {
 321                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 322                         };
 323
 324                         emmc_rst: emmc-rst {
 325                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 326                         };
 327
 328                         /*
 329                          * The data pins are shared between nandc and emmc and
 330                          * not accessible through pinctrl. Also they should've
 331                          * been already set correctly by firmware, as
 332                          * flash/emmc is the boot-device.
 333                          */
 334                 };
 335
 336                 i2c0 {
 337                         i2c0_xfer: i2c0-xfer {
 338                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 339                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 340                         };
 341                 };
 342
 343                 i2c1 {
 344                         i2c1_xfer: i2c1-xfer {
 345                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 346                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 347                         };
 348                 };
 349
 350                 i2c2 {
 351                         i2c2_xfer: i2c2-xfer {
 352                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 353                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 354                         };
 355                 };
 356
 357                 i2c3 {
 358                         i2c3_xfer: i2c3-xfer {
 359                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 360                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 361                         };
 362                 };
 363
 364                 i2c4 {
 365                         i2c4_xfer: i2c4-xfer {
 366                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 367                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 368                         };
 369                 };
 370
 371                 pwm0 {
 372                         pwm0_out: pwm0-out {
 373                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 374                         };
 375                 };
 376
 377                 pwm1 {
 378                         pwm1_out: pwm1-out {
 379                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 380                         };
 381                 };
 382
 383                 pwm2 {
 384                         pwm2_out: pwm2-out {
 385                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 386                         };
 387                 };
 388
 389                 pwm3 {
 390                         pwm3_out: pwm3-out {
 391                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 392                         };
 393                 };
 394
 395                 spi0 {
 396                         spi0_clk: spi0-clk {
 397                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 398                         };
 399                         spi0_cs0: spi0-cs0 {
 400                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 401                         };
 402                         spi0_tx: spi0-tx {
 403                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 404                         };
 405                         spi0_rx: spi0-rx {
 406                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 407                         };
 408                         spi0_cs1: spi0-cs1 {
 409                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 410                         };
 411                 };
 412
 413                 spi1 {
 414                         spi1_clk: spi1-clk {
 415                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 416                         };
 417                         spi1_cs0: spi1-cs0 {
 418                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 419                         };
 420                         spi1_rx: spi1-rx {
 421                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 422                         };
 423                         spi1_tx: spi1-tx {
 424                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 425                         };
 426                         spi1_cs1: spi1-cs1 {
 427                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 428                         };
 429                 };
 430
 431                 uart0 {
 432                         uart0_xfer: uart0-xfer {
 433                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 434                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 435                         };
 436
 437                         uart0_cts: uart0-cts {
 438                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 439                         };
 440
 441                         uart0_rts: uart0-rts {
 442                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 443                         };
 444                 };
 445
 446                 uart1 {
 447                         uart1_xfer: uart1-xfer {
 448                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 449                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 450                         };
 451
 452                         uart1_cts: uart1-cts {
 453                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 454                         };
 455
 456                         uart1_rts: uart1-rts {
 457                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 458                         };
 459                 };
 460
 461                 uart2 {
 462                         uart2_xfer: uart2-xfer {
 463                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 464                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 465                         };
 466                         /* no rts / cts for uart2 */
 467                 };
 468
 469                 uart3 {
 470                         uart3_xfer: uart3-xfer {
 471                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 472                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 473                         };
 474
 475                         uart3_cts: uart3-cts {
 476                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 477                         };
 478
 479                         uart3_rts: uart3-rts {
 480                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 481                         };
 482                 };
 483
 484                 sd0 {
 485                         sd0_clk: sd0-clk {
 486                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 487                         };
 488
 489                         sd0_cmd: sd0-cmd {
 490                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 491                         };
 492
 493                         sd0_cd: sd0-cd {
 494                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 495                         };
 496
 497                         sd0_wp: sd0-wp {
 498                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 499                         };
 500
 501                         sd0_bus1: sd0-bus-width1 {
 502                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 503                         };
 504
 505                         sd0_bus4: sd0-bus-width4 {
 506                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 507                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 508                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 509                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 510                         };
 511                 };
 512
 513                 sd1 {
 514                         sd1_clk: sd1-clk {
 515                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 516                         };
 517
 518                         sd1_cmd: sd1-cmd {
 519                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 520                         };
 521
 522                         sd1_cd: sd1-cd {
 523                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 524                         };
 525
 526                         sd1_wp: sd1-wp {
 527                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 528                         };
 529
 530                         sd1_bus1: sd1-bus-width1 {
 531                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 532                         };
 533
 534                         sd1_bus4: sd1-bus-width4 {
 535                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 536                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 537                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 538                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 539                         };
 540                 };
 541
 542                 i2s0 {
 543                         i2s0_bus: i2s0-bus {
 544                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 545                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 546                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 547                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 548                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 549                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 550                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 551                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 552                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 553                         };
 554                 };
 555
 556                 i2s1 {
 557                         i2s1_bus: i2s1-bus {
 558                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 559                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 560                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 561                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 562                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 563                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 564                         };
 565                 };
 566
 567                 i2s2 {
 568                         i2s2_bus: i2s2-bus {
 569                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 570                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 571                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 572                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 573                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 574                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 575                         };
 576                 };
 577         };
 578 };
 579
 580 &gpu {
 581         compatible = "rockchip,rk3066-mali", "arm,mali-400";
 582         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 583                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 584                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 585                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 586                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 587                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 588                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 589                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 590                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 591                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 592         interrupt-names = "gp",
 593                           "gpmmu",
 594                           "pp0",
 595                           "ppmmu0",
 596                           "pp1",
 597                           "ppmmu1",
 598                           "pp2",
 599                           "ppmmu2",
 600                           "pp3",
 601                           "ppmmu3";
 602         power-domains = <&power RK3066_PD_GPU>;
 603 };
 604
 605 &i2c0 {
 606         pinctrl-names = "default";
 607         pinctrl-0 = <&i2c0_xfer>;
 608 };
 609
 610 &i2c1 {
 611         pinctrl-names = "default";
 612         pinctrl-0 = <&i2c1_xfer>;
 613 };
 614
 615 &i2c2 {
 616         pinctrl-names = "default";
 617         pinctrl-0 = <&i2c2_xfer>;
 618 };
 619
 620 &i2c3 {
 621         pinctrl-names = "default";
 622         pinctrl-0 = <&i2c3_xfer>;
 623 };
 624
 625 &i2c4 {
 626         pinctrl-names = "default";
 627         pinctrl-0 = <&i2c4_xfer>;
 628 };
 629
 630 &mmc0 {
 631         clock-frequency = <50000000>;
 632         dmas = <&dmac2 1>;
 633         dma-names = "rx-tx";
 634         max-frequency = <50000000>;
 635         pinctrl-names = "default";
 636         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 637 };
 638
 639 &mmc1 {
 640         dmas = <&dmac2 3>;
 641         dma-names = "rx-tx";
 642         pinctrl-names = "default";
 643         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 644 };
 645
 646 &emmc {
 647         dmas = <&dmac2 4>;
 648         dma-names = "rx-tx";
 649 };
 650
 651 &pmu {
 652         power: power-controller {
 653                 compatible = "rockchip,rk3066-power-controller";
 654                 #power-domain-cells = <1>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657
 658                 pd_vio@RK3066_PD_VIO {
 659                         reg = <RK3066_PD_VIO>;
 660                         clocks = <&cru ACLK_LCDC0>,
 661                                  <&cru ACLK_LCDC1>,
 662                                  <&cru DCLK_LCDC0>,
 663                                  <&cru DCLK_LCDC1>,
 664                                  <&cru HCLK_LCDC0>,
 665                                  <&cru HCLK_LCDC1>,
 666                                  <&cru SCLK_CIF1>,
 667                                  <&cru ACLK_CIF1>,
 668                                  <&cru HCLK_CIF1>,
 669                                  <&cru SCLK_CIF0>,
 670                                  <&cru ACLK_CIF0>,
 671                                  <&cru HCLK_CIF0>,
 672                                  <&cru ACLK_IPP>,
 673                                  <&cru HCLK_IPP>,
 674                                  <&cru ACLK_RGA>,
 675                                  <&cru HCLK_RGA>;
 676                         pm_qos = <&qos_lcdc0>,
 677                                  <&qos_lcdc1>,
 678                                  <&qos_cif0>,
 679                                  <&qos_cif1>,
 680                                  <&qos_ipp>,
 681                                  <&qos_rga>;
 682                 };
 683
 684                 pd_video@RK3066_PD_VIDEO {
 685                         reg = <RK3066_PD_VIDEO>;
 686                         clocks = <&cru ACLK_VDPU>,
 687                                  <&cru ACLK_VEPU>,
 688                                  <&cru HCLK_VDPU>,
 689                                  <&cru HCLK_VEPU>;
 690                         pm_qos = <&qos_vpu>;
 691                 };
 692
 693                 pd_gpu@RK3066_PD_GPU {
 694                         reg = <RK3066_PD_GPU>;
 695                         clocks = <&cru ACLK_GPU>;
 696                         pm_qos = <&qos_gpu>;
 697                 };
 698         };
 699 };
 700
 701 &pwm0 {
 702         pinctrl-names = "default";
 703         pinctrl-0 = <&pwm0_out>;
 704 };
 705
 706 &pwm1 {
 707         pinctrl-names = "default";
 708         pinctrl-0 = <&pwm1_out>;
 709 };
 710
 711 &pwm2 {
 712         pinctrl-names = "default";
 713         pinctrl-0 = <&pwm2_out>;
 714 };
 715
 716 &pwm3 {
 717         pinctrl-names = "default";
 718         pinctrl-0 = <&pwm3_out>;
 719 };
 720
 721 &spi0 {
 722         pinctrl-names = "default";
 723         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 724 };
 725
 726 &spi1 {
 727         pinctrl-names = "default";
 728         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 729 };
 730
 731 &uart0 {
 732         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 733         dmas = <&dmac1_s 0>, <&dmac1_s 1>;
 734         dma-names = "tx", "rx";
 735         pinctrl-names = "default";
 736         pinctrl-0 = <&uart0_xfer>;
 737 };
 738
 739 &uart1 {
 740         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 741         dmas = <&dmac1_s 2>, <&dmac1_s 3>;
 742         dma-names = "tx", "rx";
 743         pinctrl-names = "default";
 744         pinctrl-0 = <&uart1_xfer>;
 745 };
 746
 747 &uart2 {
 748         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 749         dmas = <&dmac2 6>, <&dmac2 7>;
 750         dma-names = "tx", "rx";
 751         pinctrl-names = "default";
 752         pinctrl-0 = <&uart2_xfer>;
 753 };
 754
 755 &uart3 {
 756         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 757         dmas = <&dmac2 8>, <&dmac2 9>;
 758         dma-names = "tx", "rx";
 759         pinctrl-names = "default";
 760         pinctrl-0 = <&uart3_xfer>;
 761 };
 762
 763 &wdt {
 764         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 765 };
 766
 767 &emac {
 768         compatible = "rockchip,rk3066-emac";
 769 };